AD1849K

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a SoundPort Stereo Codec AD1849K

FEATURES

Single-Chip Integrated SD Digital Audio Stereo Codec Multiple Channels of Stereo Input and Output

Digital Signal Mixing

On-Chip Speaker and Headphone Drive Capability Programmable Gain and Attenuation

On-Chip Signal Filters

Digital Interpolation and Decimation Analog Output Low-Pass

Sample Rates from 5.5 kHz to 48 kHz 44-Lead PLCC and TQFP Packages

Operation from +5 V and Mixed +5 V/+3.3 V Supplies Serial Interface Compatible with ADSP-21xx Fixed-

Point DSmPs

Compatible with CS4215 (See Text)

speaker and stereo headphone drive circuits that require no additional external components. Dynamic range exceeds 80 dB over the 20 kHz audio band. Sample rates from 5.5 kHz to 48 kHz are supported from external crystals, from an external clock, or from the serial interface bit clock.

The Codec includes a stereo pair of Σ∆ analog-to-digital converters and a stereo pair of Σ∆ digital-to-analog converters.

Analog signals can be input at line levels or microphone levels.

A software controlled programmable gain stage allows independent gain for each channel going into the ADC. The ADCs’ output can be digitally mixed with the DACs’ input.

The left and right channel 16-bit outputs from the ADCs are available over a single bidirectional serial interface that also supports 16-bit digital input to the DACs and control information.

The AD1849K can accept and generate 8-bit µ-law or A-law companded digital data.

The Σ∆ DACs are preceded by a digital interpolation filter. An attenuator provides independent user volume control over each DAC channel. Nyquist images and shaped quantization noise are removed from the DACs’ analog stereo output by on-chip switched-capacitor and continuous-time filters. Two independent stereo pairs of line-level (or one line-level and one headphone) outputs are generated, as well as drive for a monaural (mono) speaker.

(Continued on page 8) FUNCTIONAL BLOCK DIAGRAM

MUX

ANALOG IN

CRYSTALS ANALOG

SUPPLY

DIGITAL

SUPPLY POWER DOWN

LINE L LINE R

MIC L MIC R

L

R GAIN

OSCILLATORS

MUTE

∑∆ A/D CONVERTER

∑∆ A/D CONVERTER GAIN

2 2

LINE 0 L

LINE 1 L HEADPHONE RETURN ANALOG

OUT

∑

∑ MONITOR MIX

ATTENUATE

∑

∑∆ D/A CONVERTER

INTERPOL

INTERPOL ATTENUATE ATTENUATE

ATTENUATE ANALOG

FILTER

ANALOG FILTER LOOPBACK

L

R 20 dB

LINE 0 R

S E R I A L P O R T

L O O P B A C K

DATA/CONTROL MODE DATA/CONTROL TRANSMIT

2

DATA/CONTROL RECEIVE PARALLEL I/O BIT CLOCK FRAME SYNC

DIGITAL I/O

AD1849K

µ/A LAW

MUTE L

R MUTE

PRODUCT OVERVIEW

The Serial-Port AD1849K SoundPort® Stereo Codec integrates the key audio data conversion and control functions into a single integrated circuit. The AD1849K is intended to provide a complete, single-chip audio solution for multimedia applications requiring operation from a single +5 V supply. External signal path circuit requirements are limited to three low tolerance capacitors for line level applications; anti-imaging filters are incorporated on-chip. The AD1849K includes on-chip monaural

SoundPort is a registered trademark of Analog Devices, Inc.

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AD1849K–SPECIFICATIONS

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ELECTRICAL SPECIFICATIONS

STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED

Temperature 25 °C DAC Input Conditions

Digital Supply (V_DD) 5.0 V 0 dB Attenuation

Analog Supply (VCC) 5.0 V Full-Scale Digital Inputs

Clock (SCLK) 256 F_S 16-Bit Linear Mode

Master Mode 256 Bits per Frame OLB = 1

Word Rate (F_S) 48 kHz ADC Input Conditions

Input Signal 1 kHz 0 dB PGA Gain

Analog Output Passband 20 Hz to 20 kHz –3.0 dB Relative to Full Scale

VIH 2.4 V Line Input

V_IL 0.8 V 16-Bit Linear Mode

External Load Impedance 10 kΩ

(Line 0) All tests are performed on all ADC and DAC channels.

External Load Impedance 48 Ω

(Line 1)

External Load Capacitance 100 pF

(Line 0, 1) ANALOG INPUT

Min Typ Max Units

Input Voltage*

(RMS Values Assume Sine Wave Input)

Line and Mic with 0 dB Gain 0 94 0.99 1.04 V rms

2.66 2.80 2.94 V p-p

Mic with +20 dB Gain 0.094 0.099 0.104 V rms

0.266 0.280 0.294 V p-p

Input Capacitance 15 pF

*Accounts for Sum of Worst Case Reference Errors and Worst Case Gain Errors.

PROGRAMMABLE GAIN AMPLIFIER—ADC

Step Size (0 dB to 22.5 dB) 1.3 1.5 1.7 dB

(All Steps Tested, –30 dB Input) PGA Gain Range*

Line and Mic with 0 dB Gain –0.2 22.7 dB

Mic with +20 dB Gain 19.8 42.7 dB

DIGITAL DECIMATION AND INTERPOLATION FILTERS*

Min Max Units

Passband 0 0.45 × F_S Hz

Passband Ripple ±0.1 dB

Transition Band 0.45 × F_S 0.55 × F_S Hz

Stopband ≥0.55 × FS Hz

Stopband Rejection 74 dB

Group Delay 30/FS

Group Delay Variation Over Passband 0.0 µs

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ANALOG-TO-DIGITAL CONVERTERS

Resolution* 16 Bits

ADC Dynamic Range, A-Weighted 78 83 dB

Line and Mic with 0 dB Gain (–60 dB Input, THD+N Referenced to Full Scale)

Mic with +20 dB Gain (–60 dB Input, 72 74 dB

THD+N Referenced to Full Scale) ADC THD+N, (Referenced to Full Scale)

Line and Mic with 0 dB Gain 0.013 0.020 %

–78 –74 dB

Mic with +20 dB Gain 0.032 0.056 %

–70 –65 dB

ADC Crosstalk

Line to Line (Input L, Ground R, –80 dB

Read R; Input R, Ground L, Read L)

Line to Mic (Input LINL & R, –60 dB

Ground and Select MINL & R, Read Both Channels)

Gain Error (Full-Scale Span Relative to Nominal) 0.75 dB

ADC Interchannel Gain Mismatch (Line and Mic) 0.3 dB

(Difference of Gain Errors)

DIGITAL-TO-ANALOG CONVERTERS

Resolution* 16 Bits

DAC Dynamic Range

(–60 dB Input, THD+N Referenced 80 86 dB

to Full Scale)

DAC THD+N (Referenced to Full Scale)

Line 0 and 1 (10 kΩ Load) 0.010 0.020 %

–80 –74 dB

Line 1 (48 Ω Load) 0.022 0.100 %

–73 –60 dB

Mono Speaker (48 Ω Load) 0.045 0.100 %

–67 –60 dB

DAC Crosstalk (Input L, Zero R, Measure –80 dB

LOUT0R & 1R; Input R, Zero L, Measure LOUT0L & 1L)

Gain Error (Full-Scale Span Relative to Nominal) 0.75 dB

DAC Interchannel Gain Mismatch (Line 0 and 1) 0.3 dB

(Difference of Gain Errors)

Total Out-of-Band Energy* –60 dB

×

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MONITOR MIX ATTENUATOR

Step Size (0.0 dB to –60 dB)* 1.3 1.5 1.7 dB

Step Size (–61.5 dB to –94.5 dB)* 1.0 1.5 2.0 dB

Output Attenuation* –95 0.2 dB

DAC ATTENUATOR

Step Size (0.0 dB to –60 dB) 1.3 1.5 1.7 dB

(Tested at Steps –1.5 dB, –19.5 dB, –39 dB and –60 dB)

Step Size (–61.5 dB to –94.5 dB)* 1.0 1.5 2.0 dB

Output Attenuation* –95 0.2 dB

SYSTEM SPECIFICATIONS

System Frequency Response* –0.5 +0.2 dB

(Line In to Line Out, 0 to 0.45 × F_S)

Differential Nonlinearity* ±0.9 LSB

Phase Linearity Deviation* 5 Degrees

ANALOG OUTPUT

Full-Scale Output Voltage (Line 0 & 1) 0.707 V rms

[OLB = 1] 1.85 2.0 2.1 V p-p

Full-Scale Output Voltage (Line 0) 1.0 V rms

[OLB = 0] 2.8 V p-p

Full-Scale Output Voltage (Line 1) 4.0 V p-p

[OLB = 0]

Full-Scale Output Voltage (Mono Speaker) 4.0 V p-p

[OLB = 1]

Full-Scale Output Voltage (Mono Speaker) 8.0 V p-p

[OLB = 0]

CMOUT Voltage (No Load) 1.80 2.25 2.50 V

CMOUT Current Drive* 100 µA

CMOUT Output Impedance 4 kΩ

Mute Attenuation of 0 dB –80 dB

Fundamental* (LINE 0, 1, & MONO)

STATIC DIGITAL SPECIFICATIONS

High Level Input Voltage (V_IH)

Digital Inputs 2.4 (VDD+) + 0.3 V

XTAL1/2I 2.4 (V_DD+) + 0.3 V

Low Level Input Voltage (V_IL) –0.3 0.8 V

High Level Output Voltage (V_OH) at I_OH = –2 mA 2.4 V

Low Level Output Voltage (VOL) at IOL = 2 mA 0.4 V

Input Leakage Current –10 10 µA

(GO/NOGO Tested)

Output Leakage Current –10 10 µA

(GO/NOGO Tested)

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DIGITAL TIMING PARAMETERS (Guaranteed over +4.75 V to +5.25 V, 08C to +708C)

SCLK Period (tCLK)

Slave Mode, MS = 0 80 ns

Master Mode, MS = 1* 1/(F_S × Bits per Frame) s

SCLK HI (t_HI)*

SCLK LO (t_LO)*

CLKIN Frequency 13.5 MHz

CLKIN HI 30 ns

CLKIN LO 30 ns

Crystals Frequency 27

Input Setup Time (t_S) 15 ns

Input Hold Time (tIH) 10 ns

Output Delay (t_D) 25 ns

Output Hold Time (t_OH) 0 ns

Output Hi-Z to Valid (t_ZV) 15 ns

Output Valid to Hi-Z (tVZ) 20 ns

Power Up RESET LO Time 50 ms

Operating RESET LO Time 100 ns

POWER SUPPLY

Power Supply Voltage Range* 4.75 5.25 V

–Digital and Analog

Power Supply Current—Operating 100 130 mA

(50% I_VDD, 50% I_VCC, Unloaded Outputs)

Power Supply Current—Power Down 20 200 µA

Power Supply Rejection (@ 1 kHz)* 40 dB

(At Both Analog and Digital

Supply Pins, Both ADCs and DACs)

CLOCK SPECIFICATIONS*

Input Clock Frequency, Crystals 27 MHz

Clock Duty Cycle Tolerance ±10 %

Sample Rate (F_S) 5.5125 50 kHz

*Guaranteed, not tested.

Specifications subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS*

Power Supplies

Digital (V_DD) –0.3 6.0 V

Analog (V_CC) –0.3 6.0 V

Input Current

(Except Supply Pins and MOUT, ±10.0 mA MOUTR, LOUT1R, LOUT1L,

LOUT1C)

Analog Input Voltage (Signal Pins) –0.3 (V_CC+) + 0.3 V Digital Input Voltage (Signal Pins) –0.3 (V_DD+) + 0.3 V Ambient Temperature (Operating) 0 +70 °C

Storage Temperature –65 +150 °C

ESD Tolerance (Human Body 500 V

Model per Method 3015.2 of MIL-STD-883B)

WARNING: CMOS device. May be susceptible to high voltage transient-induced latchup.

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD1849KP 0°C to +70°C 44-Lead PLCC P-44A

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.

Although the AD1849K features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

44-Lead Plastic Leaded Chip Carrier Pinout

0.656 (16.66) 0.650 (16.51)SQ 0.695 (17.65) 0.685 (17.40)SQ 0.048 (1.21) 0.042 (1.07) 0.048 (1.21)

0.042 (1.07) ⁶ ⁴⁰

TOP VIEW 39

29 18

17 PIN 1 IDENTIFIER 7

28

0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42)

0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19)

0.63 (16.00) 0.59 (14.99)

0.110 (2.79) 0.085 (2.16)

0.040 (1.01) 0.025 (0.64) 0.050 (1.27) BSC

0.020 (0.50) R

PIN 1 IDENTIFIER

BOTTOM VIEW

44-Lead TQFP

AD1849KST SoundPort®

STEREO CODEC

23 24 25 26 27 28 29 30 31 32 33

V_DD

PIO0

N/C LOUT0R LOUT0L LOUT1L LOUT1C PIO1

LOUT1R GNDD 1

2 3 4 5 6 7 8 9 10 11 COUT1

GNDD

COUT2

PDN C0 MINR LINR MINL CIN2 V_DD

36 35 34

44 43 42 41 40 39 38 37

CIN1 CLKIN VDD GNDD SDRX SDTX SCLK FSYNCCLKOUT TSOUT TSIN

12 13 14 15 16 17 18 19 20 21 22

LINL C1 VREF GNDA

CMOUT VCC GNDA N/C MOUT MOUTR

VCC

N/C = NO CONNECT RESET

D/C

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PIN DESCRIPTION Digital Signals

Pin Name PLCC TQFP I/O Description

SDRX 1 39 I Receive Serial Data Pin

SDTX 44 38 O Transmit Serial Data Pin

SCLK 43 37 I/O Bidirectional Serial Bit Clock

FSYNC 42 36 O Frame Sync Output Signal

TSOUT 41 35 O Chaining Word Output

TSIN 40 34 I Chaining Word Input

D/C 35 29 I Data/Control Select Input

CIN1 6 44 I Crystal 1 Input

COUT1 7 1 O Crystal 1 Output

CIN2 10 4 I Crystal 2 Input

COUT2 11 5 O Crystal 2 Output

CLKIN 4 42 I External Sample Clock Input (256 × FS)

CLKOUT 5 43 O External Sample Clock Output (256 × F_S)

PDN 13 7 I Power Down Input (Active HI)

RESET 12 6 I Reset Input (Active LO)

PIO1 37 31 I/O Parallel Input/Output Bit 1

PIO0 36 30 I/O Parallel Input/Output Bit 0

Analog Signals

LINL 18 12 I Left Channel Line Input

LINR 16 10 I Right Channel Line Input

MINL 17 11 I Left Channel Microphone Input (–20 dB from Line Level if MB = 0 or Line Level if MB = 1)

MINR 15 9 I Right Channel Microphone Input (–20 dB from Line Level if MB = 0 or Line Level if MB = 1)

LOUT0L 32 26 O Left Channel Line Output 0

LOUT0R 33 27 O Right Channel Line Output 0

LOUT1L 31 25 O Left Channel Line Output 1

LOUT1R 29 23 O Right Channel Line Output 1

LOUT1C 30 24 I Common Return Path for Large Current from External Headphones

MOUT 27 21 O Mono Speaker Output

MOUTR 28 22 I Mono Speaker Output Return

C0 14 8 O External 1.0 µF Capacitor (±10%) Connection

C1 20 14 O External 1.0 µF Capacitor (±10%) Connection

N/C 26 20 No Connect (Do Not Connect)

N/C 34 28 No Connect (Do Not Connect)

V_REF 21 15 O Voltage Reference (Connect to Bypass Capacitor)

CMOUT 19 13 O Common Mode Reference Datum Output (Nominally 2.25 V)

Power Supplies

V_CC 23 & 24 17, 18 I Analog Supply Voltage (+5 V)

GNDA 22 & 25 16, 19 I Analog Ground

V_DD 3, 8, 38 41, 2, 32 I Digital Supply Voltage (+5 V)

GNDD 2, 9, 39 40, 3, 33 I Digital Ground

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(Continued from page 1)

FUNCTIONAL DESCRIPTION

This section overviews the functionality of the AD1849K and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. The user is not expected to refer repeatedly to this section.

Analog Inputs

The AD1849K SoundPort Stereo Codec accepts stereo line-level and mic-level inputs. These analog stereo signals are multiplexed to the internal programmable gain amplifier (PGA) stage. The mic inputs can be amplified by +20 dB prior to the PGA to compensate for the voltage swing difference between line levels and typical condenser microphones. The mic inputs can bypass the +20 dB fixed gain block and go straight to the input multiplexer, which often results in an improved system signal-to-noise ratio.

The PGA following the input multiplexer allows independent selectable gains for each channel from 0 to 22.5 dB in +1.5 dB steps. The Codec can operate either in a global stereo mode or in a global mono mode with left-channel inputs appearing at both channel outputs.

Analog-to-Digital Datapath

The AD1849K ∑∆ ADCs incorporate a proprietary fourth-order modulator. A single pole of passive filtering is all that is required for anti-aliasing the analog input because of the ADC’s high 64 times oversampling ratio. The ADCs include linear-phase digital decimation filters that low-pass filter the input to 0.45 × FS

(“F_S” is the word rate or “sampling frequency”). ADC input overrange conditions will cause a sticky bit to be set that can be read.

Digital-to-Analog Datapath

The ∑∆ DACs are preceded by a programmable attenuator and a low-pass digital interpolation filter. The attenuator allows independent control of each DAC channel from 0 dB to –94.5 dB in 1.5 dB steps plus full digital mute. The anti-imaging interpolation filter oversamples by 64 and digitally filters the higher frequency images. The DACs’ ∑∆ noise shapers also oversample by 64 and convert the signal to a single-bit stream. The DAC outputs are then filtered in the analog domain by a combination of switched-capacitor and continuous-time filters. They remove the very high frequency components of the DAC bitstream output, including both images at the oversampling rate and shaped quantization noise. No external components are required.

Phase linearity at the analog output is achieved by internally compensating for the group delay variation of the analog output filters.

Attenuation settings are specified by control bits in the data stream. Changes in DAC output level take effect only on zero crossings of the digital signal, thereby eliminating “zipper”

noise. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guarantees that requested volume changes will occur even in the absence of an input signal that changes sign. The time-out period is 10.7 milliseconds at a 48 kHz sampling rate and 64 milliseconds at an 8 kHz sampling rate (Time-out [ms] ≈ 512/

Sampling Rate [kHz]).

Monitor Mix

A monitor mix is supported that digitally mixes a portion of the digitized analog input with the analog output (prior to digitiza- tion). The digital output from the ADCs going out of the serial data port is unaffected by the monitor mix. Along the monitor mix datapath, the 16-bit linear output from the ADCs is attenuated by an amount specified with control bits. Both channels of the monitor data are attenuated by the same amount. (Note that internally the AD1849K always works with 16-bit PCM linear data, digital mixing included; format conversions take place at the input and output.)

Sixteen steps of –6 dB attenuation are supported to –94.5 dB. A

“0” implies no attenuation, while a “14” implies 84 dB of attenuation. Specifying full scale “15” completely mutes the monitor datapath, preventing any mixing of the analog input with the digital input. Note that the level of the mixed output signal is also a function of the input PGA settings since they affect the ADCs’ output.

The attenuated monitor data is digitally summed with the DAC input data prior to the DACs’ datapath attenuators. Because both stereo signals are mixed before the output attenuators, mix data is attenuated a second time by the DACs’ datapath attenuators. The digital sum of digital mix data and DAC input data is clipped at plus or minus full scale and does not wrap around.

Analog Outputs

One stereo line-level output, one stereo headphone output, and one monaural (mono) speaker output are available at external pins. Each of these outputs can be independently muted.

Muting either the line-level stereo output or the headphone stereo output mutes both left and right channels of that output.

When muted, the outputs will settle to a dc value near CMOUT, the midscale reference voltage. The mono speaker output is differential. The chip can operate either in a global stereo mode or in a global mono mode with left channel inputs appearing at both outputs.

Digital Data Types

The AD1849K supports four global data types: 16-bit twos- complement linear PCM, 8-bit unsigned linear PCM, 8-bit companded µ-law, and 8-bit companded A-law, as specified by control register bits. Data in all four formats is always trans- ferred MSB first. Sixteen-bit linear data output from the ADCs and input to the DACs is in twos-complement format. Eight-bit data is always left-justified in 16-bit fields; in other words, the MSBs of all data types are always aligned; in yet other words, full-scale representations in all three formats correspond to equivalent full-scale signals. The eight least-significant bit positions of 8-bit linear and companded data in 16-bit fields are ignored on input and zeroed on output.

The 16-bit PCM data format is capable of representing 96 dB of dynamic range. Eight-bit PCM can represent 48 dB of dynamic range. Companded µ-law and A-law data formats use nonlinear coding with less precision for large-amplitude signals. The loss of precision is compensated for by an increase in dynamic range to 64 dB and 72 dB, respectively.

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On input, 8-bit companded data is expanded to an internal linear representation, according to whether µ-law or A-law was specified in the Codec’s internal registers. Note that when µ-law compressed data is expanded to a linear format, it requires 14 bits. A-law data expanded requires 13 bits, see Figure 1.

3/2 2/1

15 0

MSB

0 0 0 / 0 0

15 0

DAC INPUT MSB EXPANSION COMPRESSED INPUT DATA

3/2 2/1 LSB

LSB 8 7 LSB

Figure 1. A-Law or µ-Law Expansion

When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified prior to output. See Figure 2.

Note that all format conversions take place at input or output.

Internally, the AD1849K always uses 16-bit linear PCM representations to maintain maximum precision.

LSB

3/2 2/1

15 0

MSB

0 0 0 0 0 0 0 0

15 0

MSB ADC OUTPUT

TRUNCATION

COMPRESSION

LSB

8 7 LSB

Figure 2. A-Law or µ-Law Compression Power Supplies and Voltage Reference

The AD1849K operates from +5 V power supplies. Independent analog and digital supplies are recommended for optimal performance, though excellent results can be obtained in single supply systems. A voltage reference is included on the Codec and its 2.25 V buffered output is available on an external pin (CMOUT). The CMOUT output can be used for biasing op amps used in dc coupling. The internal reference is externally bypassed to analog ground at the V_REF pin. Note that V_REF should only be connected to its bypass capacitors.

Autocalibration

The AD1849K supports an autocalibration sequence to eliminate DAC and ADC offsets. The autocalibration sequence is initiated in the transition from Control Mode to Data Mode, regardless of the state of the AC bit. The user should specify that analog outputs be muted to prevent undesired outputs.

Monitor mix will be automatically disabled by the Codec.

During the autocalibration sequence, the serial data output from the ADCs is meaningless and the ADI bit is asserted. Serial data inputs to the DACs are ignored. Even if the user specified the muting of all analog outputs, near the end of the autocalibration sequence, dc analog outputs very close to CMOUT will be produced at the line outputs and mono speaker output.

An autocalibration sequence is also performed when the AD1849K leaves the reset state (i.e., RESET goes HI). The RESET pin should be held LO for 50 ms after power up or after leaving power-down mode to delay the onset of the autocalibration sequence until after the voltage reference has settled.

Loopback

Digital and analog loopback modes are supported for device and system testing. The monitor mix datapath is always available for loopback test purposes. Additional loopback tests are enabled by setting the ENL bit (Control Word Bit 33) to a “1.”

Analog loopback mode D-A-D is enabled by setting the ADL bit (Control Word Bit 32) to a “1” when ENL is a “1.” In this mode, the DACs’ analog outputs are re-input to the PGAs prior to the ADCs, allowing digital inputs to be compared to digital outputs. The monitor mix will be automatically disabled by the Codec during D-A-D loopback. The analog outputs can be individually attenuated, and the analog inputs are internally disconnected. Note that muting the line 0 output mutes the looped-back signal in this mode.

Digital loopback mode D-D is enabled by resetting the ADL bit (Control Word Bit 32) to a “0” when ENL is a “1.” In this mode, the control and data bit pattern presented on the SDRX pin is echoed on the SDTX pin with a two frame delay, allowing the host controller to verify the integrity of the serial interface starting on the third frame after D-D loopback is enabled.

During digital loopback mode, the output DACs are operational.

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The loopback modes are shown graphically in Figure 3.

GAIN

MONITOR DISABLE

Σ

AD1849K

LINE, MIC INPUT DISCONNECTED

FUNCTIONAL

SDTX

SDRX 0

1 LINE 0

LINE 1 OUTPUT

A/D µ/A-LAW

ENCODE

µ/A-LAW DECODE D/A

MUTE

AD1849K Analog Loopback D-A-D

GAIN

MONITOR

Σ

AD1849K

LINE, MIC INPUT

SDTX

SDRX LINE 0,

LINE 1 OUTPUT FUNCTIONAL

A/D µ/A-LAW

ENCODE

µ/A-LAW DECODE D/A

MUTE

AD1849K Digital Loopback D-D Figure 3. AD1849K Loopback Modes

Clocks and Sample Rates

The AD1849K can operate from external crystals, from a 256 × FS input clock, from an input clock with a programmable divide factor, or from the serial port’s bit clock (at 256 × F_S), selected under software control. Two crystal inputs are provided to generate a wide range of sample rates. The oscillators for these crystals are on the AD1849K, as is a multiplexer for selecting between them. They can be overdriven with external clocks by the user, if so desired. The recommended crystal frequencies are 16.9344 MHz and 24.576 MHz. From them the following sample rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz.

Regardless of clock input source, a clock output of 256 × FS is generated (with some skew). If an external input clock or the serial port’s bit clocks are selected to drive the AD1849K’s internal operation, they should be low jitter clocks. If no external clock will be used, Analog Devices recommends tying the clock input pin (CLKIN) to ground. If either external crystal is not used, Analog Devices recommends tying its input (CIN1 and/or CIN2) to ground.

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CONTROL REGISTERS

The AD1849K SoundPort Stereo Codec accepts control information through its serial port when in Control Mode. Some control information is also embedded in the data stream when in Data Mode. (See Figure 8.) Control bits can also be read back for system verification. Operation of the AD1849K is determined by the state of these control bits. The 64-bit serial Control Mode and Data Mode control registers have been arbitrarily broken down into bytes for ease of description. All control bits initialize to default states after RESET or Power Down. Those control bits that cannot be changed in Control Mode are initialized to defaults on the transition from Data Mode to Control Mode. See below for a definition of these defaults.

Control Mode Control Registers Control Byte 1, Status Register

Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0

0 0 1 MB OLB DCB 0 AC

63 62 61 60 59 58 57 56

MB Mic bypass:

0 Mic inputs applied to +20 dB fixed gain block.

1 Mic inputs bypass +20 dB fixed gain block.

OLB Output level bit:

0 Full-scale line 0 output is 2.8 V p-p (1 V rms).

Full-scale line 1 output is 4.0 V p-p.

Full-scale mono speaker output is 8.0 V p-p.

1 Full-scale line 0 output is 2.0 V p-p.

Full-scale line 1 output is 2.0 V p-p.

Full-scale mono speaker output is 4.0 V p-p.

DCB Data/control bit. Used for handshaking in data/control transitions. See “DCB Handshake Protocol.”

AC Autocalibration.

Autocalibration will always occur on the Control-to-Data mode transition. The AC bit is ignored. Autocalibration requires an interval of 194 frames. Offsets for all channels of ADC and DAC are zeroed. The user should specify that analog outputs are muted to prevent undesired outputs, i.e., OM0 = “0,” OM1 = “0,” and SM =“0.” Monitor mix will be automatically disabled by the Codec.

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Control Byte 2, Data Format Register

0 0 DFR2 DFR1 DFR0 ST DF1 DF0

55 54 53 52 51 50 49 48

DFR2:0 Data conversion frequency (F_S) select tin kHz):

DFR Divide Factor XTAL1 (24.576 MHz) XTAL2 (16.9344 MHz)

0 3072 8 5.5125

1 1536 16 11.025

2 896 27.42857 18.9

3 768 32 22.05

4 448 N/A 37.8

5 384 N/A 44.1

6 512 48 33.075

7 2560 9.6 6.615

Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin (COUT1 or COUT2) should be left unconnected. The external clock source need not be at the recommended crystal frequencies, and it will be divided down by the selected Divide Factor.

ST Global stereo mode. Both converters are placed in the same mode.

0 Mono mode. The left analog input appears at both ADC outputs. The left digital input appears at both DAC outputs.

1 Stereo mode

DF1:0 Codec data format selection:

0 16-bit twos-complement PCM linear 1 8-bit µ-law companded

2 8-bit A-law companded 3 8-bit unsigned PCM linear Control Byte 3, Serial Port Control Register

ITS MCK2 MCK1 MCK0 FSEL1 FSEL0 MS TXDIS

47 46 45 44 43 42 41 40

ITS Immediate three-state:

0 FSYNC, SDTX and SCLK three-state within 3 SCLK cycles after D/C goes LO 1 FSYNC, SDTX and SCLK three-state immediately after D/C goes LO

MCK2:0 Clock source select for Codec internal operation:

0 Serial bit clock (SCLK) is the master clock at 256 × FS

1 24.576 MHz crystal (XTAL1) is the clock source 2 16.9344 MHz crystal (XTAL2) is the clock source 3 External clock (CLKIN) is the clock source at 256 × F_S

4 External clock (CLKIN) is the clock source, divided by the factor selected by DFR2:0 (External clock must be stable and valid within 2000 periods after it is selected.) FSEL1:0 Frame size select:

0 64 bits per frame 1 128 bits per frame 2 256 bits per frame 3 Reserved

Note that FSEL is overridden in Data Mode when SCLK is the clock source (MCK = “0”). When SCLK is providing the 256 × FS clock for internal Codec operation, 256 bits per frame is effectively selected, regardless of FSEL’s contents.

MS Master/slave mode for the serial interface:

0 Receive serial clock (SCLK) and TSIN from an external device (“slave mode”)

1 Transmit serial clock (SCLK) and frame sync (FSYNC) to external devices (“master mode”)

Note that MS is overridden when SCLK is the clock source (MCK = “0”). When SCLK is providing the clock for internal Codec operation, slave mode is effectively selected, regardless of the contents of MS.

TXDIS Transmitter disable:

0 Enable serial output

1 Three-state serial data output (high impedance)

Note that Control Mode overrides TXDIS. In Control Mode, the serial output is always enabled.

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Control Byte 4, Test Register

0 0 0 0 0 0 ENL ADL

39 38 37 36 35 34 33 32

ENL Enable loopback testing:

0 Disabled

1 Enabled

ADL Loopback mode:

0 Digital loopback from Data/Control receive to Data/Control transmit (D-D) 1 Analog loopback from DACs to ADCs (D-A-D)

Control Byte 5, Parallel Port Register

PIO1 PIO0 0 0 0 0 0 0

31 30 29 28 27 26 25 24

PIO1:0 Parallel I/O bits for system signaling. PIO bits do not affect Codec operation.

Control Byte 6, Reserved Register

0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

Reserved bits should be written as 0.

Control Byte 7, Revision Register

0 0 1 0 REVID3 REVID2 REVID1 REVID0

15 14 13 12 11 10 9 8

REVID3:0 Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K.

Control Byte 8, Reserved Register

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

Reserved bits should be written as 0.

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Data Mode Data and Control Registers

Data Byte 1, Left Audio Data—Most Significant 8 Bits

L15 L14 L13 L12 L11 L10 L9 L8

63 62 61 60 59 58 57 56

In 16-bit linear PCM mode, this byte contains the upper eight bits of the left audio data sample. In the 8-bit companded and linear modes, this byte contains the left audio data sample. In mono mode, only the left audio data is used. MSB first format is used in all modes, and twos-complement coding is used in 16-bit linear PCM mode.

Data Byte 2, Left Audio Data—Least Significant 8 Bits

L7 L6 L5 L4 L3 L2 L1 L0

55 54 53 52 51` 50 49 48

In 16-bit linear PCM mode, this byte contains the lower eight bits of the left audio data sample. In the 8-bit companded and linear modes, this byte is ignored on input, zeroed on output. In mono mode, only the left audio data is used. MSB first format is used in all modes, and twos-complement coding is used in 16-bit linear PCM mode.

Data Byte 3, Right Audio Data—Most Significant 8 Bits

R15 R14 R13 R12 R11 R10 R9 R8

47 46 45 44 43 42 41 40

In 16-bit linear PCM mode, this byte contains the upper eight bits of the right audio data sample. In the 8-bit companded and linear modes, this byte contains the right audio data sample. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes, and twos complement coding is used in 16-bit linear PCM mode.

Data Byte 4, Right Audio Data—Least Significant 8 Bits

R7 R6 R5 R4 R3 R2 R1 R0

39 38 37 36 35 34 33 32

In 16-bit linear PCM mode, this byte contains the lower eight bits of the right audio data sample. In the 8-bit companded and linear modes, this byte is not used. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes, and twos-complement coding is used in 16-bit linear PCM mode.

Data Byte 5, Output Setting Register 1

OM1 OM0 LO5 LO4 LO3 LO2 LO1 LO0

31 30 29 28 27 26 25 24

OM1 Output Line 1 Analog Mute:

0 Mute Line 1

1 Line 1 on

OM0 Output Line 0 Analog Mute:

0 Mute Line 0

1 Line 0 on

LO5:0 Output attenuation setting for the left DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62” represents 93 dB of attenuation. Attenuation = 1.5 dB × LO, except for LO = “63,” which represents full digital mute.

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Data Byte 6, Output Setting Register 2

ADI SM RO5 RO4 RO3 RO2 RO1 RO0

23 22 21 20 19 18 17 16

ADI ADC Invalid. This bit is set to “1” during the autocalibration sequence, indicating that the serial data output from the ADCs is meaningless.

SM Mono Speaker Analog Mute:

0 Mute mono speaker 1 Mono speaker on

RO5:0 Output attenuation setting for the right DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62”

represents 93 dB of attenuation. Attenuation = 1.5 dB × RO, except for RO = “63,” which represents full digital mute.

Data Byte 7, Input Setting Register 1

PIO1 PIO0 OVR IS LG3 LG2 LG1 LG0

15 14 13 12 11 10 9 8

PIO1:0 Parallel I/O bits for system signaling. PIO bits do not affect Codec operation.

OVR ADC input overrange. This bit is set to “1” if either ADC channel is driven beyond the specified input range. It is

“sticky,” i.e., it remains set until explicitly cleared by writing a “0” to OVR. A “1” written to OVR is ignored, allowing OVR to remain “0” until an overrange condition occurs.

IS Input selection:

0 Line-level stereo inputs

1 Microphone (condenser-type) level inputs if MB = 0 (+20 dB gain), or line-level stereo inputs if MB = 1 (0 dB gain).

LG3:0 Input gain for left channel. “0” represents no gain. Step size is 1.5 dB; “15” represents +22.5 dB of input gain.

Gain = 1.5 dB × LG.

Data Byte 8, Input Setting Register 2

MA3 MA2 MA1 MA0 RG3 RG2 RG1 RG0

7 6 5 4 3 2 1 0

MA3:0 Monitor mix. “0” represents no attenuation, i.e., the ADCs’ output is fully mixed with the DACs’ input. Step size is 6 dB; “14” represents an attenuation of both channels of the ADCs’ output along the monitor datapath of 84 dB. Mix attenuation = 6 dB × MA, except for MA = “15,” which disables monitor mix entirely.

RG3:0 Input gain for right channel. “0” represents no gain. Step size is 1.5 dB; “15” represents +22.5 dB of input gain.

Gain = 1.5 dB × RG.

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Control Register Defaults

Upon coming out of RESET or Power Down, internal control registers will be initialized to the following values:

Defaults Calming Out of RESET or Power Down

MB 0 Mic Input Applied to +20 dB Fixed Gain Block

OLB 0 Full-Scale Line 0 Output 2.8 V p-p, Full-Scale Line 1 Output 4.0 V p-p, Full-Scale Mono Speaker Output 8.0 V p-p

DCB 1 Data/Control Bit HI

AC 0 Autocalibration Disabled

DFR2:0 0 8 or 5.5125 kHz

ST 0 Monophonic Mode

DF1:0 1 8-Bit µ-Law Data

ITS 0 FSYNC, SDTX and SCLK Three-State within 3 SCLK Cycles after D/C Goes LO MCK2:0 0 Serial Bit Clock [SCLK] is the Master Clock

FSEL1:0 2 256 Bits per Frame

MS 0 Slave Mode

TXDIS 1 Three-State Serial Data Output

ENL 0 Loopback Disabled

ADL 0 Digital Loopback

PIO1:0 3 “1”s, i.e., Three-State for the Open Collector Outputs

OM1:0 0 Mute Line 0 and Line 1 Outputs

LO5:0 63 Mute Left DAC

ADI 1 ADC Data Invalid, Autocalibration in Progress

SM 0 Mute Mono Speaker

RO5:0 63 Mute Right DAC

OVR 0 No Overrange

IS 0 Line-Level Stereo Inputs

LG3:0 0 No Gain on Left Channel

MA3:0 15 No Mix

RG3:0 0 No Gain on Right Channel

Also, when making a transition from Control Mode to Data Mode, those control register values that are not changeable in Control Mode get reset to the defaults above (except PIO). The control registers that can be changed in Control Mode will have the values they were just assigned. The subset of the above list of control registers that are assigned default values on the transition from Control Mode to Data Mode are:

Defaults at a Control-to-Data Mode Transition OM1:0 0 Mute Line 0 and Line 1 LO5:0 63 Mute Left DAC

SM 0 Mute Mono Speaker

RO5:0 63 Mute Right DAC

OVR 0 No Overrange

IS 0 Line-Level Stereo Inputs

LG3:0 0 No Gain

MA3:0 15 No Mix

RG3:0 0 No Gain

Note that all these defaults can be changed with control information in the first Data Word. Note also that the PIO bits in the output serial streams always reflect the values most recently read from the external PIO pins. (See “Parallel I/O Bits” below for timing details.) A Control-to-Data Mode transition is no exception.

An important consequence of these defaults is that the AD1849K Codec always comes out of reset or power down in slave mode with an externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word input signal (TSIN) initially. (See “Codec Startup, Modes, and Transitions” below for more details.)

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SERIAL INTERFACE

A single serial interface on the AD1849K provides for the transfer of both data and control information. This interface is simi- lar to AT&T’s Concentrated Highway Interface (CHI), allowing simple connection with ISDN and other telecommunication devices. The AD1849K’s implementation also allows a no-glue direct connection to members of Analog Devices’ family of fixed-point DSP processors, including the ADSP-2101, the ADSP-2105, the ADSP-2111, and the ADSP-2115.

Frames and Words

The AD1849K serial interface supports time-division multi- plexing. Up to four AD1849K Codecs or compatible devices can be daisy-chained on the same serial lines. A “frame” can consist of one, two, or four 64-bit “words.” Thus, frames can be 64, 128, or 256 bits in length as specified by the FSEL bits in Control Byte 3. Only 64 bits of each frame, a “word,” contain meaningful data and/or control information for a particular Codec. See Figure 4 below.

ONE WORD/FRAME WORD #1 0 63

TWO WORDS/FRAME WORD #1 WORD #2 0 63 64 127

FOUR WORDS/FRAME WORD #1 WORD #2 WORD #3 WORD #4 0 63 64 127 128 191 192 255

Figure 4. Frames and Words

The AD1849K supports two types of words: Data Words and Control Words. The proper interpretation of a word is determined by the state of the asynchronous Data/Control (D/C) pin.

The D/C pin establishes whether the SoundPort Codec is in the

“Data” mode or “Control” mode. Transitions between these modes require an adherence to a handshaking protocol to prevent ambiguous bus ownership. The Data/ Control transition protocol is described below in a separate section.

Clocks and the Serial Interface

The primary pins of the AD1849K’s serial interface are the serial data receive (SDRX) input pin. The serial data transmit (SRTX) pin, the serial data bit clock (SCLK) pin, the frame sync output (FSYNC) pin, the chaining word input (TSIN) pin, and the chaining word output (TSOUT) pin. The AD1849K can operate in either master mode—in which case SCLK and FSYNC are outputs and TSIN is an input—or in slave mode—

in which case SCLK and TSIN are inputs and FSYNC is three- stated. If the AD1849K is in master mode, the internally selected clock source is used to drive SCLK and FSYNC. Note that in Control Mode, the Codec always behaves as a slave, regardless of the current state of the MS (Master/Slave) bit.

The five possible combinations of clock source and master/slave are summarized in Figure 5.

INTERNAL OSCILLATORS CLKIN SCLK

Recommended modes are indicated above by “yes.” Note that Codec performance is improved with a clean clock source, and in many systems the lowest jitter clocks available will be those generated by the Codec’s internal oscillators. Conversely, SCLK in many systems will be the noisiest source. The master/SCLK clock source combination is impossible because selecting SCLK as the clock source overrides the MS control bit, forcing slave mode. (The SCLK pin cannot be driving out if it is simulta- neously receiving an external clock.)

The internal oscillators or CLKIN can be the clock source when the serial interface is in slave mode provided that all clocks applied to the AD1849K SoundPort Codec are derived from the same external source. Precise phase alignment of the clocks is not necessary, rather the requirement is that there is no frequency drift between the clocks.

In master mode, the SCLK output frequency is determined by the number of bits per frame selected (FSEL) and the sampling frequency, FS. In short, SCLK = FSEL × FS in master mode.

Timing Relationships

Input data (except PIO) is clocked by the falling edge of SCLK.

Data outputs (except PIO) begin driving on the rising edge of SCLK and are always valid well before the falling edge of SCLK.

Word chaining input, TSIN, indicates to a particular Codec the beginning of its word within a frame in both slave and master modes. The master mode Codec will generate a FSYNC output which indicates the beginning of a frame. In single Codec systems, the master’s FSYNC output should be tied to the master’s TSIN input to indicate that the beginning of the frame is also the beginning of its word. In multiple Codec daisy-chain systems, the master’s FSYNC output should be tied to the TSIN input of the Coded (either the master or one of the slaves) which is intended to receive the first word in the frame.

FSYNC and TSIN are completely independent, and nothing about the wiring of FSYNC to TSIN is determined by master or slave status (i.e., the master can own any one of the words in the frame). The master Codec’s FSYNC can also be tied to all of the slave Codecs’ FSYNC pins. When a slave, a Codec’s FSYNC output is three-stated. Thus, it can be connected to a master’s FSYNC without consequence. See “Daisy-Chaining Multiple Codecs” below for more details.

The FSYNC rate is always equal to the data conversion sampling frequency, F_S. In Data Mode, the key significance of

“frames” are to synchronize the transfer of digital data between an AD1849K’s internal ADCs and DACs and its serial interface circuitry. If, for example, a Codec has been programmed for two words per frame (FSEL = “1”), then it will trigger the data converters and transfer data between the converters and the interface every 128 SCLKs. The TSIN input signals the Codec where its word begins within the frame. In Control Mode, frame size is irrelevant to the operation of any particular Codec; TSIN

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TSIN is sampled on the falling edge of SCLK. A LO-to-HI transition of TSIN defines the beginning of the word to occur at the next rising edge of SCLK (for driving output data). The LO-to-HI transition is defined by consecutive LO and HI samples of TSIN at the falling edges of SCLK. Both input and output data will be valid at the immediately subsequent falling edge of SCLK. See Figures 6 and 7.

SCLK

FSYNC, TSIN, &

TSOUT

SDRX & SDTX

FIRST DATA BIT OF WORD

Figure 6. AD1849K Timing Relationships After the beginning of a word has been recognized, TSIN is a

“don’t care”; its state will be ignored until one SCLK period before the end of the current word.

SCLK

SDRX AND TSIN INPUTS

SDTX, FSYNC, AND TSOUT OUTPUTS

t_D t_OH

PIO INPUTS

PIO OUTPUTS

t_ZV

t_VZ SDTX CONTROL

OR DATA BYTE 1, BIT 7 OUTPUT

SDTX CONTROL OR DATA BYTE 8, BIT 0 OUTPUT

t_IH t_S t_IH t_S

t_HI t_LO t_CLK

Figure 7. AD1849K Timing Parameters The AD1849K comes out of reset with the default conditions specified in “Control Register Defaults.” It will be in the mode specified by the D/C pin. If in Control Mode, the SoundPort Codec can be configured by the host for operation. Subsequent transitions to Control Mode after initialization are expected to be relatively infrequent. Control information that is likely to change frequently, e.g., gain levels, is transmitted along with the data in Data Mode. See Figure 8 for a complete map of the data and control information into the 64-bit Data Word and the 64-bit Control Word.

16-BIT STEREO DATA WORD

16-BIT MONO DATA WORD

8-BIT STEREO DATA WORD

8-BIT MONO DATA WORD

CONTROL WORD

Left-Channel Audio Right-Channel Audio OM LO ADI SM RO PIO OVR IS LG MA RG

63 48 47 32 31 30 29 24 23 22 21 16 15 14 13 12 11 8 7 4 3 0

Left-Channel Audio Left-Channel Audio OM LO ADI SM RO PIO OVR IS LG MA 0000

63 48 47 32 31 30 29 24 23 22 21 16 15 14 13 12 11 8 7 4 3 0

OM LO ADI SM RO PIO OVR IS LG MA 63 5655 48 47 4039 32 31 30 29 24 23 22 21 16 15 14 13 12 11 8 7 4 3 0

Left Audio 0000 0000 Right Audio 0000 0000 RG

OM LO ADI SM RO PIO OVR IS LG MA

63 5655 32 31 30 29 24 23 22 21 16 15 14 13 12 11 8 7 4 3 0

Left Audio 0000 0000 Left Audio 0000 0000 0000

001 MB OLB DCB 0 AC 00 DFR ST DF ITS MCK FSEL MS TXDIS 0000 00 ENL ADL PIO 00 0000 0000 0000 0010 REVID 0000 0000 63 61 60 59 58 57 56 55 54 53 51 50 49 48 47 46 44 43 42 41 40 39 34 33 32 31 30 29 24 23 16 15 12 11 8 7 0

Figure 8. AD1849K Bit Positions for Data and Control