An Educational Model of the Time Space Switch
Realized in the FGPA Circuit
Marcin Dziuba, Marek Michalski
Poznan University of Technology, Chair of Communication and Computer Networks, ul. Polanka 3, 60-965 Pozna´n, Poland, e-mail: (marcin.dziuba, marek.michalski)@et.put.poznan.pl
Abstract—In this paper we will present an educational model of time space switch for E0 streams. It is realized in a hardware FPGA chip. Its functionality is programmed in Verilog and can be controlled by TTL signals or dedicated software on PC connected with USB.
I. INTRODUCTION
Nowadays communications technology offers many solu-tions for many different problems. Actual state of art is full of sophisticated and very interested mechanisms. All of them together create world what we are living in. It is very nice to live in a neighborhood of friendly technology and use it. Much nicer is to understand it and more over - create it! But before someone can became an engineer, he has to complete many courses or studies. Things described in this paper are to help students to realize their aims. This paper presents an educational model of time space switch for circuit switching [1]. Of course, actually we have more complex communication technologies, like for example packet switching systems [2] or very sophisticated mechanisms like openflow [3], but students have to start collecting their knowledge and experience from simpler mechanisms. To model time space switch we will use very modern technology, which is FPGA (Field Programmable
Gates Array). It allows us to realize not only the main subject,
but also whole working system. In this paper we will shortly describe this technology and used elements, we will present designed system and its usage during educational process, finally we will end with some conclusions and description of further works.
II. THEORETICALBACKGROUND
This paper is about time space switch. The theory of switching is widely discussed in the literature [1], [2], [4], [5], here we will present only the most important facts about space, time, and time space switching.
Space switching consists on a moving a signal from one physical input to one of physical outputs. In the Fig. 1 we can see the space switch with two inputs and two outputs. According to the internal state of the switch, signal from input zero (or one) is switched to the output zero or one. When we need more inputs and outputs, basic switching elements
0 0
1 1
Fig. 1. Basic2 × 2 space switching element
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
Fig. 2. The space switching fabric withN = 8 inputs and outputs
are connected into bigger structures, they are called switching fabrics. Switching fabrics can have different structures and configurations [2], [4], [5], [6], an example of banyan type switching fabric [6] with N = 8 inputs and outputs is presented in the Fig. 2.
In case of time switching situation is a little bit more complicated. This way of switching is an extension of a time domain access [7]. In such a situation different users of the same link have an access to it only in certain periods of time. Each such a period is called a time-slot. Time-slots for different users are grouped into one cycle, cycles with the same structure are repeated continuously. The time switching consists on a changing a position of particular time-slot in the cycle. In the Fig. 3 there is presented a time switch, which changes the order of time-slots in the cycle. It can be seen, that the structure of cycle on the input is different than structure of cycle on the output.
The time space switch combines a possibility of switching in two domains: space and time. It can reorder time-slots in the cycle, it can also place particular time-slot from particular input in different output. The idea of time space switching is shown in the Fig. 4, there are presented two cycles for each input and two for each output.
III. HARDWAREDESCRIPTION
A. Field Programmable Gates Arrays
For realization a hardware implementation of presented model FPGA chips were used [8], [9], [10], [11], [12]. The
4 3 2 1 4 3 2 1 3 2 1 4 3 2 1 4
Fig. 3. The time switch with cycle containing four time-slots
4 3 2 1 4 3 2 1 1 1 1 1 1 1 1 1 4 3 2 1 4 3 2 1 3 3 2 2 3 3 2 2 4 3 2 1 4 3 2 1 4 3 4 2 4 3 4 2 4 3 2 1 4 3 2 1 3 2 4 4 3 2 4 4
Fig. 4. The time space switch with 4 inputs and 4 outputs
functionality of these chips is programmable. They are very modern integrated digital circuits with a very high scale of integration, they contain a large number of logic gates. Actually such chips can contain more than 1 000 000 gates [13]. These gates are grouped into blocks, their functionality can be configured, hence they are called Configurable Logic
Block (CLB). The main element of each CLB, it is its Look-Up Table (LUT). This table is physically realized as a RAM. The
configuration of particular CLB consists on a storing proper data in its LUT. CLB’s are connected with other ones with buses and create array of blocks.
The content of particular LUT is programmed by writing a proper file into FPGA chip’s memory. The functionality of designed project has to be coded in some HDL - Hardware
Description Language (e.g. Verilog or VHDL). After proper
synthesis, the data can be sent to the chip and it starts its functioning.
B. General Description of Used Modules
We use FGPA chips from Xilinx Company [14]. We don’t prepare our own board, we use modules prepared by Propox [15]. It is polish company created by former students of Gdansk University of Technology. In their portfolio there are many interesting elements. We use four of them - motherboard (Fig. 5) with many slots, two kinds of mini-modules with Spartan 3 chip (Fig. 6) and module USB connectivity to PC.
IV. MOTIVATION
The main goal of model presented in this paper is to help to teach students how such a switch works. They have to configure it to realize some re-switching, generate incoming signals, send them to the output through the switch and observe signals in proper time-slot in certain output with oscilloscope and LEDs.
The presented switch has4 inputs and 4 outputs, each of them is treated as a PCM30/32 stream, so, it contains 32 time-slots. Typical usage is realized in steps described below. First, students configure the switch to move data from time-slot ti
in inputIxto time-slottjin outputOy. Each re-switching can
be defined with four numbers grouped into two pairs: Ix.ti−
Oy.tj. Next, students generate traffic inIx.ti, finally they try
to observe the same traffic onOy.tj. If everything is properly
configured, the incoming signals can be observed with LEDs
Fig. 5. Matherboard
and/or on the screen of oscilloscope. With this model students practically learn how time space switches work.
V. BASICFUNCTIONALITY
The whole model of switching system contains modules for traffic generation, traffic analysis and the main switch. All of them are implemented in the same FPGA hardware circuit, they are connected internally, but their inputs and outputs are also connected to the pins of FPGA chip and can be used for monitoring signals and controlling.
The basic frequency of main clock isf0= 50 MHz, but the switch seams to be working with 2 048 000 cycles per second. All modules of this system (main switch, traffic generator and analyzer) work with the same speed.
The main switch is configured by writing its memory. To configure re-switchingIx.ti− Oy.tj student has to set up 14 binary values (2× (2 bits for input or output number and 5 bits for time-slot number)) on dedicated DIP-switch and press button with name "SAV E". After this, in memory with addressIx.ti there is valueOy.tj. The main switch can serve
4 × 32 = 128 re-switchings in the same time.
By default, the module of traffic generation sends "zeros" in all time-slots to each input. One time-slot in one input is "connected" with dedicated button, this button will be named "GENERAT E". This time-slot and input is defined by Ix.ti
- proper values are set up via DIP-switch. If this button is pressed, generator sends out in time-slot ti to the input Ix
value 101010102. This signal can be also observed on the oscilloscope connected to the proper pin of FPGA chip.
The traffic analyzer works similarly to the traffic generator. This module receives traffic from four outputs of the switch. The main output of this analyzer is one LED, it represents signals from time-slot tj from output Oy. Values Oy.tj are
defined by 7 bits set up in DIP-switches.
Lets assume, that switch realize re-switchingIx.ti− Oy.tj, traffic generator sends out nonzero values in Ix.ti, traffic
analyzer is "tuned" for Oy.tj, so LED represents signals in
time-slot tj from outputOy. If the LED blinks according to
pushing the button "GENERATE", it is a proof, that switch realize re-switching Ix.ti− Oy.tj.
VI. EXTENDEDFUNCTIONALITY
The manual setting of particular re-switching is only the first step of usage of this model. The second one consists on a generation of random re-switchings and students are to find and point all of them. There is prepared function, which is hidden under button with name "RANDOM". It resets all the re-switchings, after this the output of each of them is changed with randomly chosen. With such a modification we will obtain a pseudo-random permutation. The task for students is to investigate what is the configuration of internal memory in the actual state. They can generate all possible signals and tune the analyzer to any parameters. The state of internal memory of the switch can be also analyzed and modified by USB connection with the usage of dedicated software. This functionality is still under development and (probably) it will be accessible only for a teacher.
VII. CONCLUSION ANDFURTHERWORKS
In this paper we have presented an educational model of time space switch. It can be used during laboratories with students or pupils in technical schools. The system is implemented in Spartan3, which is the main chip of module (Fig. 6), which is mounted in the universal board (Fig. 5) from Propox. We are going to prepare our own board, which will be dedicated for our solution, it will have dedicated equipment like power supply, switches and buttons, and slot for module with FPGA chip. We are going also to extend its functionality with self-checking modules to automatize assessment. We are going to prepare models of another types of switches, especially space switching fabrics with different structures. We hope, that they will be useful in education process in our faculty.
REFERENCES
[1] Jajszczyk A.:, „Wst˛ep do telekomutacji”, Wydawnictwo Naukowo-Techniczne, Warszawa 2004.
[2] Chao H. J., Liu B.: High Performance Switches and Routers, Wiley-IEEE Press, Maj 2007.
[3] http://www.openflow.org, web access: 20.10.2011.
[4] Beneš V. E.: Mathematical Theory of Connecting Networks and Telephone Traffic. Academic Press, Nowy Jork, 1965.
[5] Clos C.: „A study of non-blocking switching networks”. The Bell System Technical Jurnal, str. 406–424, 1953.
[6] Goke L. R., Lipowski G. J.: „Banyan Networks for Partitioning Multi-processor Systems”, 1st Annual Symposium on Computer Architecture, str. 21-28, 1973.
[7] Jajszczyk A., Tyszer J,: „Broadband time-division circuit switching”, IEEE Journal on Selected Area on Communications, vol 14, No. 2, pp 337–345, 1996.
[8] Chu P. P.: „FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version”. John Wiley & Sons, Inc., 2008.
[9] Kalisz J.: „J˛ezyk VHDL w praktyce”, Wydawnictwa Komunikacji i Ł ˛aczno´sci, 2002.
[10] Majewski J., Zbysi´nski P.: „Układy FPGA w przykładach”, BTC 2007. [11] Wilson P.: „Design Recipes for FPGAs”, Newnes, 2007.
[12] Zwoli´nski M.: „Projektowanie układów cyfrowych z wykorzystaniem j˛ezyka VHDL”, Wydawnictwa Komunikacji i Ł ˛aczno´sci, 2009. [13] „Xilinx Virtex-7 FPGA Family” http://www.xilinx.com/products/virtex7/
index.htm, web access: 20.10.2011.
[14] http://www.xilinx.com, web access: 20.10.2011. [15] http://www.propox.com, web access: 20.10.2011.
