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BUZ21-CHIP

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f Z 7 SCS-THOMSON

BUZ21 CHIP

N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN DIE FORM

DIE SIZE: 156 x 156 mils

METALLIZATION:

Top Al

Back A u /C r/N i/A u

BACKSIDE THICKNESS: 6100 A

DIE THICKNESS: 16 ± 2 mils

PASSIVATION: P-Vapox

BONDING PAD SIZE:

Source 4 0 x 3 4 mils

Gate 1 5 x 19 mils

• RECOMMENDED WIRE BONDING:

Source Al - max 15 mils

Gate Al - max 7 mils

V DSS R DS (on) *d*

100 V 0.1 0 19 A

N-channel enhancement mode POWER MOS field effect transistor. Easy drive and very fast switching times make this POWER MOS ideal for high speed switching applications.

Die geometry

SOURCE

■ GATE

Drain on backside

MC-0074

* With R,hj^ max. 1.67°C/W

June 1988 1/2

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BUZ21 CHIP

GUARANTEED PROBED ELECTRICAL CHARACTERISTICS (Tj = 25°C, Note 1)

Parameters Test Conditions Min. Typ. Max. Unit

V ( B R ) d s s Drain-source breakdown voltage

lD= 250 pA VGS= 0 100 V

I d s s Zero 9a4e volta9e

drain current

VDS= Max Rating

VDS = Max Rating x 0.8 T,= 125°C

250 1000

fiA

fA

lGSs Gate-body leakage current

VGS= ± 20 V 100 nA

Vq s (th ) Gate threshold

voltage

^ D S = ^ G S Id= 1 m A 2.1 4 V

Rds (on) Static drain-source on resistance

VGS= 1 0 V Iq= 1 A 0.1 0

NOTES: 1 - Due to probe testing limitations dc parameters only are tested. They are measured using pulse techni­

ques: pulse width <300 /is, duty cycle <2%

2 - For detailed device characteristics please refer to the discrete device datasheet

5 i

SGS-THOMSON■ „

2/2

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