Simultaneous loading and scheduling with no revisiting of stations in a flexible assembly system

Z E SZ Y T Y N A U K O W E P O L IT E C H N IK I ŚL Ą S K IE J Seria: A U T O M A T Y K A z. 134

2002 N r kol. 1554

T adeusz SAW IK

A kadem ia G órniczo -H u tn icza

SIMULTANEOUS LOADING AND SCHEDULING WITH NO REVISITING OF STATIONS IN A FLEXIBLE ASSEMBLY SYSTEM1

S u m m a r y . T h e p a p e r presents m ixed integer pro g ram m in g approach to sim ul­

ta n eo u s lo a d in g a n d scheduling of a flexible assem bly system (FAS). T h e FAS is m ade up o f a netw ork of assem bly stages in terconnected by tra n s p o rta tio n links, w here each sta g e consists o f one or m ore identical parallel sta tio n s. Each sta tio n has its own in te rn a l in p u t an d o u tp u t buffer of a finite capacity and a lim ited work space for p a r t feeders. T h e p roblem objective is to determ in e an allocation of assem bly ta sk s an d p a r t feeders am ong th e sta tio n s and to find an assem bly schedule for a m ix of p ro d u c ts w ith no revisting of sta tio n s so as to com plete the p ro d u c ts in m in im u m tim e. N um erical exam ple and som e co m p u tatio n al results are p rese n ted to illu s tra te ap p lica tio n s of th e proposed approach.

ROZDZIAŁ ZASOBÓW I HARMONOGRAMOWANIE BEZ POW ROTÓW WYROBÓW DO MASZYN

W ELASTYCZNYM SYSTEMIE MONTAŻOWYM

S t r e s z c z e n i e . W p rac y przedstaw iono m odel program ow ania całkowitoliczbowego m ieszanego do jednoczesnego o b ciążenia m aszyn i szeregow ania zad ań w elasty­

cznym sy stem ie m ontażow ym . S ystem sk ła d a się z sieci sta cji m ontażow ych. K ażda sta c ja o bejm uje je d n ą lub kilka jednakow ych m aszyn pracujących równolegle, z w łasnym i b u fo ra m i wejściowym i i w yjściow ym i o skończonych pojem nościach oraz o g raniczoną p rze strzen ią ro b o czą n a p o d a jn ik i części. M ontow any w yrób prze­

chodzi przez różne sta cje, odw iedzając każdą co najw yżej raz. Należy wyznaczyć rozdział z a d a ń m ontażow ych i p o d ajn ik ó w części pom iędzy sta cje oraz harm ono­

gram m o n ta ż u bez pow rotów wyrobów do raz odw iedzanych sta cji, ta k aby zm ini­

m alizować czas w ykonyw ania zadanego zbioru różnych w yrobów . W yniki ekspery­

m entów obliczeniow ych ilu s tru ją zastosow anie proponow anego podejścia.

‘This work was partially supported by AGH and KBN

1. Introduction

A flexible assem bly system (FAS) is a netw ork o f assem bly stages interconnected by tra n s p o r ta tio n links, w here each stage consists of one or m ore id en tical parallel sta tio n s. E ach s ta tio n h a s a finite w ork space for p a r t feeders a n d finite capacity in p u t a n d o u tp u t buffers for te m p o ra ry sto rag e of p ro d u c ts w aiting for processing or for tra n s fe r betw een th e sta tio n s. In th e system different types of assem bly tasks can be perfo rm ed to assem ble various ty p es o f p ro d u cts. Each p ro d u c t v isits a subset o f assem bly sta tio n s, w here th e req u ired p a r t feeders have been assigned, however rev isitin g o f s ta tio n s is n o t allowed.

T h e tw o m a jo r s h o rt-te rm p la n n in g issues in flexible assem bly sy stem s are load­

ing a n d scheduling. G iven a m ix of p ro d u c ts to be assem bled, th e o b jective of the lo a d in g p ro b lem is to a llo ca te assem bly task s a n d p a r t feeders am ong th e assembly s ta tio n s w ith lim ite d w ork space an d by th is to select assem bly ro u te s for a mix of p ro d u c ts, so as to b alan c e th e s ta tio n w orkloads a n d to elim in a te revisiting of s ta tio n s by p ro d u c ts. In c o n tra st, th e o b jective of th e scheduling p roblem is to de­

te rm in e th e d e ta ile d sequencing an d tim in g of all assem bly ta sk s for each individual p ro d u c t, so as to m axim ize th e system pro d u ctiv ity , w hich m ay b e defined in terms o f th e assem bly schedule le n g th (m akespan) for a m ix of p ro d u cts. T h e limited in-process buffers re su lt in scheduling problem w ith m achine blocking (e.g. [1, 4]), w here a co m p leted p ro d u c t m ay rem ain on a m achine a n d block it u n til output buffer o f th e m achine becom es em pty. T h is prevents a n o th e r p ro d u c t from being processed on th e blocked m achine.

In th is p a p e r sim u ltan eo u s loading a n d scheduling o f a FAS is considered with no rev isitin g of s ta tio n s an d a m ixed integer pro g ram m in g fo rm u latio n is proposed to solve th e problem .

T h e in te g er p ro g ra m m in g approach h a s been w idely used to solve th e loading pro b lem s (e.g. [3, 5]), som e scheduling problem s (e.g. [2]), an d recently also to schedule surface m o u n t technology lines (e.g. [7]).

M ixed in teg er p ro g ra m m in g m odels for sim ultaneous o r seq u en tial loading and scheduling of various FAS configurations w ith u n lim ite d in-process buffers and re­

v isitin g of s ta tio n s were p resen ted in [6].

T h e p a p e r is organized as follows. M ixed integer pro g ram m in g m odel for simul­

ta n e o u s FAS lo ad in g a n d scheduling is p resented in th e n e x t section. A numerical ex am p le a n d som e resu lts o f co m p u ta tio n a l ex p erim en ts w ith A M P L /C P L E X solver are p rese n ted in section 3 a n d conclusions are m ad e in th e la s t section.

2. M ixed integer program for simultaneous loading and scheduling

L et us consider a FAS m ad e u p of m processing sta g es i e I = I a U Pb — { 1 , . . . ,m } , for assem bly {Ia) a n d for buffering (Jfl). T h e processing stag es are in­

te rc o n n e c te d by tr a n s p o r ta tio n p a th s t h a t link any p a ir of assem bly stages. Trans­

p o rta tio n tim e s betw een th e stages, however, are assum ed to b e negligible. Each assem bly sta g e i £ I a consists of m* > 1 identical p arallel assem bly statio n s. In ad d itio n , each assem bly sta g e h as its own in te rn a l in p u t an d o u tp u t buffer stages

S im ultaneous L oading a n d Scheduling.. 353

T able 1 N o ta tio n

I n d ic e s

h = processor in sta g e i, h £ H, = { 1 , . . . , m ;}

i = processing stage, i £ I = I a U Ib = { L • • • >

j = processing ta sk , j € J = { 1 , . . . ,n } k

=

p ro d u c t, k £ K = { 1 , . . . , v}

I n p u t p a r a m e t e r s

&ij w orking sp ace required for assignm ent of ta sk j to assem bly sta tio n in sta g e i

hi to ta l w orking space of each assem bly s ta tio n in sta g e i £ I a (num ber of ta sk s t h a t m ay be assigned to each s ta tio n in sta g e i, if all a y = 1) Pijk = processing tim e in sta g e i of ta sk j of p ro d u c t k

Hi = th e se t o f parallel processors a t sta g e i Ia = th e se t o f assem bly stages

Ib = th e se t o f buffer stages

h i i ) — {i — l , i + l} - th e se t of in p u t an d o u tp u t buffer stages of assem bly sta g e i € I a

h = th e se t of assem bly sta g es capable of perform ing ta s k j Jk = th e ordered set o f ta sk s required for p ro d u c t k

Q = a large n u m b e r n o t less th a n th e schedule length D e c is io n v a r ia b le s

Umax = schedule len g th

Cik = com pletion tim e in sta g e i of p ro d u c t k dik = d e p a rtu re tim e from stag e i of p ro d u c t k

Xij = 1, if ta sk j is assigned to processing stag e i € Ij\ otherw ise x y = 0 (ta sk assignm ent variable)

Vks

=

1, if p ro d u c t k precedes p ro d u c t s; otherw ise yks = 0 (p ro d u c t se­

quencing variable)

Zihk

==

1, if p ro d u c t k is assigned to processor h e H i in stag e i £ / ; otherw ise z ihk = 0 (p ro d u c t assignm ent variable)

i - 1 a n d i + 1 of a fixed capacity m ;_ i and m i+1 buffers, respectively. D enote by JB (i) = {i — l , i + 1} th e set o f in p u t an d o u tp u t buffer stages of assem bly stage i £ Ia-

In th e sy stem n different ty p e s of assem bly task s j £ J = { l , . . . , n } can be perform ed to sim u lta n eo u sly assem ble v p ro d u c ts k £ K — { l , . . . , u } of various types. L e t J k b e th e sequence o f assem bly ta sk s required to com plete p ro d u c t k.

E ach assem bly s ta tio n in sta g e i £ I a h as a finite w ork space 6; w here a lim ited nu m b er o f c o m p o n en t feeders an d g rip p er m agazines can b e placed. A s a resu lt only a lim ite d n u m b e r o f assem bly ta sk s can be assigned to one assem bly sta tio n . L et I j C I a b e th e su b se t of assem bly stages capable of perform ing ta sk j , an d let a y be th e a m o u n t of w orking space o f assem bly s ta tio n in stag e i £ I j , required for assig n m e n t of ta sk j . Finally, den o te by py* > 0 th e assem bly tim e required to perform in sta g e i € I j ta sk j € J* of p ro d u c t k.

T h e p roblem o bjective is to d eterm in e an allo catio n of assem bly ta sk s a n d part feeders am o n g th e s ta tio n s w ith lim ite d w orking space an d to find an assembly schedule for a m ix of p ro d u c ts so as to com plete th e p ro d u c ts in m inim um tim e w ith no b ack track in g , i.e., w ith n o revisiting o f sta g es by p ro d u cts.

A n a ssig n m e n t o f assem bly ta sk s to sta tio n s determ in es a processing ro u te for each p ro d u c t, i.e., a sequence of s ta tio n s to b e v isited in o rd er to com plete the req u ired sequence of tasks. T h e ” no backtracking” requirem ent im plies th a t for each p ro d u c t a su b se t of successive ta sk s is assigned to one assem bly sta tio n , and hence each assem bly s ta tio n can b e v isited a t m o st once by every p ro d u ct.

A unified m o d elin g ap p ro ach is a d o p ted w ith th e buffers viewed as machines w ith zero processing tim es. A s a re su lt th e scheduling p roblem w ith buffers can be converted in to o ne w ith no buffers b u t w ith blocking. T h e blocking tim e o f a machine w ith zero processing tim e denotes p ro d u c t w aitin g tim e in th e buffer represented by t h a t m achine. W e assum e t h a t each p ro d u c t assigned to sortie assem bly s ta tio n m ust also v isit th e in p u t an d o u tp u t buffers of t h a t sta tio n . However, zero blocking tim e in a buffer sta g e in d ic ates th a t th e corresponding p ro d u c t does n o t need to w ait in th e buffer. L et us n o te t h a t for each buffer stage, a p ro d u c t’s com pletion tim e is eq u al to its d e p a rtu re tim e from th e previous stage, since th e buffer processing time is zero.

W a itin g o f p r o d u c t in th e in p u t or o u tp u t buffer connected w ith an assembly sta g e w here th e assem bly ta sk j is to be perform ed is referred to as buffering ta sk j . B o th assem bly s ta tio n s an d buffers are referred to as processors, an d b o th assembly an d buffering ta sk s are referred to as processing tasks.

F or each ty p e o f p ro d u c t th e to ta l assem bly tim e in each sta g e d ep en d s on the a ssig n m e n t o f assem bly ta sk s an d th e corresponding p a r t feeders. T h e ” no back­

tra c k in g ” req u irem en t enables a su b set of successive ta sk s of each p ro d u c t assigned to an assem bly s ta tio n to b e perform ed contiguously, w ith no breaks betw een the task s. T herefore, for each p ro d u c t k a n d each assem bly sta g e i S Ia, th e total assem bly tim e is a v aria b le d eterm in e d by th e su m m atio n o f th e assem bly tim es for all ta sk s j € Jk th a t have been assigned to th is stage, i.e. Y ,j£ jk P ijk^ij, w here Xy is ta sk assig n m e n t b in a ry v ariable (see, T able 1).

F or every p r o d u c t k le t d en o te its com pletion tim e in each sta g e i, and dik its d e p a r tu re tim e from sta g e i. P rocessing w ith o u t p ree m p tio n ind icates th at p ro d u c t k co m p leted in sta g e i a t tim e c,-* s ta r ts its processing in th a t stage at tim e Cik — 12jeJk Pijk^ij- P ro d u c t k com pleted in stag e i a t tim e d e p a rts a t time dik > Cik to an available processor in th e n ex t sta g e of its processing ro u te. If at tim e Cik all processors in th e n e x t sta g e are occupied, th e n th e processor in stage i is blocked by p ro d u c t k u n til a dow nstream processor becom es available.

T h e m a th e m a tic a l fo rm u latio n o f th e m ixed integer p ro g ra m for sim ultaneous load in g an d scheduling w ith no back track in g of a FAS is p resented below.

M inim ize

Cmax (1)

su b je c t to

S im u lta n eo u s L oading an d Scheduling.. 355

Task a ssig n m e n t w ith no backtracking constraints

y x i j = ij j ^ j (2) ieij

y ) aijx ij ~ ^ i ^ i a (3)

j e J

x ij = x lj> j € J, i £ I j , l £ (4) x iq ^ x ij 4" £jr lj k £ K , j , g , f G z £ / j P'j I r : j —( g -4 r (5) P roduct a ssig n m e n t constraints

y Zihk > x a \ k £ K , j £ Jk, i € I j (6) he//;

E

^z>hJt

<

^1; i £ l , k £ K (7) hSHi

Zihk = A i ! 6 / x , i e -TbW. h £ H u f £ H t, k £ K \ m i = m l, h = f (8) P roduct com pletion constraints

C\k P. Pijkx ijt i £ I A , k £ K (9) jeJk

Cik 4“ Q (2 2-/r) ^ Cik 4“ ^ ) P lg k x lg , k £ H , j , r € 2 £ /yj I £ I T .

9£Jk

i ^ l , j < la s t{ J k) , r = n e x t ( j , J k) (10) P roduct non-in terferen ce constraints

Cik 4” Q ( 2 “I- P k s Z ih k Z ih s) ^ ^:3 ”1“ ^ 1 P i j k x ij ] i € d, h £ H i, k, S £ H k <C S (11) jeJk

Cis 4" Q ( 3 Dks Zihk Zihs') ^ dik 4“ ) ’ Pirsx in i £ J, h £ H i, k , S £ H . k <C S (12) r e J ,

B u ffe rin g constraints

Q—ik 4*Q (2 Xij X[r ) > diAiki k £ K , j , r £ 7^,2 £ Ij, I £ I r .

i ^ l , i < m , l > l , j ■< la s t( J k) , r = n e x t( j, Jk) (13) ci—ik Q (2 Xij Xir) di+ik] k £ H , j , r £ J k ,i € Jj , l £ dr :

i ^ l , i < m , l > l , j -< la s t{ J k ) ,r = n e x t( j,J k ) (14) Cik = d i-ik 4-

E

Pijkx ij 1 i € I A, k £ K : i > 1 (15)

jZJk

Ci+ifc = dik! i £ l A , k £ K : i < m (16) C o m pletion and departure tim e constraints

d i k < Q y x i j - , i £ l , k £ K (17)

je J k

Cik < dik', i £ I , k £ K (18)

d i k < C max\ i £ l , k £ K (19)

E Pijkx i j / m i < Cmax') i e I a (20)

ke.Kje.Jk

E

Pijkx ij < c maxi k £ K (21)

*G/a j€Jk

Variable e lim in a tio n constraints

Xij — 0; i G ^ A t j 0 I j (22)

yk, = 0; k , s e K : k > s (23)

Variable nonneg a tivity and integrality constraints

C i k > 0 \ i e I , k e K (24)

<Uk > 0; i 6 I , k 6 K (25)

Xij e { 0,1} ; i <= I , j 6 J (26)

z/fcJe { 0 , l } ; (27)

zih/t € {0, l} ; z € I , h 6 if), k <E K (28) T h e ob jectiv e fu n ctio n (1) represents th e schedule len g th to b e m inim ized. Con­

s tr a in t (2) ensures t h a t each ta sk ty p e is assigned to exactly one stage, an d (3) th a t to ta l space req u ired for th e ta sk s assigned to each assem bly sta g e does n o t exceed th e sta g e finite w ork space available. E q u atio n (4) ensures th a t th e buffering tasks are assigned to th e in p u t an d o u tp u t buffer of th e assem bly sta g e w here th e corre­

sp o n d in g assem bly ta sk is assigned. C o n s tra in t (5) ensures t h a t consecutive tasks of each p ro d u c t are assigned to th e sam e assem bly stage, so th a t b ac k trac k in g (re­

v isitin g of stages) is n o t required, (-< denotes precedence relatio n s am ong assem bly ta sk s).

C o n s tra in ts (6) a n d (7) ensure t h a t in every assem bly sta g e each p ro d u c t is assigned to exactly one processor, if a t le a st one of its required ta sk s is assigned to th is sta g e, a n d eq u a tio n (8) ensures th a t th e p ro d u c t is assigned to th e in p u t and o u tp u t buffers o f th e assem bly sta tio n selected by (6) and (7).

C o n s tra in t (9) ensures th a t each p ro d u c t is processed in all stag es, w here th e ta sk s req u ired for its com pletion are assigned, an d (10) m a in ta in s for each p ro d u ct th e precedence rela tio n s am ong its tasks.

C o n s tra in ts (11) an d (12) are p ro d u c t non-interference c o n stra in ts. No two p ro d ­ u c ts can b e perfo rm ed on th e sam e processor sim ultaneously. F or a given sequence of p ro d u c ts e ith e r c o n s tra in t (11) o r (12) is active, an d only if b o th p ro d u c ts k and s are assigned to th e sam e processor.

A p a ir o f c o n s tra in ts (13) a n d (14) in d ic ate th a t each p ro d u c t arrives in an in put buffer I — 1 o f an assem bly sta g e I € I a im m ed ia te ly a fte r its d e p a rtu re from the o u tp u t buffer i + 1 o f th e preceding assem bly stag e i £ I a of its processing route.

E q u a tio n (15) ensures t h a t in every sta g e i € I a assem bly of each p ro d u c t sta rts im m e d ia te ly a fte r its d e p a rtu re from th e in p u t buffer i — 1, a n d (16) t h a t each p ro d u c t arriv es in th e o u tp u t buffer i + 1 im m ed ia te ly a fte r its d e p a rtu re from the assem bly sta g e z 6 I a-

C o n s tra in t (17) ensures th a t th e p ro d u c t does n o t v isit stages w here its required ta sk s are n o t assigned, an d (18) in d ic ates th a t in every stage p ro d u c t d e p a rtu re tim e is n o t la te r th a n its com pletion tim e. F in ally (19) defines th e m ax im u m com pletion tim e, a n d (20), (21) im pose lower bounds, th a t ac co u n t on m ax im u m w orkload and m a x im u m to ta l processing tim e, respectively.

S im u lta n eo u s L oading an d Scheduling.. 357

3. Numerical examples

In th is section a n um erical exam ple an d som e c o m p u tatio n al resu lts are presented to illu s tra te a p p lic a tio n o f th e proposed m a th e m a tic a l pro g ram m in g form ulation.

T h e FAS config u ratio n for th e exam ple is shown in F ig. 1. T h e system is m ade u p m = 9 processing stages. T h e se t o f assem bly stages is I a — { 2 ,5 ,8 } and th e se t of buffering stag es is I b = { 1 ,3 ,4 ,6 ,7 ,9 } . E ach assem bly s ta tio n h as its in te rn al in p u t a n d o u tp u t buffer of a u n it capacity. T h e system consists o f m,- = 2 parallel processors in sta g es i = 1 ,2 ,3 , m , = 3 p arallel processors in stages i = 4 ,5 ,6 an d rrii = 2 p ara llel processors in stages i — 7 , 8 , 9.

R4 M5 R6

A—

►

B1

i___

M2 B3

1 r

i«—

— ►

R7 M8 ^{B 9}

Fig. 1. FAS with parallel stations Rys. 1. System z maszynami równoległymi

T h e p ro d u c tio n b a tc h consists of v = 7 p ro d u c ts to be assem bled o f n = 20 types of co m p o n en ts. T h e ord ered sets Ą , k 6 K of ta sk s required for each p ro d u c t k are show n below.

Ji

= ( 1 , 2 , 3 , 4 , 6 , 8 , 1 1 , 1 2 , 1 3 , 1 4 , 1 6 , 1 8 ) J 2 = ( 1 ,2 ,4 ,5 ,6 ,7 ,9 ,1 0 ,1 1 ,1 2 ,1 4 ,1 5 ,1 6 ,1 7 ,1 9 ,2 0 ) J 3 = ( 2 ,3 ,4 ,5 ,7 ,8 ,9 ,1 0 ,1 2 ,1 3 ,1 4 ,1 5 ,1 7 ,1 8 ,1 9 ,2 0 ) J 4 = ( 1 ,3 ,5 ,6 ,7 ,8 ,9 ,1 0 ,1 1 ,1 3 ,1 5 ,1 6 ,1 7 ,1 8 ,1 9 ,2 0 ) Js = ( 1 ,3 ,5 ,6 ,7 ,8 ,9 ,1 0 ,1 1 ,1 3 ,1 5 ,1 6 ,1 7 ,1 8 ,1 9 ,2 0 )

J 6 = ( 1 ,2 ,3 ,4 ,6 ,8 ,1 1 ,1 2 ,1 3 ,1 4 ,1 6 ,1 8 ) J 7 = ( 1 , 2 , 3 , 4 , 6 , 8 , 1 1 , 1 2 , 1 3 , 1 4 , 1 6 , 1 8 ) .

T h e assem bly tim es (pijk = Pjk, Vi € I j , j = 1 , . . . 20, k = 1 , . . . 7), w ork space req u ired for feeder assignm ents (a ij7-, i = 2 ,5 ,8 , j = 1 , . . -20), an d th e to ta l work space i = 2 ,5 ,8 ) available a t each s ta tio n are given below

4 . 4 .0 . 4 .4 . 4 .4 2 . 2 .2 . 0 .0 . 2 .2 2 , 0 ,2 , 2 ,2 , 2 ,2 2 , 2 ,2 , 0 ,0 , 2 ,2 0 , 4 ,4 , 4 ,4 , 0 ,0 2 , 2 ,0 , 2 ,2 , 2 ,2 0 , 3 ,3 , 3 ,3 , 0 ,0 5 .0 .5 . 5 .5 . 5 .5 0 , 2 ,2 , 2 ,2 , 0 ,0 0 , 4 ,4 , 4 ,4 , 0 ,0 4 . 4 .0 . 4 .4 . 4 .4 2 .2 .2 .0 .0 , 2 ,2 2 , 0 ,2 , 2 ,2 , 2 ,2 2 ,2 ,2 ,0 ,0 , 2 ,2 0 , 4 ,4 , 4 ,4 , 0 ,0 2 , 2 ,0 , 2 ,2 , 2 ,2 0 , 3 ,3 , 3 ,3 , 0 ,0 5 , 0 ,5 , 5 ,5 , 5 ,5 0 , 2 ,2 , 2 ,2 , 0 ,0 L 0 , 4 ,4 , 4 ,4 , 0 ,0

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b7 = 16, b5 = 20, b8 = 18.

For th e ex am p le p roblem th e m ixed integer pro g ram m in g ap p ro ach has con­

s tru c te d an assem bly schedule w ith m in im u m m akespan C max — 78. T h e schedule is show n in G a n tt c h a rt p resented in F ig. 2. In th e figure M in d ic ates an assem bly sta g e an d B s ta n d s for a buffering stage. P ro d u c ts are num bered a n d in d ic ated w ith different p a tte rn s .

In o rd e r to e v a lu a te perform ance of th e m ixed integer pro g ram m in g approach an d th e C P L E X solver, a d d itio n a l te s t instances of th e ex am ple p roblem w ere solved.

T h e p ro b lem ch a ra c te ristic s a n d co m p u ta tio n a l resu lts are show n in T able 2. For th e te s t in stan c es th e n um ber o f assem bly stages \Ia\ was equal to 3,5,6 or 10, the to ta l n u m b e r of processing stages m was 9,15,18 or 30, th e n u m b er o f assem bly task ty p es n was 10 or 20, a n d th e to ta l n u m b e r of assem bly ta sk s J2k=i 1*7*1 was 50 or 100. E ach sta g e i g I consists of m , = 2 p arallel processors.

T h e size o f th e m ixed integer p ro g ra m m in g m odel for th e te s t in stan ces is rep­

resented by th e to ta l n u m b er of variables, Var., n um ber of b in a ry variables, B in., n u m b e r o f co n s tra in ts , C o n str., a n d n u m b er o f nonzero coefficients, N o n z., in th e c o n s tra in t m a trix . T h e la s t tw o colum ns of th e ta b le give b e s t solu tio n value and

S im u lta n eo u s L oading an d Scheduling.. 359

Fig. 2. Assembly schedule for FAS with parallel stations

Rys. 2. Harmonogram montażu dla systemu z maszynami równoległymi

to ta l n u m b e r of nodes in th e b ra n c h -a n d -b o u n d tre e u n til th e b est solution was reached. T h e c o m p u ta tio n a l ex p erim en ts were perform ed w ith A M PL an d th e C P L E X v.6.5.2 on a C om paq P re sario la p to p w ith P en tiu m III, 450 MHz. T he c o m p u ta tio n tim e for each te s t in stan c e w as lim ite d to 3600 C P U seconds.

Table 2 P roblem Characteristics and Solution Results

m x TTii.n, Y %=i IJjfel Var. Bin. Constr. Nonz. r "771QI Nodes

9x2,10,50 354 227 1863 9059 41 511

9x2,20,100 434 307 5877 23652 83 858

15x2,20,100 708 497 10774 47335 71 1390

18x2,20,100 846 593 13980 62980 67 1316

30x2,20,100 1394 973 27937 138435 64 11163

* Best makespan found within tim e lim it of 3600 CPU seconds

F or th e te s t in stan c es C P L E X solver was n o t able to prove o p tim ality w ith in th e allow ed 3600 seconds of C P U tim e, however th e b e s t solutions were found much ea rlier th a n th e tim e lim it.

I t should b e n o te d t h a t th e num ber of ” no backtracking” c o n stra in ts (5) is 0 ( |/ 4 |n . 3u), w here \IA \, n , a n d v d en o te respectively, th e n um ber o f assem bly stages, n u m b er o f ta s k ty p es an d n u m b e r of p ro d u cts. In som e of th e te s t instances th e n u m b er of c o n s tra in ts (5) was as large as h a lf of th e to ta l num ber of all th e con­

s tra in ts , w hich in d ic ates th a t no back track in g requirem ent significantly co n trib u tes to th e c o m p u ta tio n tim e o f th e FAS loading an d scheduling problem .

T h e ex p e rim en ts w ith various featu res o f th e C P L E X solver to speed up the so lu tio n process have in d ic ated th a t th e b e s t resu lts are o b ta in e d for various non­

d e fa u lt se ttin g s o f th e b ra n c h -a n d -b o u n d alg o rith m . In m ost cases, th e b e st results were o b ta in e d for a n ea rly d ep th -first b ra n c h -a n d -b o u n d stra te g y for n ode selection a n d for th e stro n g b ran c h in g s tra te g y w ith a lim ite d n u m b er of different branches considered for different choices of b ran c h in g variable. F or such se ttin g s good feasible so lu tio n s w ere found m ore quickly an d fewer nodes were required to reach th e best solutions.

4. Conclusions

T h is p a p e r show s th a t m ixed integer p ro g ra m m in g ap p ro ach can be used to solve h a rd c o m b in ato ria l o p tim iz a tio n pro b lem o f sim u ltan eo u s loading an d scheduling a general flexible assem bly system w ith finite ca p ac ity in-process buffers, lim ite d work space for p a r t feeders a n d no rev isitin g o f sta tio n s. T h e proven o p tim al so lutions th a t can be o b ta in e d for sm all size problem s m ay also help to ev alu ate th e perform ance of v arious h eu ristic alg o rith m s c o n stru c te d for th e loading a n d scheduling problem s.

However, th e c o m p u ta tio n a l effort required to find proven o p tim a l schedules for rea listic pro b lem s can b e very high. In such cases a hierarchical, tw o-level approach (e.g. [6]) m ay help to find b e st assem bly schedules a t a m uch lower co m p u tatio n al cost. In th e two-level ap p ro a ch th e solu tio n of th e loading p roblem a t th e top-level c re ate s a jo b shop p roblem w ith finite in-process buffers to be solved a t th e base- level, w here b o th th e pro b lem s are sim p ler th a n th e original m ixed integer program for th e sim u lta n eo u s loading an d scheduling.

R E F E R E N C E S

1. H all N .G . an d S risk a n d a ra ja h C.: A survey o f m achine scheduling pro b lem s w ith b locking a n d n o-w ait in process. O perations Research, vol.44, 1996, pp.510-525.

2. J ia n g J a n d H siao W .: M a th e m a tic a l pro g ram m in g for th e scheduling problem w ith a lte r n a te process p la n s in FM S, C om puters and In d u stria l Engineering, vol.27, n o .10, 1994, pp.15-18.

3. K irkavak N, a n d D incer C.: A n aly tical lo ad in g m odels in flexible m an u factu rin g system s. European Jo urnal o f Operational Research, vol.71, 1993, pp.17-31.

4. M cC orm ick, S .T ., P in ed o M .L., Shenker S. a n d W olf B.: S equencing in an as­

sem bly line w ith blocking to m inim ize cycle tim e. Operations Research, vol.37, 1989, pp.925-936.

5. Saw ik T .: P roduction P la n n in g and Scheduling in Flexible A ssem bly System s.

S pringer-V erlag, Berlin. 1999.

6. Saw ik T .: S im u ltan eo u s versus sequential loading an d scheduling o f flexible as­

sem bly system s. In te rn a tio n a l Jo urnal o f P roduction Research, vol. 38, 2000, pp.3267-3282.

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7. Saw ik T .: M ixed integer pro g ram m in g for scheduling surface m o u n t technology lines. In te rn a tio n a l Jo u rn a l o f P roduction Research, vol. 39, 2001, pp. 3219-3235.

R ecenzent: D r hab. inż. M irosław Zaborow ski, P rof. Pol. Śl.

S t r e s z c z e n i e

W p rac y p rzedstaw iono m odel program ow ania całkowitoliczbowego m ieszanego do jednoczesnego obciążen ia m aszyn i szeregow ania z a d ań w elastycznym sys­

tem ie m ontażow ym . S ystem sk ła d a się z w ielu stadiów m ontażow ych połączonych siecią tra n sp o rto w ą , zaś każde sta d iu m obejm uje je d n ą lu b kilka jednakow ych m aszyn p rac u jąc y ch rów nolegle. K aż d a m aszy n a m a bufor wejściowy i wyjściowy o skończonej pojem ności oraz ograniczoną przestrzeń roboczą, w której um ieszczane są p o d a jn ik i m ontow anych części. W system ie m ontow ane są jednocześnie różne typy w yrobów . K ażdy w yrób przechodzi w różnej kolejności przez wiele stadiów m ontażow ych, o d w ied zając co najw yżej raz każde sta d iu m . N ależy w yznaczyć rozdział z a d a ń m ontażow ych i p o d ajn ik ó w części pom iędzy sta d ia oraz h arm ono­

g ram m o n ta ż u bez pow rotów w yrobów do ra z odw iedzanych stadiów , ta k aby zm ini­

m alizow ać czas w ykonyw ania zadanego zbioru wyrobów . W yniki eksperym entów obliczeniow ych ilu s tru ją zastosow anie proponow anego podejścia.