Single electron tunneling based arithmetic computation

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Single Electron Tunneling

Based Arithmetic Computation

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof.dr.ir. J.T. Fokkema, voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op woensdag 24 november 2004 om 10:30 uur

door

Caspar Robert LAGEWEG

elektrotechnisch ingenieur geboren te Haarlem, Nederland

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Dit proefschrift is goedgekeurd door de promotor: Prof.dr. S. Vassiliadis

Toegevoegd promotor: Dr. S. Cotofana

Samenstelling promotiecommissie: Rector Magnificus, voorzitter

Prof.dr. S. Vassiliadis, TU Delft, promotor

Dr. S.D. Cotofana, TU Delft, toegevoegd promotor Prof.dr. N.J. Dimopoulos, University of Victoria

Prof.dr. M. Glesner, Technische Universit¨at Darmstadt

Prof.dr. Y. Leblebici, Ecole Polytechnique Federale de Lausanne Prof.dr. R. Stefanelli, Politecnico di Milano

Prof.dr. J.R. Long, TU Delft

Prof.dr. C.I.M. Beenakker, TU Delft, reservelid

ISBN 90-9018686-7 NUG 959

Keywords: Single electron tunneling, arithmetic circuits, logic design Cover photo c2004 Torben Linde, København, Denmark

Copyright c 2004 C.R. Lageweg

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author.

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To those who made this possible, and those that should have been here...

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Single Electron Tunneling

Based Arithmetic Computation

Caspar Robert Lageweg

Abstract

I

n this dissertation we investigate the implementation of computer

arith-metic operations with Single Electron Tunneling (SET) technology based circuits. In our research we focus on the effective utilization of the SET technology’s specific characteristic, i.e., the ability to control the transport of individual electrons. We pursue two main research directions: Single Elec-tron Encoded Logic (SEEL) and ElecElec-tron Counting (EC) arithmetic. All the design we propose are verified by means of simulation and evaluated in terms of area, delay and energy consumption. The first line of research, i.e., the SEEL paradigm, is based on encoding Boolean variables as a net charge of zero or one electron thus charge transport in a SEEL gate due to switching activity is limited to one electron. Within the SEEL paradigm we first pro-pose a generic Threshold Logic Gate (TLG) from which we derive a Boolean logic gate family. Subsequently, we investigate the behavior of the SEEL TLG as a network component, argue that buffering is a method to reduce crosstalk problems and propose four SEEL buffers. A buffer choice is argued, based on TLG buffering suitability, and subsequently utilized to implement buffered Boolean gates. We next explore SEEL implementations of memory elements and propose static latches, flip-flops and dynamic memory elements. Given the above components, i.e., SEEL Boolean gates, threshold gates and memory elements, we propose building blocks for serial adders, ripple carry adders, carry-lookahead adders and tree multipliers and evaluate the above adders and multipliers. The second line of research, i.e., the EC paradigm, is based on encoding integer values as charge and performing arithmetic operations on charge encoded operands. Within the EC paradigm we first suggest a set of EC building blocks and propose generic schemes for EC based addition and multi-plication. We then assume that limited amounts of charge can be transported in an EC block and propose designs for high radix EC addition and multiplication that can manage such limitations.

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Acknowledgments

The work presented in this dissertation represents the outcome of my Ph.D. research at the Computer Engineering (CE) laboratory of the Electrical Engi-neering department, Delft University of Technology, Delft, The Netherlands. During this time I have come across many people who have supported and inspired me in different ways.

First, I want to thank my family for their support during the many years that have brought me to where I am today. Life has its ups and downs and your support has always helped me through the downward turns of life

I next want to thank my former colleagues at the Hewlett-Packard labs in Bris-tol, UK, and in particular Stuart Quick, for guidance and friendship. Besides presenting me with the experience of working in a corporate research environ-ment, my stay at HP Labs also increased my interests in research.

I want to sincerely thank my adviser, Stamatis Vassiliadis, for his many con-tributions during the years which I’ve had the privilege of knowing him. He has inspired me to pursue a Ph.D. study, presented me with the opportunity to do Ph.D. research in the emerging field of nano-electronics, and kept me on-course during the various storms in the Ph.D. landscape.

I am most grateful for the countless contributions of my co-adviser Sorin Coto-fana. When I started my research, I knew virtually nothing about the field of nano-electronics and quantum-electronics. Sorin has kept me focused on the bigger picture, and has helped me to stay structured and focused throughout. He has inspired and improved my work in many ways, including academic thinking and technical writing. He also taught me how to appreciate fine cigars and cognac.

I want to thank all colleagues at the CE lab for providing a fun and friendly place to work in. I will fondly remember the many conversations during lunch-breaks about anything and (mostly) nothing. I want to specifically thank

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Stephan Wong and Pyrrhos Stathis for providing me with opportunities to clear my mind when I hit a wall with thinking.

Last, and the opposite of least, I want to thank my wife Chantal (and my son Noah) for their love, support, and understanding over the year(s) (although Noah is only 1 year old). There truly is no place like Home!

C.R. Lageweg Delft, The Netherlands, 2004

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Chapter 1 Introduction

D

uring the last six decades we have witnessed spectacular increases in

the processing power of logic and arithmetic circuits. These increases were to a large extend due to advances in algorithms and device tech-nology [22]. Since the seventies the microelectronics industry has followed Moore’s “law” [48], doubling the number of processing elements every 18 months. Feature size reduction in microelectronic circuits, and the correspond-ing increase in the number of transistors per cm2, have been important con-tributing factors to this dramatic increase.

Currently, circuit technology is primarily based on (C)MOS devices and it is anticipated that CMOS feature sizes will continue to be scaled down in the near future. The 2003 edition of the International Technology Roadmap for Semiconductors [63] predicts that in 15 years ultra-thin body (UTB) MOS-FETs will reach gate lengths of 10 nm. However, it also predicts that such devices will increasingly operate in a quasi-ballistic mode, i.e., with electrical currents dwindling down to individual electrons. Note that this is already oc-curring in today’s circuits in the form of undesired tunnel currents through thin oxides [5, 24, 47]. Consequently, the switching behavior of future MOSFET devices will greatly differ from MOSFET behavior in the traditional sense. On the other hand, it is generally accepted that sooner or later MOS based cir-cuits cannot be reduced further in (feature) size due to fundamental physical restrictions [61].

Given the anticipated end of the CMOS era, several candidate technologies based on alternative operating principles have been under investigation for the last two decades. These candidate technologies include, amongst others, Sin-gle Electron Tunneling (SET), Carbon Nanotubes, Rapid SinSin-gle Flux Quantum

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2 CHAPTER1. INTRODUCTION

(RSFQ), Resonant Tunneling Diodes (RTD), and Magnetic Spin devices (see [62] for an overview of some of these emerging technologies). As of yet it is undecided which of these technologies, if any, will supplant (C)MOS. If a candidate technology is to replace (C)MOS in at least some application areas, it must satisfy as many of the following criteria as possible. First, the candi-date technology should have greater feature size scaling potential then CMOS, i.e., larger device density. Second, given the anticipated device density the candidate technology should have extremely low energy consumption. Note that energy consumption is one of the main problems anticipated for (C)MOS in the near future [63]. Third, it should be able to operate at room tempera-ture as liquid cooling would encumber potential systems with added cost and bulk. Fourth, device switching should occur sufficiently fast, such that when the device is used in conjunction with the appropriate design techniques and architectures to build circuits and systems it can compete with or outperform “equivalent” (C)MOS based designs.

(a) Conventional process. (b) Carbon nanotube.

Figure 1.1: SET inverter implementations.

In this dissertation we focus on the SET technology [41, 38]. As an emerg-ing technology the SET technology offers a number of advantages as follows. First, it offers a greater scaling potential than (C)MOS as the device structure is less complex. Second, SET has the potential to realize circuits that consume much less energy than (C)MOS circuits. Third, recent advances in silicon

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3

based fabrication technology (see for example [51]) indicate that SET based circuits have the potential to operate at room temperature. An additional bene-fit of the SET technology is that SET quantum tunnel junctions, the basic SET circuit element, can be fabricated in many different ways. In order to illustrate the variety in possible implementation technologies, we present in Figure 1.1 two possible implementations of the SET inverter [64]. Figure 1.1(a) depicts an SET inverter fabricated in a conventional lithographic technology on sil-icon [21]. In this case the tunnel junctions resemble conventional capacitors and consist of small gaps between conducting plates. Figure 1.1(b) on the other hand depicts a carbon nanotube based implementation [23] in which case the tunnel junctions consists of small gaps in a multiwall carbon nanotube. When examining the progress made thus far with the SET technology as a whole, one can roughly divide previous research in two main categories. The first category consists of device research and is mainly focused on device fab-rication and fabfab-rication technology aspects. When surveying the field as a whole, one can certainly observe that the main research effort has occurred in this category. The second category of SET research focuses on the applica-tion of SET devices for various purposes, such as logic design and memory fabrication. The work presented in this thesis falls within the second category. Given that the main SET research effort has thus far occurred at the device level, limited innovation has occurred at the circuit and system level. Mainly, there have been attempts to mold the technology to a CMOS-like design style by making devices that mimic the behavior of the MOS transistor [37, 64, 44, 30, 14, 7, 73, 26]. Given that SET devices exhibit a different behavior than the MOS transistor, such attempts make limited use of the potential of the technology itself. It is our belief that an emerging (nano)technology such as SET can only be effectively used if its specific behavior is explicitly utilized at all design levels, i.e., device, circuit and system. In other words, one should examine and utilize a technology’s unique features.

The distinguishing feature of the SET technology is that charge transport oc-curs in discrete quantities, i.e., one electron at a time. This offers the ability to design circuits in which the transport of individual electrons can be accurately controlled. In this thesis we address the effective utilization of the SET tech-nology for the design and implementation of computer arithmetic operations. More specifically, we pursue two main lines of research: single electron en-coded logic and electron counting based arithmetic. Single electron enen-coded logic is based on encoding logic values with single electrons. Electron count-ing arithmetic is based on encodcount-ing variables as charge quantities and

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imple-4 CHAPTER1. INTRODUCTION

menting arithmetic operations via controlled charge transports.

The work presented in this thesis is intended to be general, i.e., independent of a manufacturing process. SET switching behavior is based on a fundamental physical phenomenon, i.e., the quantized nature of charge transport that occurs in nanometer-scale devices. In our research we focused on applications that utilize this fundamental behavior. As such we have ignored practical problems that dominate current experimental SET circuits such as the background charge and the limited temperature ranges at which these circuits operate correctly. The remainder of this chapter is organized as follows. In Section 1.1 we present the theoretical background of SET and its switching and delay mod-els. Section 1.2 investigates related work and states the open questions which arise from this investigation. The structure of the remainder of the thesis is discussed in brief in Section 1.3.

1.1 SET Background

The SET technology introduces the quantum tunnel junction as a new circuit element for (logic) circuits. A tunnel junction can be viewed as two (metal) conductors, separated by a thin layer of insulating material, as depicted in Fig-ure 1.2. The tunnel junction can be thought of as a ”leaky” capacitor, such that the ”leaking” can be controlled by the voltage across the tunnel junction. Although this behavior at first glance appears similar to that of a diode, the dif-ference stands in the scale at which switching occurs. Charge transport though a tunnel junction can only occur in quantities of a single electron at a time. Additionally, given the feature sizes anticipated for such circuits, the transport of a single electron can have a significant effect on the voltage across a tunnel junction, such that transporting a few electrons through a tunnel junction will inhibit further charge transport, making it possible to control the transport of charge in discrete and accurate quantities.

SET devices (see [39, 32] for overview papers) consist of tunnel junctions and capacitors. A tunnel junction is characterized by a capacitance Cj and a

resistance Rj, each of which depends on the physical size of the tunnel

junc-tion and the thickness of the insulator. In classical physics the transport of charge through an insulator is considered impossible. However, according to quantum physics theory, one can calculate the probability that an electron will tunnel through such an energy barrier. This probability is relatively large if the tunneling is energetically favorable, or in other words, if it lowers the total amount of energy present in the entire circuit [17].

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1.1. SET BACKGROUND 5 Embedding Circuit symbol 00 00 00 00 11 11 11 11 insulator metal metal

Figure 1.2: Schematic representation of the quantum tunnel junction.

The operating principle of SET circuits is based on the controlled transport of charge through tunnel junctions. The transport of charge through a tunnel junc-tion is referred to as tunneling, where the transport of a single electron through a tunnel junction is referred to as a tunnel event. It is assumed that a tunnel event is only possible if this is energetically favorable for the complete circuit in which the tunnel junction is embedded. When tunneling occurs, electrons are considered to tunnel through a tunnel junction strictly one after another [1]. The minimum amount of charge that can thus be transported though a tunnel junction is a single electron. However, the charge present on a tun-nel junction can have any value, including arbitrary fractions of the electron charge. In quantum physics, the electron can be perceived as both a particle and a wave function. Non-integer multiples of the electron charge result from electrons with a part of their wave function on the tunnel junction and a part of it elsewhere.

When tunneling does not occur, the electrical behavior of the SET tunnel junc-tion corresponds with a classic capacitor. A capacitor Cj containing a charge

q contributes _2Cq2

j to the energy present in the circuit. This implies that tunnel

events change the energy of the circuit in steps of:

q_e2

2Cj ≡ Ec

(1.1) In the equation above, as well as in the remainder of the thesis, we refer to the charge of the electron as qe = 1.602 ∗ 10−19C 1. The energy Ec is referred

to as the charging energy, and it is the characteristic energy scale at which 1

Strictly speaking this is incorrect, as the charge of the electron is of course negative. How-ever, it is more intuitive to considerqeas a positive constant for the formulas which determine

whether or not a tunnel event will occur. We correct for this when we discuss the direction in which the tunnel event takes place.

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tunneling occurs. The charging energy is the dominant form of energy if it is large when compared to all other forms of energy present in the circuit. Electron tunneling is a quantum mechanical process, governed by the principle that the electron’s wave function extends through the tunnel barrier. In order to have charge quantization, the electron’s wave function should be located either on one side of the barrier or on the other side. Therefore, quantum charge fluctuations must be small. Heisenberg’s uncertainty principle states that quantum charge fluctuations appear on an energy scale Eq with a time

scale of τ . The product satisfies Eqτ ≥ h (Planck’s constant h = 6.6 ∗

10−34_{J s). The time scale associated with tunneling through a junction is τ} _≈

RjCj. The charging energy Ecdominates over quantum charge fluctuations if

Ec >> Eq. Therefore, for proper operation of SET circuits it is required that:

Ecτ >> Eqτ ⇔ e2 2Cj RjCj >> h⇔ Rj >> h e2 = 25.8kΩ (1.2)

A commonly used value for the tunnel resistance Rj is 100kΩ. Under the

above condition the electron can be considered as a particle, rather than a wave function [70].

The second form of energy which is relevant to the observability of single electron tunneling events is the thermal energy. The energy associated with thermal fluctuations is kBT (Boltzman’s constant kB = 1.38 ∗ 10−23J/K).

The charging energy dominates over the thermal energy if:

Ec >> kBT (1.3)

Combining Equations (1.3) and (1.1) the above implies that in order for the single electron charging effects to be observable at room temperature (T ≈ 300K) we need Cj to be in the order of 1 aF or less. When both the quantum

charge fluctuation energy and the thermal energy are much smaller than the electron charging energy, single electron charging effects become observable as the charging energy is the dominant form of energy present in the circuit. Concluding, if the above conditions are satisfied one can successfully control the transport of individual electrons within the system.

When determining the probability of a potential tunnel event, one must calcu-late the amount of free energy before (Finitial) and after (Ff inal) the tunnel

event. Such a potential tunnel event changes the amount of free energy by ΔE = Ff inal− Finitial. If the amount of free energy decreases (ΔE < 0), the

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1.1. SET BACKGROUND 7

probability of the tunnel event is zero for T = 0K and if T > 0K but Equa-tion (1.3) is satisfied, the probability of the tunnel event is larger than zero but it can be ignored.

The average number of tunnel events per second Γ is calculated as follows [18]:

Γ = −ΔE

q_e2Rj

1

(eΔE/kBT − 1) (1.4)

When T = 0K or ΔE >> kBT Equation (1.5) reduces to:

Γ = −ΔE/q2

eRj if ΔE < 0 (1.5)

Γ = 0 if ΔE > 0 (1.6)

The amount of free energy F that is present in a circuit consists of charge which is stored on capacitors (including junctions), and of charge that has been transported by voltage sources. The free energy F is calculated as follows. Each capacitor Ci containing a charge of qi contributes to the free energy F

by an amount q2i

2Ci. In a circuit consisting of k capacitors Ci that each contain

a charge of qi, and of l voltage source Vj that have each transferred a charge

qj(t) since t = 0, the total amount of free energy in the circuit is calculated as:

F = k−1 i=0 q2_i 2Ci − l−1 j=0 qj(t)Vj (1.7)

Given the above equation, one can calculate the amount of free energy be-fore (Finitial) and after (Ff inal) potential tunnel events and calculate the

cor-responding change in free energy ΔE = Ff inal− Finitial. For large circuits,

consisting of many capacitors, tunnel junctions and voltage sources, calculat-ing ΔE for each potential tunnel event becomes increascalculat-ingly complicated. For each tunnel junction, calculating the effect of potential tunnel events on ΔE can be simplified by introducing the equivalent capacitance Ce. The

ca-pacitance Cerepresents the circuit that embeds the tunnel junction, and

con-sists of all other tunnel junctions and capacitors in the circuit. We define the charge on the tunnel junction before and after a tunnel event as qj and qj,

re-spectively. Likewise, we define the charge on Ce (modeling the rest of the

circuit) before and after the tunnel event as qrand qr, respectively. The change

in free energy ΔE due to a tunnel event can then be calculated as [67, 69]: ΔE = q_j2 2Cj + qr2 2Ce − q2_j 2Cj + q2r 2Ce (1.8)

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The above equation can be further simplified by introducing the critical change

qc, resulting in [67, 69]: ΔE = −qe Cj (|qj| − qc ) (1.9) qc = qe 2 · 1 (1 + Ce/Cj) (1.10)

Given that the schemes we present in this thesis assume voltages based signals, we derive from Equations (1.9) and (1.10) the calculation of ΔE based on the

critical voltage Vc: ΔE = −qe(|Vj| − Vc) (1.11) Vc = qc Cj = qe 2(Ce+ Cj) (1.12)

One can observe from the above two equations that ΔE is only negative if

|Vj| > Vc. Combining Equations (1.5) and (1.11), the tunneling rate can be

expressed as:

Γ = |Vj| − Vc

qeRj

(1.13) The critical voltage Vc, also referred to as the Coulomb gap, acts as a voltage

threshold for tunnel events and is the minimum voltage needed across the tun-nel junction in order to make tuntun-neling possible (ΔE < 0). An advantage of the above is that Vc only has to be calculated once per tunnel junction and it

is independent of the current value of the voltage sources and the charge dis-tribution throughout the circuit (i.e., the current ’state’ of the circuit). If the absolute value of the voltage across the tunnel junction |Vj| is less then the

critical voltage, the tunnel junction is in Coulomb blockade. If tunnel events cannot occur in any of the circuit’s tunnel junctions, i.e., |Vj| < Vc for all

junctions in the circuit, the circuit is in a stable state. In this thesis we focus on circuits where a limited number of tunnel events may occur, after which the circuit is in a stable state. The stable state determines the current output value that results from the current charge distribution.

Summarizing the above, tunnel events will occur through a tunnel junction if and only if:

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1.1. SET BACKGROUND 9 2 V V 1 C_e C C 3 2 C 1 C j C_j

Figure 1.3: Reducing the embedding circuit to an equivalent capacitor Ce.

In order to demonstrate the calculation of the critical voltage Vc we present

an example circuit as depicted in Figure 1.3. When calculating the equivalent capacitance Ce, voltage sources are considered to have and infinitely large

capacitance. Ground points form one reference node and when calculating Ce

all ground points are considered to be connected together. For this example

Ceis formed by C1in series with C2+ C3(capacitors C2and C3in parallel),

i.e., Ce = _CC1₁_+C(C2₂+C_+C3₃). Assuming Cj = C1 = C2 = C3 = 1aF , we find that

Ce= 2₃aF . Using Equation (1.12), we find that Vc = ₂₍2 qe

3aF+1aF ) = 48mV .

0 1 2 3

Figure 1.4: State transition diagram for a Poisson process.

Given that electron tunneling is a quantum physical process, the transport of individual electrons can only be described by a stochastic process. This implies that we can at most calculate the chance that an electron has tunneled through a tunnel junction after a time interval td. Given that we are interested in the delay

of individual tunnel events, calculating the average delay 1/Γ, as suggested in [65] for calculating small currents, is not accurate enough. Thus we apply stochastic modeling to the charge transport in order to calculate the charge transport probabilities. If tunneling can occur in multiple tunnel junctions, i.e., multiple tunnel events have a non-zero probability, the complexity of these stochastic calculations increases dramatically. For this discussion we assume a system in which only one tunnel junction has non-zero tunneling probability at a time. Once the first tunnel event has been resolved other tunnel events are processed in the same junction until no more are possible. Tunnel events can

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therefor form a chain of events, each of which must be resolved before the next one occurs. Assuming a constant tunneling rate Γ, the chain can be described as a Poisson process as depicted in Figure 1.4 in which the state n represents the number of electrons transported thus far. The Poisson process describes the evolution in a single direction through a discrete set of states, where all states have equal transition rate to the next state. The Poisson process starts in the state n = 0, and evolves monotonously.

The master equations of the Poisson process are:

dPn(t)

dt = ΓPn−1(t) (1.15)

P₀(t = 0) = 1 (1.16)

where Pn(t) is the probability of being in a state n after t time, and Γ the

transition rate between neighboring states in the transition diagram. These equations can be solved via Laplace transformation of the Poisson process as:

Pn(t) =

(Γt)n

n! e

−Γt _(1.17)

In SET circuits, the state n corresponds with the number of transported elec-trons. If one assumes that switching is accomplished through the transport of one or more electrons then P₀(td) is the probability that no charge has been

transported after td seconds. In other words, P0(td) is the error probability

after tdseconds which is calculated as:

Perror= P0(td) = e−Γtd (1.18)

If we assume a switching accuracy of 1−Perror, then tdis the minimum delay

which is required to reach this accuracy and it is calculated as:

td= −

ln(Perror)

Γ (1.19)

Combining Equations (1.13) and (1.19), we can express the minimum delay as follows:

td= −

ln(Perror)qeRj

|Vj| − Vc

, (1.20)

In the remainder of this dissertation, unless otherwise stated, the following values are assumed: Rj = 105Ω and Perror = 10−8. Although Rj depends

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1.1. SET BACKGROUND 11

The error probability Perrordetermines the reliability of the circuit. Given that

switching in SET circuits is stochastic in nature, the error probability cannot be reduced to 0. It is therefore assumed that an error reduction mechanism in the form of hardware or data redundancy, as for example suggested in [20, 57], can be embedded in all the schemes that we present in this thesis in order to achieve the desired accuracy. In general, one can observe from Equation (1.20) that a trade-off exists between the delay and the error rate. There are two methods to approach this issue. First, we can assume a certain error probability Perror

and calculate the corresponding delay td. Second, we can target a certain

de-lay tdand calculate the corresponding error probability. If the resulting error

probability is too large it can be reduced by an error reduction mechanism. In addition to the switching error probability as described in Equation (1.20) there are two other fundamental phenomena that may cause errors: thermal tunneling and co-tunneling. Given a maximum acceptable switching error probability, we must ensure that the thermal error probability as well as the co-tunneling error probability are of the same order of magnitude as the switching error probability or less.

For any temperature T > 0 there exists a non-zero probability that a tunnel event will occur through a junction even if|Vj| < Vc. The error probability

Pthermdue to thermal tunneling can be described by a simple formula as:

Ptherm = e−ΔE/KBT (1.21)

For practical purposes, this implies that, if we intend to add or remove charge to a circuit node by means of tunnel events, the total capacitance attached to such circuit nodes must be less then 900aF for 1K temperature operation, or less then 3aF for 300K (room temperature) operation [16]. This represents a major SET fabrication technology hurdle as even for cryostat temperature operation very small circuit features are required to implement such small capacitors. For a multi-junction system in which a combination of tunnel events leads to a reduction of the energy present in the entire system there exists a non-zero probability that those tunnel events occur simultaneously even if |Vj| < Vc

for all individual tunnel junction involved. This phenomenon is commonly re-ferred to as co-tunneling [3, 2]. Although a detailed analysis of co-tunneling is outside the scope of the present work, we remark that several means are avail-able to reduce the co-tunneling error probability. First, the ratio of co-tunneling rate to desired tunneling rate can be reduced linearly by increasing the tunnel resistance Rjof the tunnel junctions involved in co-tunneling. The main

prob-lem of this approach is that it also linearly increases the switching delay as stated in Equation (1.20). Second, each of the individual junctions involved in

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the co-tunneling process can be replaced by N junctions (N > 1) separated by islands. Although such an approach results in an exponential decrease of the co-tunneling probability, it also approximately results in a linear increase in the delay time as an electron must now tunnel through N times as many junctions as before. Third, resistors can be added between the SET circuit and the sup-ply voltage lines as demonstrated in [43, 75, 42]. This method can reduce the co-tunneling rate without significantly increasing the delay. This is due to the fact that the delay added by a resistor is on the RC scale. Thus, assuming for example R = O(106) Ω and C = O(10−17) F , we find that the delay added by the resistor is tRC = O(10−11) s. Given that for the structures we propose

in this thesis the switching delay is at least in the order of 10−9seconds when assuming such values for R and C, the additional delay due to the co-tunneling suppressing resistors would be negligible. Although the circuits discussed in the remainder of this dissertation do not contain such resistors, co-tunneling suppressing resistors of appropriate value can be appended to our designs in order to reduce the co-tunneling error to an acceptable error probability. The biggest technological challenge currently comes from the fact that thus far all experimental SET circuits have displayed a random background charge (random charge present on circuit nodes), which is assumed to be the result of trapped charge particles in the tunnel junctions themselves or in the sub-strate. This random charge results in a random additional voltage across tunnel junctions, which can cause errors in their switching behavior. The origins of the background charge problem are not yet clear and several possible sources are reported in literature [58, 40, 74]. At the same time there are indications [39] that the offset charge problem may reduce or even disappear entire for the nanometer-scale feature size circuits required for room temperature operations. Given this and the fact that our investigation is intended to be independent of a manufacturing process, we ignore the aspects related to background charge and its potential influence on SET based computational structures.

1.2

1.3 Thesis Framework

The remainder of the dissertation is organized as follows:

• Chapter 2 investigates the implementation of SEEL threshold logic

gates. We first introduce the concept of threshold logic. Subsequently, we present the SET electron box circuit, consisting of one junction and one capacitor, which can be thought of as a one input threshold gate. Us-ing the electron box as a basis, we propose a SUs-ingle Electron Encoded Logic (SEEL) generic linear threshold gate scheme. This scheme is ex-emplified by implementing 2-input AND, OR, NAND, and NOR gates as instances of the generic threshold gate. We simulate the proposed im-plementations and calculate their area, delay and energy consumption.

• Chapter 3 investigates the design of networks of SEEL threshold logic

gates. We first discuss the crosstalk problems that arise when SEEL threshold gates are utilized as components in a network structure. We subsequently argue that augmenting these threshold gates with an ac-tive buffer reduces these crosstalk problems. We propose two types of dynamic buffers and two types of static buffers that each operate ac-cording to the SEEL paradigm. The correct operation of each of the proposed buffer implementations is verified by means of simulation. We conclude that the static inverting buffer is the most suitable candidate for our intended purpose, i.e., buffering SEEL linear threshold gates. We then present a family of 2-input Boolean logic gates which are derived from the generic SEEL threshold gate and subsequently buffered with the static inverting buffer. Furthermore, we calculate the area, delay and energy consumption of these Boolean gates. In order to demonstrate that the gates can operate correctly in a network structure, we implement an example gate network with such buffered gates and verify the gate net-work by means of simulation. Finally, we argue that although the static inverting buffer can be utilized as a buffer for any instance of the generic

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1.3. THESIS FRAMEWORK 19

linear threshold gate, the circuit parameters of the buffer depend on the particular threshold gate instance. The resulting design trade-offs are subsequently investigated.

• Chapter 4 investigates the implementation of SET based memory

ele-ments that operate in accordance with the SEEL paradigm. Given that practical computational systems require both combinatorial logic and memory elements such that (intermediate) results and status informa-tion can be stored for later processing, the implementainforma-tion of memory elements forms an important aspect of any technology. After a brief in-troduction of memory elements, we first investigate the implementation of the RS-latch, the D-latch and the flip-flop based on Boolean logic gates as found in most logic design textbooks. Given that the SEEL Boolean gates are derived from a generic threshold gate scheme, we next investigate the same three memory elements implemented directly in threshold logic gates. Subsequently, we explore memory elements that utilize the specific behavior of the tunnel junction. We then com-pare the Boolean gate and threshold gate based RS-latch, D-latch, and flip-flop implementations in terms of circuit area, switching delay and energy consumption.

• In chapter 5 we investigate the implementation of 2-1 binary addition.

We first discus serial addition and propose Boolean logic gate (BLG) and threshold logic gate (TLG) based implementations of the full adder. Subsequently, we propose BLG and TLG based 1-bit and k-bit serial adders and calculate the area, delay and energy consumption. Second, we discuss parallel addition, propose BLG and TLG based implementa-tions of ripple carry adders, and calculate their area, delay and energy consumption. We then propose BLG and TLG based implementations of two types of look-ahead carry generator (LCG) blocks and calculate the the area, delay and energy consumption of TLG and BLG based 16-bit, 32-bit and 64-bit carry lookahead adders. Given the poor delay of the TLG based LCG blocks, we subsequently propose delay optimized versions of the TLG based LCG blocks, and calculate the area, delay and energy consumption of delay optimized 16-bit, 32-bit and 64-bit carry lookahead adders.

• Chapter 6 investigates the implementation of binary multiplication.

First, we propose a Boolean gate full adder based implementation of the 7/3 counter (v1) and a threshold gate full adder based implemen-tation of the 7/3 counter (v2). We subsequently propose a threshold

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gate based implementation of the 7/3 counter (v3), verify the v3 design by means of simulation, and calculate the area, delay and energy con-sumption of each of the three 7/3 counter implementations. Second, we propose 16 and 32-bit tree multipliers based on the v2 and v3 7/3 counter designs, and analyze these multipliers in terms of area, delay and energy consumption. Third, we investigate an alternative designs for the 32-bit multiplier that is based only on 3/2 counters. As our cal-culations indicate that the 7/3 counter based implementations are less effective than expected we subsequently propose an improved threshold gate based 7/3 counters (v4) and evaluate the implications of this new design on the area, delay and energy consumption of the 16 and 32-bit multipliers.

• In Chapter 7 we investigate the implementation of addition and

multipli-cation based on the electron counting paradigm. The electron counting paradigm is based on encoding integer values X directly as a net extra charge Xqe. First, we propose a set of two electron counting building

blocks which can be utilized for electron counting computations. Sec-ond, using the set of building blocks, we propose schemes for comput-ing addition related arithmetic functions, e.g., addition and multiplica-tion, for which it is assumed that the number of the electrons that can be accurately controlled within the system is unrestricted. Third, we in-vestigate high radix electron counting for the more practical case when the number of the electrons that can be accurately controlled is limited. Fourth, we introduce SET based implementations for the two proposed blocks and evaluate their area and delay. Finally, we propose SET based implementations for the following circuits operating under the electron counting paradigm: 4-bit Digital to Analog Converter, 5-bit Analog to Digital Converter, 4-bit adder, and 3-bit multiplier.

• Chapter 8 concludes the thesis by presenting an overview of the thesis,

summarizing its main contributions and suggesting directions for future research.

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Chapter 2 SEEL Threshold Logic Gates

T

he implementation of Boolean logic functions in current computer

(arithmetic) circuits is still predominantly based on traditional Boolean logic gates, such as those that calculate the logic AND, OR, NAND, and NOR functions. This has thus far proved to be a very effective ap-proach, particularly for (C)MOS circuits, resulting in compact designs and high switching speeds. However, Single Electron Tunneling (SET) is a tech-nology whose switching behavior differs greatly from CMOS. Therefore, there probably exist more efficient design styles that make better use of the SET technology.

When examining existing proposals for SET based logic circuits, one notices that the majority of these are mainly based on the so-called SET transistor [37]. The SET transistor can be biased such that it mimics the behavior of the PMOS or the NMOS transistor. Consequently, SET transistor based circuits can be utilized to implement the standard Boolean logic gates in a CMOS-like approach [64]. However, such circuits typically require the transport of a relatively large number of electrons in order to switch their output value. This results in increased delay and energy consumption. We thus believe that this approach does not use the SET technology to its full potential.

A technology can be used more efficiently if its specific behavior is explic-itly utilized. In the case of SET technology, its unique characteristic is the ability to control the transport of single electrons. This suggests the potential to implement Single Electron Encoded Logic (SEEL), in which the Boolean logic values ’0’ and ’1’ are encoded as a net charge of 0qe and 1qe.

Addi-tionally, when examining the switching behavior of a single tunnel junction, one observes that a voltage threshold must be overcome in order to transport

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22 CHAPTER2. SEEL THRESHOLDLOGICGATES

charge. We therefore argue that SET technology holds promise for an efficient implementation of SEEL linear threshold gates. Such an implementation can be derived from the SET electron box circuit.

The remainder of this chapter is organized as follows. Section 2.1 introduces the concept of threshold logic and its potential advantages for logic design. Section 2.2 presents the SET electron box circuit, consisting of one junction and one capacitor, which can be thought of as a one input threshold gate. Us-ing the electron box as a basis, Section 2.3 discusses a generic SEEL linear threshold gate scheme. Section 2.4 proposes a Boolean logic family consist-ing of 2-input AND, OR, NAND and NOR gates that were derived from the threshold gate. Each of these Boolean gates is verified by simulation and an-alyzed in terms of required area, gate delay and energy consumption. Section 2.5 concludes the chapter.

2.1 Threshold Logic

It is well known that any Boolean function can be computed using a network of AND, OR, NAND and NOR Boolean logic gates. Although these basic Boolean gates can be efficiently implemented in currently used technologies such as CMOS this does not necessarily hold true for a novel technology such as Single Electron Tunneling (SET). However, there are alternative logic de-sign styles, such as threshold gate based logic [45, 56], that may be more suitable for novel technologies such as SET.

x x x 1 2 n ω ω ω n 1 2 F(X)

Figure 2.1: n-input Linear Threshold Gate.

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2.1. THRESHOLDLOGIC 23

which is able to compute any linearly separable Boolean function given by:

F(X) = sgn{F(X)} = 0 if F(X) < 0 1 if F(X) ≥ 0 (2.1) F(X) = n i=1 ωixi− ψ (2.2)

where xi are the n Boolean inputs and wi are the corresponding n

inte-ger weights. The linear threshold gate performs a comparison between the weighted sum of the inputs Σn_i₌₁ωixi and the threshold value ψ. If the

weighted sum of inputs is greater than or equal to the threshold, the gate pro-duces a logic ’1’. Otherwise the output is a logic ’0’.

A single input linear threshold gate can achieve the computation of the n-input AND, OR, NAND and NOR functions as follows:

AN D(a₁, a₂, . . . , an) = sgn{a1+ a2+ . . . + an− n} (2.3)

OR(a₁, a₂, . . . , an) = sgn{a1+ a2+ . . . + an− 1} (2.4)

N AN D(a₁, a₂, . . . , an) = sgn{−a1− a2− . . . − an+ n − 1}(2.5)

N OR(a₁, a₂, . . . , an) = sgn{−a1− a2− . . . − an} (2.6)

The above can be easily verified. For example, consider the 2-input AND function, which can be computed as AN D(a₁, a₂) = sgn{a₁ + a₂ − 2}.

Given the definition of the sgn function, as stated by Equation (2.1), the sum of inputs will not be greater than or equal to the threshold ψ = 2, i.e., F (X) = 1, unless both inputs are ’1’. Therefore, a network of linear threshold gates can implement any Boolean function.

One of the main advantages of threshold logic is that a single threshold gate can implement Boolean functions that would require multiple traditional Boolean logic gates. This phenomenon can be exemplified by the computation of the function AND-OR(a, b, c) = a OR (b AND c). Assuming traditional Boolean logic gates, this expression can be computed in two gate levels at a cost of one 2-input AND gate and one 2-input OR gate. When assuming threshold logic, the computation can be achieved with a single 3-input threshold logic gate as follows:

AN D− OR(a, b, c) = sgn{2a + b + c − 2} (2.7) It can be verified that the above threshold logic equation implements the AND-OR(a, b, c) function by assuming different values for a, b and c and calculating

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the resulting output. It has been proved that threshold logic networks can cal-culate a wide range of Boolean functions, such as addition related operations, using significantly less logic gates and less depth then networks consisting of traditional Boolean logic gates [49, 8]. Moreover, CMOS based threshold gate designs that prove the feasibility of such threshold logic networks have been proposed [53, 6, 54].

An additional benefit of threshold logic is that threshold gates can utilize in-verted input signals and/or produce inin-verted output signals in a straightfor-ward manner at no additional costs in hardware. Assume for example that only the inverse of the desired input signal is available, i.e., a instead of a. Given that for threshold equations a = −a + 1, one can substitute a with

−a + 1 and utilize the inverted input a instead of a. For Equation (2.7)

this would result in AN D − OR(a, b, c) = sgn{−2a + b + c}. A sim-ilar substitution can be made if the desired input signal is a and only a is available. Likewise, the inverse of the entire threshold equation can be de-rived by inverting the sign of each weight, and by subtracting one from the threshold value and inverting the result. For Equation (2.7) this would result in

AN D− OR(a, b, c) = sgn{−2a − b − c + 1}.

When examining the switching behavior of a SET tunnel junction, the ele-mentary building block for SET circuits, we observe that switching, i.e., the transport of charge through the tunnel junction, is only possible if the voltage

Vj across this tunnel junction is larger than a given critical voltage Vc. This

critical voltage acts as a voltage threshold for charge transport. Therefore, the switching behavior of the SET tunnel junction appears to be similar to that of a threshold logic gate. As will be explained in details in Section 2.3, a single SET tunnel junction can form the basis of an efficient linear threshold logic gate implementation.

The next section introduces the SET electron box circuit. The electron box circuit, containing just one SET tunnel junction, can be thought of as a one input threshold gate and forms the basis for the generic SEEL threshold gate discussed later in this chapter.

2.2 Single Electron Box

One of the conceptually simplest SET circuits in which the charge transport of a single electron can be controlled is the electron box. The electron box consists of a tunnel junction in series with a capacitor, as displayed in Figure 2.2. The tunnel junction has a capacitance of Cj and the capacitor has a

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ca-2.2. SINGLE ELECTRON BOX 25

+

−

C + V − Vout island j c j + − C Vin

Figure 2.2: The electron box circuit.

pacitance of Cc. The node between the tunnel junction and the capacitor is

referred to as an “island”. An island is a circuit node that contains a net charge

qisland = jqe, such that j = 0 corresponds with the electrical equilibrium,

i.e., the island contains as many protons as it contains electrons. Electrons can only be added, or removed from, the island via tunnel events through the tunnel junction. Given that for this circuit the equivalent capacitor Ce = Cc,

Equation 1.12 implies that the critical voltage Vcof the tunnel junction in the

electron box circuit can be expressed as:

Vc=

qe

2(Cj + Cc)

(2.8) Given the sign convention displayed in Figure 2.2, the voltage Vj across the

tunnel junction is:

Vj = CcVin Cj+ Cc − jqe Cj+ Cc (2.9) In Equation (2.9), the first term is due to capacitive division of the input voltage

Vin over Cj and Cc. The second term is the voltage resulting from an extra

charge of jqeon the island, which has a total capacitance of Cj+ Cc.

The circuit is in a stable state if|Vj| < Vcis satisfied. Using Equations (2.8)

and (2.9), this results in the following relation:

−qe+ 2jqe 2Cc < Vin< qe+ 2jqe 2Cc (2.10) Therefore, for any value of Vin, the circuit will reach a stable state for a unique

value of j satisfying the above relation. If the circuit is initially in a stable state, then the circuit will remain in this stable state if the circuit’s input voltage

Vinis gradually increased or decreased. However, the voltage Vj will

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an electron will tunnel through the junction towards the side with the highest voltage. As a result of this tunnel event the voltage across the tunnel junction will be reduced below the junction’s critical voltage Vc, thereby blocking

fur-ther charge transport until a furfur-ther increase or decrease of Vinagain results in

|Vj| > Vc. If the input voltage Vin is continuously increased, the electrons

al-ways tunnel away from the island, resulting in sudden increases of the island’s charge. For a continuously decreasing input voltage Vin the opposite occurs.

The island charge qisland resulting from the input voltage Vin is displayed in

Figure 2.3. c −q 2C 2C 2C −q q Cc c c 3q q V in 0 island q e e 2q q e e e e e

Figure 2.3: Electron box - charge qislandresulting from voltage Vin.

The operating principle of the electron box can be used as a basis for imple-menting SEEL gates if, for example, the input voltage is restricted to 0 <

Vin < _Cqe_c. One can observe from Figure 2.3 that this limits the net charge on

the island to 0qeor 1qe. Additionally, it can be observed that Vin = _2Cqe_c = ψ

acts as a natural threshold for the circuit, such that qisland = 0qefor Vin < ψ

and qisland = 1qefor Vin > ψ (assuming 0 < Vin < _Cqe_c). This suggests that

the electron box can be utilized as a basis for implementing a generic SEEL threshold gate, as illustrated in the next section.

2.3 Generic Linear Threshold Gate

Using the electron box circuit as a basis, we propose the circuit depicted in Figure 2.4 as a generic SEEL linear threshold gate implementation [33]. The

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2.3. GENERICLINEARTHRESHOLDGATE 27 V b x C b y _{V o} C o C C V V 2 1 C V C C V V₁ 2 2 1 C V 1 2 p p p C j + − V_j p p p n n n n n n p n inputs V Inputs V r s r s q e

Figure 2.4: The n-input linear threshold gate.

tunnel junction Cj and the output capacitor Co form the two original circuit

elements of the electron box. The input signals Vp = {V₁p, V₂p, . . . , V_rp}

are weighted by their corresponding capacitors Cp = {C₁p, C₂p, . . . , C_rp}

and added to the voltage Vj across the tunnel junction. The input signals

Vn _{= {V}n

1 , V2n, . . . , Vsn} are weighted by their corresponding capacitors

Cn = {C₁n, C₂n, . . . , C_sn} and subtracted from the voltage across the tunnel

junction. The critical voltage Vc, needed to enable tunneling, acts as the

intrin-sic threshold of the circuit. The biasing voltage Vb, weighted by the capacitor

Cb, is used to adjust the gate threshold to the desired value ψ.

Considering all voltage sources in Figure 2.4 to be 0 Volt (or ground), the circuit can be viewed as consisting of three capacitors in series, i.e., C_Σp, Cj,

and C_Σn. This results in the following notations, which are used throughout this section:

C_Σp = Cb+ Σrk=1C p

k (2.11)

Single electron tunneling based arithmetic computation

Single Electron Tunneling

Based Arithmetic Computation

Single Electron Tunneling

Based Arithmetic Computation

Abstract

I

Acknowledgments

Contents

Chapter 1

Introduction

D

1.1

SET Background

1.2

Related Work and Open Questions

1.3

Thesis Framework

Chapter 2

SEEL Threshold Logic Gates

T

2.1

Threshold Logic

2.2

Single Electron Box

+

−

2.3

Generic Linear Threshold Gate