Novel Batch Titanium Nitride CVD Process for Advanced Metal Electrodes

Novel Batch Titanium Nitride

CVD Process for

Advanced Metal Electrodes

Peter Zagwijn, Wilco Verweij,

Dieter Pierreux, Noureddine Adjeroud,

Radko Bankras, Ed Oosterlaken,

Gert Jan Snijders,Michiel van den Hout

,

Pamela Fischer, Rudi Wilhelm,

and Martin Knapp

ASM International N.V.

Bilthoven, The Netherlands.

Memory devices for the generations beyond 65 nm will be based on Metal Insulator Metal (MIM) capacitor cell structures. The most promising candidate for both metal electrodes (top and bottom) is Titanium Nitride (TiN) as shown for instance by the ITRS roadmap for Front End Processes. Furthermore next generation MIM capacitors for Embedded Memory devices target TiN as Electrode material. Also in Gatestack development for advanced CMOS (beyond 45 nm technology node) TiN is widely used as mid-gap metal gate electrode. Currently TiN is already applied in top electrodes, sometimes in combination with poly silicon electrode material. Historically most metal nitrides are deposited by single wafer low pressure deposition tools. This article describes a novel CVD process for TiN films developed in a 300 mm Vertical Furnace. We have solved Chlorine incorporation at low temperature inside the TiN layer while at the same time the batch process yields a 3 times higher throughput per dual reactor system compared to a single wafer system with 3 chambers.

We show process results for load sizes ranging from 5 to as much as 100 wafers that prove filler wafers are only required to a minimum.

This versatility in load size is illustrated in Figure 1 where the deposited thicknesses for 3 different Product wafer load size processes with one and the same recipe are given. Per Product wafer a constant decrease of 0.7 Å in thickness is measured. For the 3 different load sizes only 3 Filler wafers were used. For films with a thickness of 20 nm the dual reactor system produces as much as 100 wafers per hour.

Stochiometric TiN films are generated with thickness uniformities of 1% range (see Figure 2). The results of Auger analysis on film composition are given in Table 1. The Chlorine contamination is well below 1 at.%. Thin film resistivity value measures as low as 150 µΩcm and very good conformality on high aspect ratio DRAM device structures has been demonstrated. Step coverage ratios in the range of 85 to 95% are measured for an aspect ratio that exceeds 1: 40. The A412 system has a novel actively heated lower chamber design to keep particle generation due to byproducts of the deposition process to a minimum. This results in typically less than 50 added particles larger in size than 0.12 µm for the TiN CVD process. Furthermore an effective dry quartz in situ cleaning process that is executed after 2000 production wafers have been processed reduces the amount of wet quartz cleaning to a minimum.

Figure 1. Flexible Loadsize performance of the pulsed CVD TiN process for 5, 10 and 25 Product wafers in the furnace. Per product wafer added a constant decrease of 0.7 Å in TiN thickness is observed. Each run contains only 3 dummy wafers plus the product wafers as indicated.

Figure 2. Thickness trend for 40 consecutive runs. A run to run uniformity of less than 1% (range +/-) is obtained.

Table 1. Summary Auger Electron Spectroscopy composition analysis of TiN layers deposited in the Top and Bottom of the vertical batch furnace. The column on the right contains reference data of a Single wafer deposition system.

1) Currently at the Delft University of Technology, The Netherlands. 1.00 1.00 1.01 N:Ti 3 0.7 0.7 Cl (%) 2 1.3 1.6 O (%) 47.5 49 49 N (%) 47.5 49 48.7 Ti (%) Reference

*

*

Av. Thickness (compensated)

100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 140.00 730 740 750 760 770 780 Run nr. T hi ckn es s [ A ]

Av. Thickness (compensated)

100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 140.00 730 740 750 760 770 780 Run nr. T hi ckn es s [ A ]