74LCX02

March 1995 Revised June 1999

7 4LCX02 Low V o lt age Quad 2-I nput NOR Gat e wi th 5V T o le rant I nput s

74LCX02

Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs

General Description

The LCX02 contains four 2-input NOR gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys- tems to 3V systems.

The 74LCX02 is fabricated with advanced CMOS technol- ogy to achieve high speed operation while maintaining CMOS low power dissipation.

Features

■5V tolerant inputs

■2.3V–3.6V V_CC specification provided

■5.2 ns t_PD max (V_CC = 3.3V), 10 µA ICC max

■Power down high impedance inputs and outputs

■±24 mA output drive (V_CC = 3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up performance exceeds 500 mA

■ESD performance:

Human body model > 2000V Machine model > 200V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74LCX02M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 74LCX02SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX02MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

A_n, B_n Inputs

O_n Outputs

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74L C X Absolute Maximum Ratings

Recommended Operating Conditions

Note 1: The Absolute Maximum Ratings are those beyond which the safety of the device cannot be guaranteed. The device should not be operating at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: I_O Absolute Maximum Rating must be observed.

Note 3: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

V_CC Supply Voltage −0.5 to +7.0 V

V_I DC Input Voltage −0.5 to +7.0 V

V_O DC Output Voltage −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 2) V

I_IK DC Input Diode Current −50 V_I < GND mA

I_OK DC Output Diode Current −50 V_O < GND

+50 V_O > V_CC mA

I_O DC Output Source/Sink Current ±50 mA

I_CC DC Supply Current per Supply Pin ±100 mA

I_GND DC Ground Current per Ground Pin ±100 mA

T_STG Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

V_CC Supply Voltage Operating 2.0 3.6

Data Retention 1.5 3.6 V

V_I Input Voltage 0 5.5 V

V_O Output Voltage HIGH or LOW State 0 V_CC V

I_OH/I_OL Output Current V_CC = 3.0V − 3.6V ±24

mA V_CC = 2.7V − 3.0V ±12

V_CC = 2.3V − 2.7V ±8

T_A Free-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate, V_IN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions V_CC T_A = −40°C to +85°C

Units

(V) Min Max

V_IH HIGH Level Input Voltage 2.3 − 2.7 1.7

2.7 − 3.6 2.0 V

V_IL LOW Level Input Voltage 2.3 − 2.7 0.7

2.7 − 3.6 0.8 V

V_OH HIGH Level Output Voltage I_OH = −100µA 2.3 − 3.6 V_CC - 0.2

V

I_OH = -8 mA 2.3 1.8

I_OH=−12 mA 2.7 2.2

I_OH = −18 mA 3.0 2.4

I_OH=−24 mA 3.0 2.2

V_OL LOW Level Output Voltage I_OL= 100µA 2.3 − 3.6 0.2

I_OL = 8mA 2.3 0.6

I_OL= 12 mA 2.7 0.4 V

I_OL= 16 mA 3.0 0.4

I_OL = 24 mA 3.0 0.55

I_I Input Leakage Current 0 ≤ V_I≤ 5.5V 2.3 − 3.6 ±5.0 µA

I_OFF Power-Off Leakage Current V_I or V_O= 5.5V 0 10 µA

I_CC Quiescent Supply Current V_I = V_CC or GND 2.3 − 3.6 10

3.6V ≤ V_I≤ 5.5V 2.3 − 3.6 ±10 µA

∆I_CC Increase in I_CC per Input V_IH= V_CC−0.6V 2.3 − 3.6 500 µA

7 4LCX02 AC Electrical Characteristics

Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH).

Dynamic Switching Characteristics

Capacitance

Symbol Parameter

T_A = −40°C to +85°C, RL = 500 Ω

Units V_CC = 3.3V ± 0.3V, V_CC = 2.7V V_CC = 2.5V ± 0.2V

C_L= 50 pF C_L = 50 pF C_L = 30 pF

Min Max Min Max Min Max

t_PHL Propagation Delay Time 1.5 5.2 1.5 6.0 1.5 6.2

t_PLH 1.5 5.2 1.5 6.0 1.5 6.2 ns

t_OSHL Output to Output Skew 1.0

ns

t_OSLH (Note 4) 1.0

Symbol Parameter Conditions V_CC

(V)

T_A = 25°C Units Typical V_OLP Quiet Output Dynamic Peak V_OL C_L= 50 pF, V_IH= 3.3V, V_IL= 0V 3.3 0.8

C_L= 30 pF, V_IH= 2.5V, V_IL= 0V 2.5 0.6 V V_OLV Quiet Output Dynamic Valley V_OL C_L= 50 pF, V_IH= 3.3V, V_IL= 0V 3.3 −0.8

C_L= 30 pF, V_IH= 2.5V, V_IL= 0V 2.5 −0.6 V

Symbol Parameter Conditions Typical Units

C_IN Input Capacitance V_CC= Open, V_I= 0V or V_CC 7 pF

C_OUT Output Capacitance V_CC = 3.3V, V_I = 0V or V_CC 8 pF

C_PD Power Dissipation Capacitance V_CC= 3.3V, V_I= 0V or V_CC, f = 10 MHz 25 pF

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74L C X AC Loading and Waveforms

FIGURE 1. AC Test Circuit (C_L includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay, Pulse Width and t_rec Waveforms

3-STATE Output High Enable and Disable TImes for Logic

3-STATE Output Low Enable and Disable Times for Logic

Setup Time, Hold TIme and Recovery TIme for Logic

t_rise and t_fall FIGURE 2. Waveforms

(Input Pulse Characteristics; f=1MHz, t_r=t_f=3ns)

Test Switch

t_PLH, t_PHL Open

t_PZL, t_PLZ 6V at V_CC = 3.3 ± 0.3V V_CC x 2 at V_CC = 2.5 ± 0.2V t_PZH,t_PHZ GND

Symbol V_CC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

V_mi 1.5V 1.5V V_CC/2

V_mo 1.5V 1.5V V_CC/2

V_x V_OL + 0.3V V_OL + 0.3V V_OL + 0.15V V_y V_OH − 0.3V V_OH − 0.3V V_OH − 0.15V

7 4LCX02

Schematic Diagram

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74L C X Physical Dimensions

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

7 4LCX02 Low V o lt age Quad 2-I nput NOR Gat e wi th 5V T o le rant I nput s

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the

2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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Physical Dimensions

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14