Single-Electron and Molecular Devices

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Single-Electron and

Molecular Devices

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Single-Electron and

Molecular Devices

Proefschrift

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof.dr.ir. J.T. Fokkema, voorzitter van het College voor Promoties,

in het openbaar te verdedigen op maandag 24 november 2003 om 10.30 uur door

Günther LIENTSCHNIG

Diplom-Ingenieur, Technische Universität Wien geboren te Wenen, Oostenrijk.

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Toegevoegd promotor: Dr. P. Hadley

Samenstelling van de promotiecommissie:

Rector Magnificus, voorzitter

Prof.dr.ir. J. E. Mooij, Technische Universiteit Delft, promotor

Dr. P. Hadley, Technische Universiteit Delft, toegevoegd promotor Prof.dr. C. Dekker, Technische Universiteit Delft

Prof.dr. J. M. van Ruitenbeek, Universiteit Leiden

Prof.dr.ir. T. M. Klapwijk, Technische Universiteit Delft

Univ.Prof.Dr.phil. H. Kurz, Rheinisch-Westfälische Technische Hochschule Prof.dr.ir. A. H. M. van Roermund, Technische Universiteit Eindhoven

Cover design: Looh’s PIG, Austria

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Printed by: Febodruk b.v., The Netherlands

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ISBN 90-9017-550-4

Keywords: single-electron tunneling networks, hybrid SET-FET simulations, charge traps, aluminum oxide, self-assembled monolayers, conduction through oligomers and organic molecules

Copyright c 2003 by Günther Lientschnig

All rights reserved. No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, in-cluding photocopying, recording or by any information storage and retrieval system, without permission from the author.

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Acknowledgement

The scientist does not study nature because it is useful, he studies it because he delights in it, and he delights in it because it is beautiful. If nature were not beautiful, it would not be worth knowing, and if nature were not worth knowing, life would not be worth living.

JULES-HENRIPOINCARÉ

Scientific research is not something one can do alone; it is very much a group effort with many people involved. On a bigger scale, it is the society at large setting the prerequisites and deciding to what extent it fosters the increase of knowledge. In the Netherlands, substantial investments are made into applied and fundamental science. As direct and indirect consequence, the Netherlands hosts a range of high-tech companies and many groups and scientists con-tributing to the forefront of research and technology.

The Delft University of Technology is home to a particularly interesting group. When I first visited QT, the Quantum Transport Group headed by Hans Mooij, I was impressed by its size, by the wide range of projects, and by its international character. Humming with activity, there is a constant influx of new people joining, while people leaving from here seize the world and ac-quire postdoctoral, permanent, or other top positions. Visitors come on an almost daily basis and there are close co-operations both with many people from far away as well as with all the other groups in the immediate vicinity. In the four-and-a-half years that I have had the pleasure of being part of the group, QT has split in two, with two of its own staff being appointed profes-sors; both QT and MB, the Molecular Biophysics Group, have quickly grown to become even bigger than QT was before; the NanoScience department has been formed together with MB, NF, EM, Electron Microscopy and, of course, with the theorists from above; the Leiden–Delft connection has been intensi-fied, and as if DIMES’s 2000 m2 _{of cleanroom were not enough, the next one}

is about to be built. I only can join in with all the laudations in other prefaces written in this institute: Hans, you and your co-architects have created a truly

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unique research environment indeed! I am very glad that I could have been here.

I definitely enjoyed the group culture, which seems to be representative of Dutch university life in general, — being on first-name terms with everybody, a very flat hierarchy, open doors everywhere, money? – no problem! And everything is so easy. . . , pragmatic. If there actually is some bureaucracy, then it has been well shielded from me!

Hans, jij bent mijn officeële promotor, maar mijn echte begeleider was natu-urlijk Peter Hadley. Peter, you’ve been an extremely nice supervisor, indeed. Your door was always open and I cannot remember a single time that you did not have time instantaneously when I walked in. Thank you very much for all your guidance and help! I especially liked your repeatedly unconventional thinking and your pinpointing of hidden and glossed-over, physical mysteries; some of them I am still pondering about. . .

QT is so big that I hardly noticed these nanotube guys in the beginning. Strangely, only some time after the MB people had split from QT and had taken refuge at the far end of the hallway did I get in closer contact with them. The reason for this has a name, viz. Jeong-O Lee. Jeong-O, without ques-tion you are the person I worked most closely with. I very much enjoyed the time we spent together measuring and interpreting, sometimes until early in the morning; often without much success; and then again, we were amply re-warded: It’s moving with the gate! I learnt a lot from you, especially when I asked you stupid questions. However, it was not only physics. — You were a focal point of social activity. I think of your Korean cooking parties, the concert expeditions, and the going-out-for-dinners with the others; the very special MB ice-cream cauldrons, the Hoge Veluwe, and of course the secret seminar-room-to-cinema-transformations making use of state-of-the-art pre-sentation equipment. I wish you much success with your further career back home!

When we started the QT-MB molecule collaboration, I got into closer con-tact with Cees Dekker. Cees, I esteem your way of working, very quick and effective. Certainly, you have very strong opinions. Occasionally, I have, too; so there is room for discussion. I am looking forward to work with you the next five months.

Thanks to the other members of the core molecular-electronics team, Mu-rat Durkut, Marta Mas-Torrent (¡Gracias por nuestras conversaciones en Es-pañol! — ¡Pero todavía tenemos que hablar más de moléculas!), and Duncan den Boer. Of course there is also Hubert Heersche, who always succeeds in

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vii breaking his junctions as soon as he has produced them; and his comrade Jorden van Dam: bedankt voor al onze discussies, maar vooral moeten jullie mij nog uitleggen, waar Groningen nu eigenlijk precies ligt, en of ze daar ook zo een slechtexxxxxxxxxxxx

XXXXXXXXXX koffie drinken. Herre van der Zant and Yann Kervennic love molecules, too. Strangely, they claim that their’s is the best method for mea-suring them. Keith Williams also joins our Tuesday discussion, putting his vast chemistry knowledge at our disposal. Keith, I never was quick enough to measure your email-response time, but fortunately, I soon will be even quicker in positively responding to your concert and other invitations!

Of course, we all know that chemistry can be reduced to solving the Schrö-dinger equation; but still, chemists are no way superfluous. Frank (halber Tiroler) Wiertz: Frankie, because of you, the letters CV got a whole different meaning for me. Dirk Heering: Dirk, I think, electrochemists definitely think differently. Andrew Grimsdale and Prashant Sonar, Luke Oldridge and Ashok Mishra: The molecules you fabricate are definitely much too complex for a Schrödinger approach. Rather we have to measure them! And then, there are René Janssen, and Martin Struijk, Richard Egberingk, and David Reinhoudt. The molecules you have sent are much smaller; but still, the theorists have their difficulty with them! Ahh yes, the theorists. . . I would like to thank Yuli Nazarov, Milena Grifoni, Jos Thijssen, and Ferdinand Evers for all the discussions we had!

Furthermore, there are Silvano De Franceschi and all the other people from the Leo Kouwenhoven group who do not want to trap real molecules. Rather, they build artificial ones, but alas! they are just two-dimensional! Leo, thanks for the many cakes you bring, each time that you have received new money again; and Silvano, thanks! In you, I always have found an interested discus-sion partner.

Thanks for all the technical help I received from Richart Stegink and Eti-enne Swinkels (ookal zijn jullie straks weer ervandoor gegaan!), from Bram (bijna altijd blij fluitend en origineel) van der Enden, from Mascha van Oos-sanen, die zelfs om vijf voor vijf nog begint mijn samples te bonden; from meester-elektronicus en ruis-annihilator Raymond Schouten; from Leo Lan-der, Wim Schot, and Willem den Braver; from Dick Korbee; and from all the DIMES staff, Emile van der Drift, Bert de Groot, Bernard Rousseau, Anja Suur-ling, Marc Zuiddam, and Arjan van Zuuk.

I worked together with Diederik Rep (jammer, dat onze Shottky-Barrier SET’s geen success waren!), Ming-Jiunn (Yes! I excuse!) Lai, and Irek Weyman. Thanks to all of you!

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Arthur van Roermund initiated the whole DIOC project that my work was financed from. Thanks for all the discussions we had in our DIOC meetings to Sorin Cotofana (I liked your special email), Rudie (who reads old books with yellow pages) van de Haar, Jaap Hoekstra, Pieter Jonker, Roelof (almost part of DIOC as well) Klunder, Casper Lageweg, Andriy Levytskyy, Sven Rogge, Eelco Rouw, Gert-Jan Smit, Pattrick de Wilde, Jie Han, and Chris Verhoeven.

My office mates were Yann Kervennic, Ton Wallast, Michel Hendriks, Pablo Jarillo-Herrero, and our newest addition, Franck Ballestro. Ton, bedankt voor het wijzen van de juiste richting midden in de jungle van het nederlandse recht. Pablo, ¡gracias por todas nuestras tan fructíferas conversaciónes so-bre física! pero no deberías tomarme tanto en serio. Empar, hemos hablado muchísima por teléfono, casi cada día, pero nunca he descubierto tu secreto. Eres la única persona con quien Pablo siempre habla en voz baja, muy dul-cemente. Franck, oui, allons-nous à Paris!

There are many other people I would like to thank: The Linux masters Laurens Willems van Beveren, Jelle Plantenberg, and Hannes Majer; NT-guru Michael Janus, and my network administrator comrade Eugen Onac; the man-agement staff Ria van Heren, Yuli French-Nakagawa and Bart van Leijen; my mesoscopic physics and quantum computation teachers not yet mentioned, Carlo Beenakker and Lieven Vandersypen; and many other people in- and out-side QT, notably: Adrian Bachtold, Patrice Bertet, David Dixon, Jeroen Elzer-man, Alexander ter Haar, Kees Harmans, Jing Kong (who rather drives with me to DIMES instead of joining the others for dinner), Serge Lemay, Adrian Lupascu, Alberto Morpurgo, Yasu Nakamura, Floor Paauw, Erwin Slot, Sami Sapmaz, Arnold Storm (yes, I like your VI better than mine!), Christoph Wass-huber, Frank Wilhelm, Zhen Yao, and Floris Zwanenburg. There are many more, please forgive me, if I have forgotten to mention you here. . .

Come to that, the last stage of writing a thesis is a very hectic period. I should have known this, since it is stated in the prefaces of many other theses I have read. I would like to thank several people that have helped me in this period, especially Kees Harmans and Jort Wever for the time they invested for the Dutch translation of the summary; Keith Williams, Ronald Hanson, and Jelle Plantenberg for getting the formulation of my stellingen right; Mar-tin (oide Hitt’n) Luh for his master-piece of graphical design (do host ma a uandliche freid gmocht!); Peter Hendriks and Peter van Limbeek from Febo-druk for their prompt, excellent, and reliable service; and Elfriede Nordlohne, Kotska Wallace, Jeong-O Lee, Diederik Rep, and of course, Peter Hadley for proof-reading.

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ix There are also my climbing, travelling, dancing and other friends outside Delft who have made my stay in the Netherlands a very pleasant one. Thanks to all of you! Especially, to all the inmates that I have lived together with dur-ing this time: My family of choice, Norbert (großer Bruder) Frischauf; Tina und Karina natürlich, die eine große Leere im Haus hinterließen, als sie Holland wieder verließen; and our other part-time visitors, Rodolfo Condessa, Ger-hard Kminek, Timm Riesen, Kotska Wallace, and Albert (McWasi) Washüttl. Herzlichen Dank an meine Eltern, die mich immer unterstützten, an meine treueste Besucherin, Schwesterherz Silvia, und an meine Tanten, Verwandten und all meine Freunde in Österreich, vor allem an die, die sich schon lange vordem dieses Büchlein fertig wurde, angekündigt haben: Poldi und Walter, Hermi, Christina und Johanna, und Martin und Brigitte.

Last but surely not least, very special thanks to my two paranimfen, mijn (halve) marathonmaatje, Silvia Trautner, en mijn persoonlijke Nederlands-le-rares en Duits-enthousiaste Elfriede Nordlohne. Heel erg bedankt voor alles!

Finally, I thank Frank Danesy, Norbert Gurker, Helmut Leeb, and Frank-Martin Seifert for their advice when taking the decision between doing a Ph.D. or taking a job in industry. Going to TU Delft was certainly the right choice!

Günther Lientschnig Delft, October 2003

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Chapter 1 Introduction: From Metallic

Single-Electron Transistors to

Molecular Devices

Prediction is difficult, especially the future. NIELSBOHR

The advent of large-scale integration of electronic circuits in the early 1970’s enabled the development of both microprocessors and semiconductor mem-ory, thus initiating the third, and later the fourth generation of digital comput-ers. Since then, new technology generations have been introduced every three years, each of them decreasing the transistors’ lateral dimensions by thirty per-cent. The minimum feature size was 6 µm in 1971, it is now 90 nm, and it is projected to be just 35 nm in 2012. However, there is no doubt that funda-mental physical constraints will eventually limit this process of further minia-turization, even though the predictions for this final limit have continuously been adjusted towards smaller sizes. Nonetheless, devices with dimensions approaching the wavelength of free electrons cannot be described anymore by purely semi-classical theory. Rather, quantum mechanical effects like tunnel-ing, Coulomb blockade, and wave interference have to be taken into account.

These quantum effects are generally viewed as unwanted obstacles by semi-conductor industry. Yet, it might just as well be possible to take advantage of them, or to deal with deviations from the ideal transistor behavior on a higher level, thus performing computation in a different and unconventional way. Ex-actly these issues have been investigated at the Delft University of Technology during the last four-and-a-half years, within an interdisciplinary project enti-tled NANOCOMP– Novel Computational Structures based on Quantum Devices.

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It is characteristic of the development of integrated semiconductor circuits that it has been taken place in several clearly separated disciplines in parallel: from the technology and device level over the circuit and signal-processing levels up to the algorithm, system and architecture levels. Likewise, NANO -COMP has been divided into several subprojects to tackle the issues from dif-ferent aspects and viewpoints.

This thesis forms part of NANOCOMP and is concerned with the quantum device level. It is not concerned with quantum computing, which is dealt with in another of the NANOCOMP sub-projects. There, devices are not really sep-arated from each other but form a truly quantum-mechanically time-coherent integral whole that asks for a logic completely different to conventional binary logic. In this work however, the focus lies on novel devices that show non-semiclassical behavior due to their small size, but that might be connected together in a classical way to form new computational structures according to more traditional schemes based on Boolean logic or alternative, but essentially equivalent logic such as threshold logic, neural networks, or fault-tolerant ar-rays.

Initially, the work concentrated on metallic single-electron tunneling tran-sistors (SET’s). These devices had attracted a lot of interest because they do not have a monotonously rising transfer function like conventional transistors. In-stead, their signal output is a periodic or quasi-periodic function of the signal input, which represents a new, unconventional, and possibly exploitable prop-erty for designing circuits.

However, single-electron transistors will only work at room temperature, if they are made extremely small. Even with e-beam lithography, it was not pos-sible to reliably decrease the structure size down to the required, nanometer-sized dimensions. We thus combined lithographic (top–down) fabrication meth-ods with a bottom–up approach, where parts of the devices are fabricated by chemical synthesis and then incorporated into circuits by self-assembly. In-stead of metal components, molecules were thus used. The obtained molec-ular devices did not only exhibit single-electron effects, they also exhibited a rich variety of other phenomena that normal metal SET’s do not.

In this chapter, CMOS transistors and its possible rival candidates are first discussed in general. Then, single-electron transistors are dealt with in more detail. Specifically, their advantages and disadvantages are reviewed, and their usability as elements for logic circuits is evaluated. Especially when single-electron tunneling takes place through small molecules, it is important to have good coupling to the gate electrode. This issue is touched upon next.

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1.1 Conservative Mentality, or Obvious Smartness? 3 Finally, an overview of the measurements on molecular devices is given. In the course of this introduction, all the other chapters of this thesis are introduced.

1.1 Conservative Mentality, or Obvious Smartness?

For more than 25 years, complementary metal-oxide-semiconductor (CMOS) technology has been dominating semiconductor and computer industry. The expected end of the roadmap has continuously been shifted towards more in-tegration. Many problems have been solved:

In the late 1970’s, the complexity of the chip-design was seen as a potential showstopper, but with computer-aided design, this obstacle has easily been overcome. In the late 1980’s, power-consumption was the big concern, but voltage scaling and power-management continuously put off this problem. To-day it is the availability of commercially feasible lithographic manufacturing methods that cast doubts, but with new techniques, optical lithography down into the 50 nm region now seems possible, and other mass-production raphy methods like extreme ultraviolet lithography, X-rays proximity lithog-raphy, and e-beam and ion-beam projection lithography look promising. Ac-cording to the semiconductor roadmap, the miniaturization will continue for at least the next 15 years.

Transistors with a source–drain length of 15 nm have already been demon-strated [1], and even a transistor with a source–drain length less than 10 nm has been reported that still exhibited gain [2]. However, the source–drain sep-aration has to be considerably bigger than the gate-oxide thickness in order that gain occur. The ultimate limit for the source–drain distance turns out to be ∼3 nm; in practice, the limit will be more like 7-10 nm [3].

Despite being one of the main drivers of the High–Tech sector, semiconduc-tor industry has the reputation of being very conservative in their planning and decision making process. Investment into innovative new concepts fre-quently is claimed to be low, and those who promote novel quantum devices often argue that if there would be as much invested in novel quantum devices as there is for the further development of CMOS, something better than CMOS could be developed.

Many devices and techniques have been proposed as possible future tech-nologies that may supplant CMOS field-effect transistors (FET’s) as the dom-inant device technology. These include rapid single-flux quantum devices, DNA computing, spin devices, resonant tunneling diodes (RTD’s), carbon nan-otube FET’s, single-electron transistors (SET’s), and molecular electronic

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de-vices. However, while some proposals possess advantages in certain aspects, none exhibits the full range of capabilities and versatility to replace CMOS logic.

Rapid single-flux quantum circuits for example are extremely fast and can operate at frequencies of ∼THz, but they require liquid helium temperature and a tight process tolerance. DNA computing is only practicable for specific problems and general purpose computing is not possible. Spin devices offer possibilities for magnetic RAM, but they are not suitable for logic operations. Carbon nanotube transistors are possibly the most promising in the list, even though their placement and integration in circuits might prove challenging. They outperform conventional semiconductors in terms of speed and not sur-prisingly, they are being actively investigated by IBM Research [4].

The RTD is a two-terminal device that shows negative differential resis-tance. In principle, it is possible to devise schemes to perform logic oper-ations with such circuit elements because bistability can be generated with them. However, even though Esaki tunnel diodes are known since 1962 and extensive development programs have been carried out to produce logic cir-cuits, these efforts have failed. This is due to a fundamental reason [5]. Disad-vantageous properties inherently present in bi-stable device logic in general, prohibit large-scale integration: the requirement of a separate reset operation, not much room for fan-out, and no standardized output signals; this last is-sue being the biggest drawback. This does not mean that resonant tunneling devices are not useful. In contrary, in conjunction with field effect transistors, memories can be made that can far outperform SRAM [6].

It is not a coincidence that the only three devices having been success-fully used as basic elements in commercial computing machines are all three-terminal devices: the relay, the vacuum tube, and the transistor. Furthermore, they are all highly non-linear, they have standardized binary output signals, and they have voltage and current gain providing high fan-out. It seems that these properties are necessary for being able to integrate Boolean logic ele-ments on a large-scale. In the next section a special class of three-terminal devices with very different behavior compared to FET’s will be discussed.

1.2 The ultimate reduction of current

A single-electron transistor consists of a small, conducting island that is only weakly connected to a source and to a drain electrode. More precisely, the resistance between the island and each of the electrodes must be considerably

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1.2 The ultimate reduction of current 5 larger than the quantum resistance. In this case, the charge on the island or the number of electrons on the island respectively, is well defined. A current flow through the island can therefore only be mediated by successive addition and removal of single electrons to and from the island. A single electron would for example tunnel from source to island, and subsequently from island to drain; hence the name single-electron transistor. Higher order tunnel events are also possible, but shall be neglected here. Now, if the island is very small, so is its total capacitance CΣ; the charging energy for one or minus one electron charge

on the island, i.e. the energy required to add or remove an electron will thus be very high, Ec = e2/(2CΣ). This implies that the island will resist being charged

or discharged, even if finite bias-voltage differences, ∆V = V1 − V2, between

source and drain are applied. Two tunnel resistances, R1and R2, in series thus

result in infinite differential resistance as long as |∆V | < e/(CΣ), and no current

will flow through the SET. This phenomenon is known as Coulomb blockade. The situation changes, if a gate electrode is added that capacitively cou-ples to the island. If a gate voltage Vg is applied such that half an electron

charge is polarized on the capacitor between gate and island, then effectively, minus half an electron charge is left on the island and will be distributed on the junction capacitances, C1 and C2, between source and island, and island

and drain, respectively. Now, if an electron charge is moved from one of the electrodes to the island and the charge state is thus moved from 0 to 1, then the effective charge changes from −1

2eto + 1

2e; but since the charging energy is

a quadratic function of the charge, the charging energy thus does not change. Hence the Coulomb blockade is lifted, and a current can flow through the SET, I ≈ ∆V /(R1 + R2).

It is easy to see that if a charge of ne, witn n being an integer, is polarized on the gate capacitor, then the SET transistor is off, i.e. the SET is in Coulomb blockade; and if a charge of (n + 1/2)e, is polarized on the gate capacitor, the SET is on, i.e. the Coulomb blockade is lifted. Unlike for FET’s, the transfer function of SET’s is thus periodic with the gate voltage. Figure1.1 shows the differential conductance of a SET as a function of its bias voltage V1 − V2 and

the gate voltage Vg− V2. If the SET were symmetrically biased, the stability

di-agram would be symmetric, but because the drain voltage V2acts as a ground,

the Coulomb diamonds are tilted.

The positive slope of the Coulomb diamond can be calculated to be Cg/(CΣ−

C1), and the negative slope is, −Cg/C1. These values correspond to the

maxi-mum voltage gain. The current in the n,n + 1 diamond can be written as [7],

I = ab

CΣ(R2a + R1b))

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Figure 1.1:The differential conductance of a SET is plotted as function of the bias and the gate voltage. The parameters of the SET are, C1 = C2 = Cg = 1aF, R1 = 100kΩ,

and R2 = 300kΩ. The black diamonds labeled -1, 0, and 1 are the Coulomb blockade

regions where no current flows through the SET. The charge on the island is −e, 0, and +e, respectively. The other diamonds with more numbers are unstable regions where current is flowing. Thus the charge state of the island switches between 0 and e in the region labeled; 0, 1.

a = +CΣV1+ ne − Q0− C1V1− C2V2− CgVg+ e/2, and,

b = −CΣV2+ ne + Q0+ C1V1+ C2V2+ CgVg − e/2.

Here, Q0 is the offset charge that will be discussed further below. From this

equation, the maximum transconductance near the boundary between the di-amonds labeled n and n, n + 1 can be determined, dI/dVg = Cg/(R2CΣ); and

the maximum transconductance near the boundary between the diamonds la-beled n, n + 1 and n is, dI/dVg = −Cg/(R1CΣ).

The striking, unconventional I-V characteristics of SET’s raise the question whether they can be exploited in novel logic schemes. Two broad classes of such proposals have been put forward. The first one is basically based on the idea to switch a SET between Coulomb-blockade and instable regions where current does flow [8, 9]. It is somehow analogous to CMOS logic and we refer to it as voltage-state logic. We now argue that voltage-state SET logic is not competitive with CMOS logic.

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1.2 The ultimate reduction of current 7

Figure 1.2: (a) The voltage gain is plotted as a function of the gate capacitance and temperature for a junction capacitance of 0.1 aF. The voltage gain depends on the bias current. The bias current was adjusted to achieve maximum gain. The bias currents that were used were I = 1 nA at 4.2 K, I = 20 nA at 50 K, I = 50 nA at 100 K, I = 100 nA at 200 K, I = 200 nA at 300 K, I = 200 nA at 400 K, and I = 300 nA at 500 K. (b) The maximum voltage gain possible for a given junction capacitance is plotted as a function of temperature. The currents which resulted in the maximum gain are given in the plot.

made smaller. This is because voltage gain, Cg/(CΣ− C1), decreases with

de-creasing gate capacitance. It is difficult to achieve a large gate capacitance when the island of a SET consists of a very small island or a single molecule. As the gate capacitance is increased for fixed junction capacitance and fixed temperature, the voltage gain first increases until the charging energy is on the order of kBT, and then it decreases sharply. This is illustrated in Fig. 1.2 (a)

where the voltage gain is plotted as a function of gate capacitance for different temperatures. In all of the curves the junction capacitance is assumed to be 0.1 aF. This is a lower limit on the smallest junction capacitances that can be achieved [7].

Thus for every junction capacitance and temperature, there is a maximum voltage gain. Figure1.2 (b) is a plot of the maximum gain. To determine the maximum gain, both the gate capacitance and the bias current of the SET were varied. The graph shows that it will be very difficult to make SET’s with volt-age gain greater than one that operate at room temperature. It will be even harder to get them to operate in a dense integrated circuit, which usually has a temperature of about 400 K. For room temperature voltage gain, the junction capacitance will have to be about 0.1 aF with a gate capacitance of 0.3 aF. This

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kind of SET has not yet been fabricated, but might be on the edge of being just feasible.

However, even if room temperature operation of voltage-state SET logic once will be possible, it will not be fast [7, 10]. The speed will be limited by the RC-delay formed by the resistance of the SET and the capacitance at the output of the SET. This capacitance depends on the parasitic capacitance of the wire at the output of the SET and the input capacitance of any devices connected to the SET. The parasitic capacitance of a wire is approximately 100 aF/µm. The large output impedance of a SET of at least 100 kΩ makes it an intrinsically slow device which will not match the speed of CMOS circuits.

However, SET’s exhibit extremely high charge sensitivity, which makes them very interesting for charge sensing and memory applications. This ad-vantage can be fully exploited, if SET’s are integrated with field-effect transis-tors in hybrid circuits. The FET’s can then buffer the high output impedance of the SET’s. In chapter 2 a simulation tool is presented that can analyze such hybrid SET-FET circuits and a few simple hybrid circuits are discussed.

In the other class of proposals for logic schemes, many islands are inter-connected via tunnel junctions and capacitors. Instead of switching between stable and unstable as is done in voltage-state logic, charge-state logic takes ad-vantage of bistable or multi-stable configurations and switches between dif-ferent charge states. These multi-stable states can be very complex, even for relatively small circuits. In chapter 3, a method is devised to analytically ana-lyze stability diagrams.

Many different charge-state logic designs have been proposed, among them systolic single-electron digital circuits [11], quantum-dot cellular automata [12], and the single-electron parametron [13]. Because single electrons basically represent one bit and jump individually from one island to another, this corresponds to absolutely minimal charge transfer. Hence, power consumption is extremely small. It is known that if classical computation is made reversible (this always can be done without introducing much higher circuit complexity), computa-tion can be performed with arbitrarily low energy dissipacomputa-tion [14]. Biological systems largely operate in such a regime [15]. The single-electron parametron also operates adiabatically and thus consumes much less energy per operation than kBT. In contrast, present day CMOS transistors consume ∼500 kBT of

energy. Charge state logic thus offers great perspectives in this respect.

The big disadvantage of charge-state logic schemes is that they require the absence of offset charges. In reality however, the background charge problem is almost insurmountable and is the main reason for the (practical)

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inapplica-1.3 Im schönsten Apfel sitzt der Wurm 9 bility of charge-state logic. The origin of the background charge is the extreme charge sensitivity of SET’s. A single charged vacancy or an interstitial ion in the oxide near a SET can be enough to switch the transistor from the being conducting to being nonconducting or to completely change the stability dia-grams, respectively.

1.3 Im schönsten Apfel sitzt der Wurm

In October 2002, the scandal of J. H. Schön shattered the (nano-) physics and electronics community when it became clear that most, if not all of his work had been fraudulent [16]. This included 13 publications in Science and Nature within a two-years time frame, every single one of which would have been a nanotechnology breakthrough.

None of Schön’s alleged observations had been reproduced in independent experiments. The reason why his activity could nevertheless persist for such a relatively long time is twofold. First, the results in this field are notoriously sample-specific and are not easily reproduced. Failure to reproduce a given result in a given sample is thus not considered proof of anything. And second, most of his alleged experiments had relied on his claim that his gate oxide was very strong. Indeed, in a publication where he had claimed to see supercon-ductivity in pentacene, his gate would have supported a charge accumulation about twice as high as achievable with the best alternative gate dielectrics.

A good gate oxide is of paramount importance for electronic devices. The higher the capacitance, the more charge can be accumulated, and the higher gain can be achieved. In principle, it should be possible to make even insu-lators conductive (or maybe superconductive. . . ) by inducing charge, but the gate oxide then obviously has to be an even better insulator.

Aluminum oxide, AlOx is sometimes argued to be a potential replacement

for silicon dioxide, and it is sputtered AlOx that Schön had reported to have

used. The quality of aluminum oxide is known to be very dependent on the preparation method. In chapter 4, the properties of aluminum oxide that forms naturally on the surface of freshly evaporated aluminum are investigated. The maximum charge accumulation was relatively high, but depending on the preparation method, there were also a lot of charge traps present.

One of Schön’s phenomenal papers described self-assembled monolayer field-effect transistors, where a monolayer of short molecules was sandwiched between two metal electrodes. He reported unreasonably high gate effects for such devices, and mainly because of this paper, the inconsistencies in the

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Schön data started to become apparent.

We also fabricated similar devices and measured the conductance across self-assembled monolayers of small molecules in the nanometer range. It was not much extra work to put a gate electrode nearby. Of course, we did not observe considerable gate effects, but we observed interesting non-linear cur-rent–voltage characteristics. The results that we obtained with these devices are communicated in chapter 5.

1.4 The ultimate miniaturization of size

Tremendous progress has been made during the last five years. Semiconduc-tor industry has not only pushed the limit and has demonstrated field-effect transistors with source–drain lengths below 20 nm, also conducting polymer thin film transistors and light–emitting diodes have experienced a remarkable development and have made it into commercial applications. Little is known however about the intermolecular and especially about the intramolecular con-duction mechanisms of organic molecules. Our challenge hence consisted in measuring the conduction across such molecules, preferably across a single molecule or at least just a few molecules in parallel.

The conductance measurements across self-assembled monolayers of mol-ecules described in the previous section has the disadvantage that the majority of molecules cannot be gated. We thus turned to longer molecules with sizes in the range between 5 and 10 nm. We deposited them between two electrodes with a gate electrode underneath and this way, good gate coupling could be achieved. We observed single-electron tunneling, albeit with voltage depen-dent resistances. The experimental results are detailed in chapter 6.

The recent years have seen a rapidly increasing number of efforts to mea-sure the conductance across even smaller molecules in the nanometer-scale range. It all started 1998 with a paper by M. A. Reed describing a break junc-tion technique [17]. Even though it is now generally agreed that its claim to measure the conductance across a single organic molecule was incorrect, it generated a lot of enthusiasm and research activity in various labs around the world. The break junction technique has since been refined, the presently most trusted experiments measuring organic molecules being carried out in Karl-sruhe [18], and having culminated in the measurement of the conductance of single hydrogen molecules [19]. However, this technique has the substantial disadvantage that a gate electrode so far could not have been incorporated. This gap has been filled by the invention of another method, viz. the

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electro-Bibliography 11 migration technique [20], and other methods involving electrochemical depo-sition and electrochemical etching are under development [21].

We also have succeeded in fabricating nanometer-sized gaps with a gate electrode underneath and self-assembling sub-nm sized molecules in between them. Indubitably, further miniaturization than this is not possible. We con-vincingly showed that the electrodes are well defined, and when depositing molecules with isocyanide end-groups between them, they simply act as vol-tage-dependent barriers. However, when molecules with thiol end-groups are self-assembled, single-electron tunneling is observed, in addition to a plethora of unorthodox phenomena. These are fundamentally interesting features that are as yet not understood and are still being investigated. Chapter 7 gives a detailed description of the measurement results.

Due to the very nature of the subject it is difficult to exactly know what it really is that finally is measured. To date, there just does not exist an imag-ing method that is able to resolve simag-ingle nanometer-sized organic molecules between metallic electrodes. Caution must therefore be employed when in-terpreting the measurement results, especially for the devices with extremely short molecules. In the end, it is only possible to exactly describe the sample fabrication process, to carefully perform control experiments, and to subse-quently interpret the measurement results in a cautious way. Even though this whole new field is controversial at times, it is an exciting and fascinating sub-ject that might yield innovative applications in due time and that in any case is of paramount fundamental interest.

Bibliography

[1] B. Yu, B. Wang, A. Joshi, Q. Xiang, E. Ibok, M. Lin, IEDM, Tech Dig. 937 (2001).

[2] B. Doris et al., IEDM (2002).

[3] C. R. Kagan, A. Afzali, R. Martel, L. M. Gignac, P. P. Solomon, A. G. Schrott, and B. Ek, Nano Lett. 3, 119 (2003).

[4] T. Theis, private communication (2003). [5] R. W. Keyes, Rev. Mod. Phys. 61, 279 (1989).

[6] J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, IEEE Electr. Dev. Lett, 19, 7 (1998).

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[8] J. R. Tucker, J. App. Phys. 72, 4399 (1992).

[9] A. N. Korotkov, R. H. Chen, and K. K. Likharev, J. App. Phys. 78, 2520 (1995).

[10] R. H. Chen, A. N. Korotkov, and K. K. Likharev, App. Phys. Lett. 68, 1954 (1996).

[11] M. G. Ancona, Superlatt. Microstruct. 20, 461 (1996).

[12] I. Amlani, A. O. Orlov, G. Toth, G. H. Bernstein, C. S. Lent, G. L. Snider, Science 284, 289 (1999).

[13] K. K. Likharev and A. N. Korotkov, Science 273 763 (1996). [14] K. K. Likharev, Int. J. Theor. Phys. 21, 311 (1982).

[15] C. H. Bennett, IBM J. Res. Develop. 17, 525 (1973).

[16] M.R. Beasley (Chair), S. Datta, H. Kogelnik, H. Kroemer, and D. Monroe, Report of the investigation committee on the possibility of scientific mis-conduct in the work of Hendrik Schön and coauthors,http://www.lucent. com/news_events/pdf/researchreview.pdf(2002).

[17] M. A. Reed, C. Zhou, C. J. Muller, T. P. Burgin, and J. M. Tour, Science 278, 252 (1997).

[18] J. Reichert, R. Ochs, D. Beckmann, H. B. Weber, M. Mayor, and H. v. Löh-neysen, Phys. Rev. Lett. 88, 176804-1 (2002).

[19] R. H. M. Smit, Y. Noat, C. Untiedt, N. D. Lang, M. C. van Hemert, and J. M. van Ruitenbeek, Nature 419, 906 (2002).

[20] H. Park, A. K. L. Lim, A. P. Alivisatos, J. Park, and P. L. McEuen, App. Phys. Lett 75, 301 (1999).

[21] Y. V. Kervennic, D. Vanmaekelbergh, L. P. Kouwenhoven, and H. S. J. van der Zant, Appl. Phys. Lett. 83, 3782 (2003).

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Chapter 2 Simulating Hybrid Circuits of

Single-Electron and Field-Effect Transistors

If you want to make beautiful music, you must play the black and the white notes together. RICHARDM. NIXON

An exact model for a single-electron transistor was developed within the cir-cuit simulation package SPICE. This model uses the orthodox theory of single-electron tunneling and determines the average current through the transistor as a function of the bias voltage, the gate voltage, and the temperature. Circuits including single-electron transistors, field-effect transistors (FET’s), and oper-ational amplifiers were then simulated. In these circuits, the single-electron transistors provide the charge sensitivity while the FET’s tune the background charges, provide gain, and provide low output impedance.

This chapter has been published in: Günther Lientschnig, Irek Weymann, and Peter Hadley, Jpn. J. App. Phys. 42, 6467 (2003).

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2.1 Introduction

Single-electron transistors (SET’s) are used to perform sensitive charge mea-surements and are widely discussed as possible components of dense inte-grated circuits [1]. These devices are attractive for applications in inteinte-grated circuits because they can be very small and they dissipate little power. How-ever, SET’s have low gain, high output impedances, and are sensitive to ran-dom background charges. This makes it unlikely that single-electron transis-tors would ever replace field-effect transistransis-tors (FET’s) in applications where large voltage gain or low output impedance is necessary. The most promis-ing applications for SET’s are charge senspromis-ing applications such as the readout of few electron memories [2], the readout of charge-coupled devices [3], and precision charge measurements in metrology [4]. In these applications, field-effect transistors are used to buffer the high output impedance of SET tran-sistors and to automatically tune the background charges. Here we present a SPICE model for a single-electron transistor that can be used to perform sim-ulations of circuits where single-electron transistors are combined with other circuit elements.

Several very good single-electron circuit simulation programs already ex-ist. Notable among these are SIMON [5] and MOSES[6]. However, these sim-ulation programs cannot include many standard electronic components such as diodes and transistors. We have chosen to model the SET circuits using SPICE [7] because it is so widely used to analyze electronic circuits. Exten-sive libraries of digital and analog circuit elements exist for SPICE. Other SPICE models for single-electron transistors also exist. These models are ei-ther phenomenological models [8], simplifications of the orthodox theory of single-electron tunneling [9, 10, 11], or they use extensions of SPICE that are not generic to all versions of SPICE[12]. Here we describe an implementation of the full orthodox theory that uses only the capabilities in publicly avail-able versions of SPICE [13]. The model uses a stationary master equation ap-proach that is suitable for quickly evaluating small circuits that combine SET’s and other standard circuit elements. The model presented here is not limited to single-electron transistors with tunnel junctions that have equal resistances and can be extended to include an arbitrary number of charge states enabling SET simulations for arbitrarily high temperatures and bias voltages.

In section2.2, the orthodox theory calculation is sketched and the imple-mentation of this theory in a SPICEmodel is discussed. The model is then vali-dated by comparing the current through a single-electron transistor predicted by the SPICE-SET model with the simulations of a conventional Monte-Carlo

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2.2 The model 15 circuit simulator. In section2.3, SPICEsimulations of circuits consisting of only SET’s are described. In particular, simulations of an inverter circuit and a ring oscillator are discussed. In section2.4, simulations of hybrid circuits involv-ing SET’s, FET’s, and operational amplifiers are described. In the simulations, field effect transistors are used to current bias SET’s, to buffer the high output impedance, and to tune the background charges. While the SPICE-SET model can be used to simulate circuits where single-electron transistors are combined with any other circuit elements, we only consider circuits that combine SET’s and FET’s since these are the most interesting for charge sensing applications.

2.2 The model

Figure2.1shows a schematic of a SET indicating the two tunnel junctions. In the model described here, two gates are coupled to the island. This is because many circuit applications require SET’s with two gates. A voltage source is at-tached to each electrode (the source, the drain, and the two gates). In addition to the two gates, a stray capacitance C0 to ground and a background charge

Q0 are included in the model. To determine the average current that flows

Figure 2.1:A schematic diagram of a single-electron transistor showing the two tunnel junctions, two gates, the stray capacitance C0, and the background charge Q0.

through the transistor, first the voltages of the island for the relevant charge states must be calculated. Simple electrostatics will show that the voltage of the island when a charge of ne is present on the island is,

V (n) = (ne + Q0+ C1V1+ C2V2+ Cg1Vg1+ Cg2Vg2)/CΣ. (2.1)

Here e is the positive elementary charge, n is an integer that specifies the num-ber of elementary charges that have been added to the island, CΣ = C1+ C2 +

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other quantities are defined in Fig.2.1. The energy it takes to move an infinites-imally small charge dq from ground at a potential V = 0 to the island is V dq. As soon as charge is added to the island, the voltage of the island changes. By integrating V dq from 0 to e one can show that the electrostatic energy needed to add a charge e to the island is,

eV (n) + e2/(2CΣ). (2.2)

The change in energy when a charge e tunnels from a lead at voltage Vi to the

island is thus,

∆Ei = −eVi+ eV (n) + e2/(2CΣ). (2.3)

When a charge of e tunnels from the island to a lead, the signs of the first two terms in eq. (2.3) are reversed. The change in energy can be used to calculate the tunnel rate, which is given by the expression,

Γi =

∆Ei

e2_R

i(exp(∆Ei/kBT ) − 1)

, (2.4)

where Ri is the tunnel resistance, T is the temperature and kB is Boltzmann’s

constant. There are four possible single-electron tunneling events for a SET. A charge e can tunnel left through tunnel junction 1 (Γ1L), one can tunnel right

through tunnel junction 1 (Γ1R), one can tunnel left through tunnel junction 2

(Γ2L), or one can tunnel right through tunnel junction 2 (Γ2R). Higher order

tunnel events where two or more electrons tunnel simultaneously are not con-sidered in this model.

Once the rates for all the relevant charge states have been determined, the probabilities that the charge states are occupied can be determined from the recursion relation,

P (n) = P (n − 1) Γ2L(n − 1) + Γ1R(n − 1) Γ2R(n) + Γ1L(n)

. (2.5)

The average current flowing through the transistor in the direction from tunnel junction 1 to tunnel junction 2 is,

I =X

n

eP (n)(Γ1R(n) − Γ1L(n)), (2.6)

and the average voltage of the island is,

V =X

n

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2.2 The model 17 To efficiently calculate the current and voltage, first the charge state n that has the highest probability to be occupied should be determined. This charge state can be estimated using eq. (2.5). The most probable charge state is [14],

nopt = −(Q0+ C1V1+ C2V2+ Cg1Vg1+ Cg2Vg2)/e +CΣ e V1R2+ V2R1 R1+ R2 . (2.8)

Figure 2.2:The model of a SET in SPICE. The white voltage sources are external to the SET model and the gray sources are internal to the model. E1 is a voltage source that fixes the voltage of the island of the SET (node 5) using eq. (2.7) and G1 is a current source that specifies the source - drain current using eq. (2.6).

Equations (2.1)–(2.8) were implemented in SPICE to calculate the values for the voltage source E1 and the current source G1 in the SPICE-SET model depicted in Fig. 2.2. The exact details and the complete source code of the model and for all the simulations described in this paper can be found online on our group’s Internet site [15].

The model can handle arbitrarily large gate voltages. Depending on the number of charge states implemented in the model, it can also handle arbitrar-ily high bias voltages and temperatures. The simulation time is linearly de-pendent on this number of charge states. The simulations described here were performed with a SPICE-SET model that includes eleven charge states around the most probable charge state. This is sufficient to perform room temperature simulations of transistors with a total capacitance of a few attoFarads. It is straightforward to extend this model to include more charge states as outlined in the source code on the Internet. By comparing the charging energy with the electron energies that are provided by the temperature and the expected maximum voltage difference ∆Vmax between source and drain, the number of

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charge states necessary can be estimated by,

n ≈ 2CΣ

e2 (e∆Vmax+ 7kBT ) . (2.9)

Here we have chosen to consider only electrons with a thermal energy of less than 7kBT which leaves us with an accuracy of about e−7 for the tunnel rates,

ie. the accuracy is in the 0.1 percent range.

Figure2.3compares the simulations of a single-electron transistor using the SPICE-SET model (black lines) with the ones using a conventional Monte-Carlo simulation program (gray lines). For the Monte-Carlo simulations we used SIMON[5] and we chose simulation parameters that resulted in approximately the same calculation time on a Pentium computer as the SPICE-SET simulation. As it clearly can be seen, the simulations give identical results except for some wiggles in the Monte-Carlo simulation lines which are due to the stochastic character of the Monte-Carlo algorithm.

In Fig.2.3(a), the current-voltage characteristics are plotted for a number of gate voltages. Figure 2.3 (b) shows the current through a SET as a func-tion of the gate voltage for a number of bias voltages. These periodic current oscillations are known as Coulomb oscillations. If the thermal fluctuations (≈ kBT) are larger than the energy it takes to add an electron to the island, the

Coulomb blockade is washed out. This is demonstrated in Fig. 2.3 (c) where the current-voltage characteristic is plotted for three different temperatures. In this simulation, a Coulomb staircase is clearly seen in the low temperature simulation. A Coulomb staircase is observed if the two tunnel junctions have greatly different resistances. The simulations in Fig.2.3were done for junction capacitances of C1 = C2 = 1aF. These are approximately the smallest

junc-tion capacitances that have been reproducibly obtained experimentally. Junc-tion capacitances of this magnitude were obtained by Pashkin et al. [16] using electron-beam lithography to define a 2 nm aluminum island. This was also achieved by Park et al. [17] by using a C60molecule as the conducting island.

Ono et al. [18] achieved such small junction capacitances in silicon by using pattern dependent oxidation.

Some care must be taken in using the SPICE-SET model described here. The model assumes that the capacitances of the source and drain electrodes are large enough that charge quantization on these electrodes can be neglected. Furthermore, the model calculates only the average current but does not in-corporate the stochastic nature of electron tunneling. This is a problem when frequencies approaching I/e are considered. Sometimes this SPICEmodel can

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2.2 The model 19

Figure 2.3: Comparison of the single-electron transistor simulations performed with the SPICE-SET model (black lines) with the ones performed with a conventional

Monte- Carlo simulation program (gray lines). In all three simulations the parame-ters used were: C1 = C2 = 1aF, Cg = 1aF, Cg2 = 0, C0 = 0, V1 = 0, Vg2 = 0, Q0 = 0.

(a) The current through the SET transistor is plotted as function of the bias voltage for six different gate voltages that induce (from bottom left to bottom right) charges -0.5e, -0.4e, -0.3e, -0.2e, -0.1e, and 0e, rspectively; T = 4.2 K, R1 = R2 = 100kΩ.

(b) The current through the SET transistor is plotted against the gate voltage for bias voltages V2 = 5 mV to 150 mV in steps of 5 mV, T = 4.2 K, R1 = R2 = 100kΩ. (c)

Current-voltage characteristics are plotted for three different temperatures, Vg1 = 0,

R1 = 100kΩ, R2 = 1MΩ.

also fail to converge at very low temperatures because a SET develops dis-continuities in the differential conductance in the limit of low temperatures. This however is not a limitation, since raising the temperature of the simula-tion somewhat solves this problem without changing the device

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characteris-tics. Despite the two limitations of the model described above, there are cir-cuits where it can be usefully applied. Two such circir-cuits, the single-electron inverter and the single-electron ring oscillator, are described in the following section.

Figure 2.4: A schematic diagram of a single-electron inverter and the input-output characteristics of the inverter calculated at 4.2 K, 27 K, and 77 K. The simulations performed with SPICE-SET (black lines) are compared with the ones performed with

a conventional Monte-Carlo simulation program (gray lines). To generate this graph, the parameters were taken from ref. [18]. All junction capacitances were set equal to C = 1aF, all junction resistances were set equal to R = 1 GΩ, the input capacitances were Cin1 = Cin2 = 2aF, the background charges were Q1 = −0.15e, Q2= 0.15e, and

the bias voltage was Vb = 20mV.

2.3 Single-electron transistor circuits

An inverter is a basic logic element that converts a low input signal into a high output signal and a high input signal into a low output signal [19, 20]. An inverter can be constructed by placing two single-electron transistors in series that share a common input gate (see Fig.2.4). For the SPICEmodel to be valid, the output capacitance CL, must be large enough that single-electron effects

on node 2 are not significant. Experimental realizations of single-electron in-verters are described in refs. [18] and [21]. Figure 2.4shows the input-output characteristics of a single-electron inverter. The parameters for this simulation were take from ref. [18]. For proper operation of the inverter, voltage gain is required. The output voltage must change faster than the input voltage in the

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2.3 Single-electron transistor circuits 21 transition region where the output changes from high to low. For the inverter in Fig.2.4, voltage gain at 30 K is possible but there is no voltage gain at 77 K. The largest voltage gain that has been observed in a single-electron inverter is 5.2 at 200 mK [22] and the highest temperature for which voltage gain was ob-served was a gain of 1.2 at 27 K [18]. Simulations show that substantial voltage gain at room temperature does not seem possible [23].

Figure 2.5: The output voltages of nine inverters in series as a function of time. The inverter characteristics are the same as in Fig.2.4except that the resistances have been reduced to 100 kΩ and the bias voltage has been increased to 35 mV. The operating temperature is 4.2 K.

To investigate the speed of the inverters, nine inverters were placed in se-ries with the output of each inverter connected to the input of the next inverter. The input of the first inverter was driven from low to high and this signal then propagated through the inverter chain. Figure 2.5 shows the results of this simulation. There is a delay of 90 ps at each inverter stage. The delay is largely determined by the output impedance of the inverters combined with the par-asitic capacitance of the wire at the output of the inverters. The capacitance at the output of the inverters was chosen to be 200 aF. This is the capacitance of a wire with a length of about 1 µm.

A ring oscillator is used to generate an oscillating signal. One can be built by connecting three inverters in a ring. This circuit has no dynamically stable solution, provided that the speed of a single inverter stage be sufficiently faster than the signal propagation through the whole circuit. Thus, the voltage at the output of each inverter oscillates as a function of time. Figure2.6 shows the ring oscillator circuit and the voltages at the outputs of the three inverters as a function of time. In the first 2 ns, the power supply is ramped up from 0 mV

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to 35 mV and the ring oscillator soon assumes its oscillating behavior.

Figure 2.6: The ring oscillator circuit and the voltages at the outputs of the three in-verters as a function of time. Each of the triangular inverter symbols represents the circuit shown in Fig. 2.4. The values for the resistances and capacitances on the in-put of each inverter are 10 MΩ and 100 aF. The power supply is ramped from 0 mV to 35 mV in the first 2 ns. In order to get each of the inverters started at a slightly different time, resistances of the order of 1 kΩ and capacitances of the order of 0.1 pF are added to the power supply. The solid line is the voltage at the output of the first inverter, the dashed line is the voltage at the output of the second inverter, and the dotted line is the voltage at the output of the third inverter.

2.4 SET’s combined with other circuit elements

The circuits described and simulated above consist entirely of single-electron transistors and basically reproduce results that can be obtained using other single-electron simulation programs. The real advantage of using SPICEis that other devices such as FET’s can be simulated in the same circuit with SET’s. In this section circuits with SET’s, FET’s, and operational amplifiers are de-scribed.

One of the problems that has to be addressed in single-electronics is how the SET’s will be biased. Many circuits require the SET’s to be current biased. However, it is impractical to use a separate external current source for every SET on a chip. A better solution is to make on-chip current sources for every SET that requires a current source. A simple current source can be constructed using just one FET. Figure2.7shows a single-electron transistor that is current

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2.4 SET’s combined with other circuit elements 23

Figure 2.7: The schematic of a current biased SET with a FET output stage and the corresponding SPICE simulation. The solid line is the voltage at the output voltage

of the SET stage (node 2) and the dashed line is the voltage at the output of the FET stage (node 4). A voltage of 0.4 V has been subtracted from the voltage at node 4 to remove a dc offset. The parameters of the SET are the same as the ones in Fig.2.3. The bias voltage is VDD = 1.5 V, and the resistor is 10 kΩ. For the MOSFET’s, a

standard Shichman-Hodges transistor model was used. For the NMOS bias transistor, the transconductance was specified with the SPICEparameter KP = 10−7A/V2and

the threshold voltage was chosen to be V T O = −1 V, while for the NMOS source follower, the transistor parameters were KP = 10−2A/V2_{and V T O = −0.5 V.}

biased by a FET and the corresponding SPICEsimulation of the circuit. A sec-ond FET is used in the circuit of Fig.2.7 to buffer the output of the SET. This is one way to solve the problem of the large output impedance of SET’s. It is fundamental to the operation of SET’s that the output impedance must be larger than the quantum resistance (≈ 25 kΩ), otherwise the charge on the is-land of the SET is not well defined. For SET’s that operate at high temperature, the output impedance is typically much larger. This is a problem if the output of the SET has to drive a signal a long distance across the chip. The time it takes for the output of the SET to settle to the right value is RC where R is the output impedance of the SET and C is the capacitance of the wire that carries the signal away from the SET. Thus, the high output impedance can make the response of the circuit slow. By adding the FET buffer stage at the output of the SET, the output impedance is reduced to 100 Ω, increasing the speed of the circuit greatly [24].

The thorny background charge problem can also be addressed by com-bining SET’s with other circuit elements. This problem arises because of the

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tremendous charge sensitivity of a SET. A single charged vacancy or an inter-stitial ion in the oxide near a SET can be enough to switch the transistor from conducting to nonconducting. The consequence of this is that when many SET’s are fabricated on a chip, some of them will be conducting with zero voltage applied to the gate and some will be nonconducting with zero volt-age applied to the gate. During the course of time, the charged defects often move or shift between different positions. These movements are detected by the single-electron transistors. The same kinds of charged defects are present and move in field-effect transistor circuits but most field-effect transistors are not as sensitive to charge so the consequences of these background charges are not as great. The background charge problem is probably the single greatest problem preventing the widespread use of SET’s integrated circuits.

Figure 2.8: The schematic of a charged-locked loop circuit and the corresponding SPICE simulation. The solid line shows that the voltage at the output is Vout =

−C_inVin/Cout. In the simulation Cin = 1aF and Cout= 0.1aF. The operational

ampli-fier is a Texas Instruments TLC2201 which is powered by two voltage sources of −5 V and +5 V, the bias voltage is Vb= 2V, and all the other parameters are the same as the

corresponding ones in Fig.2.7. The dashed line is the voltage at the output of the SET (node 2) when the loop is opened, i.e. when the output of the operational amplifier is disconnected from the gate capacitor Cout. The voltage gain, linearity, and dynamic

range are all improved by using a charge-locked loop.

There is a class of circuits called charged-locked loops that can automati-cally tune the background charge away. Figure2.8shows an example charged-locked loop circuit where a SET is current biased and feedback is used to keep the voltage across the SET constant. If charge is added at the input gate (node 3), the feedback circuit subtracts the same amount of charge from the

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feed-2.5 Conclusions 25 backoutput gate (node 4). The voltage change at the output is proportional to the voltage change at the input with a voltage gain set by the ratio of the in-put and outin-put capacitances Cin/Cout. In the simulation of Fig.2.8, the voltage

gain was set to be 10. Using a charge-locked loop improves both the linearity and the dynamic range of the charge measurement. Moreover, a charge-locked loop eliminates some of the problems associated with the background charge. The output voltage always changes by ∆Vout = −∆qin/Cout irrespective of the

background charge. This is not the only charged-locked loop circuit possible. Another way to build a charge-locked loop is to voltage bias a SET and use a feedback loop to keep the current through the SET constant. Sometimes an ac modulation of the gate charge is used to improve the charge sensitivity of a charge-locked loop.

2.5 Conclusions

A SPICEmodel for a single-electron transistor was described that implements the full orthodox theory of single-electron tunneling. This model can be com-bined with the standard SPICE libraries to simulate circuits of SET’s and con-ventional semiconductor devices. The complete source code for these simula-tions is available on the internet. The most promising applicasimula-tions for SET’s involve charge sensing in metrology or the readout of few electron memories. In these applications, SET’s should be integrated with field-effect transistors. The SET’s provide charge sensitivity and the field-effect transistors provide voltage gain, buffer the high output impedance of the SET’s, and tune the off-set charges.

Acknowledgements

We thank R. van der Haar, C. J. P. M. Harmans, R. Schouten, and Y. Nakamura for the useful suggestions they made.

Bibliography

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[2] K. K. Likharev and A. N. Korotkov, Proc. of the 1995 Int. Semicond. Device Res. Symp. (Univ. of Virginia, Charlottesville, VA, 1995) p. 355.

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[3] T. R. Stevenson, A. Aassime, P. Delsing, R. Schoelkopf, K. Segall, and C. M. Stahle, IEEE Trans. Appl. Supercond. 11, 692 (2001).

[4] M. W. Keller, A. L. Eichenberger, J. M. Martinis, and N. M. Zimmerman, Science 285, 1706 (1999).

[5] C. Wasshuber, H. Kosina, and S. Selberherr, IEEE Trans. Comput. Aided Des. 16, 937 (1997).

[6] R. H. Chen, Meeting Abstracts 96-2 (The Electrochem. Soc., Pennington, Pa., 1996) p. 576; MOSES = Monte Carlo Single Electron Simulator, http:

//hana.physics.sunysb.edu/set/software/index.html.

[7] SPICE = Simulation Program with Integrated Circuit Emphasis, http://

infopad.eecs.berkeley.edu/∼_{icdesign/Spice/}_{; for an overview see for}

ex-ample P. W. Tuinenga, Spice, A Guide to Circuit Simulation & Analysis Using PSpice (Prentice Hall, 3rd ed., 1995)

[8] Y. S. Yu, Y. I. Jung, J. H. Park, S. W. Hwang, and D. Ahn, Journal of the Korean Physical Society 35, S991 (1999).

[9] X. Wang and W. Porod, Superlattices and Microstructures 28, 345 (2000). [10] K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. Takagi, and A. Toriumi,

Jpn. J. Appl. Phys. 39, 2321 (2000).

[11] S. Amakawa, H. Majima, H. Fukui, M. Fujishima, and K. Hoh, IEICE Trans. Electron E81-C, 21 (1998).

[12] M. Kirihara, K. Nakazato, and M. Wagner, Jpn. J. Appl. Phys. 38, 2028 (1999).

[13] For instance, we used Orcad’s PSPICEavailable athttp://pcb.cadence.com. [14] A derivation of this result can be found at http://qt.tn.tudelft.nl/∼_hadley/

set/transistor/nopt.html.

[15] Seehttp://qt.tn.tudelft.nl/research/set/spice/.

[16] Yu. A. Pashkin, Y. Nakamura, and J.S. Tsai, Appl. Phys. Lett. 76, 2256 (2000).

[17] H. Park, J. Park, A. K. L. Lim, E. H. Anderson, A. P. Alivisatos, and P. L. McEuen, Nature 407, 57 (2000).

[18] Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, Hideo Namatsu, Kenji Kurihara, and Katsumi Murase, Appl. Phys. Lett. 76, 3121 (2000).

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Bibliography 27 [20] R. H. Chen, A. N. Korotkov, and K. K. Likharev, Appl. Phys. Lett. 68, 1954

(1996).

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Chapter 3 Single-Electron Tunneling Networks

Let us not confuse stability with stagnation.

MARYJEANLETENDRE

If islands and voltage sources are interconnected by tunnel junctions and capacitors, the resulting single-electron tunneling (SET) network is either sta-ble or unstasta-ble with respect to first-order tunnel events. This depends both on the topology of the network and on the applied voltages, and is best visu-alized with stability diagrams. Even for simple circuits, these diagrams can be very complex since every additional island increases the dimension of the problem by one. A program was developed that calculates stability diagrams for arbitrary SET networks analytically. This is many orders of magnitudes faster than what is achievable with Monte Carlo simulations. Furthermore, it provides detailed information about the charge states of the SET network and about multi-stable regions.

The program SETNETSis accessible over the Internet: G. Lientschnig and P. Hadley,http:

//qt.tn.tudelft.nl/research/set/setnets(1999). 29

Single-Electron and Molecular Devices

Single-Electron and

Molecular Devices

Single-Electron and

Molecular Devices

Proefschrift

Günther LIENTSCHNIG

Acknowledgement

Contents

Chapter 1

Introduction: From Metallic

Single-Electron Transistors to

Molecular Devices

1.1

Conservative Mentality, or Obvious Smartness?

1.2

The ultimate reduction of current

1.3

Im schönsten Apfel sitzt der Wurm

1.4

The ultimate miniaturization of size

Bibliography

Chapter 2

Simulating Hybrid Circuits of

Single-Electron and Field-Effect Transistors

2.1

Introduction

2.2

The model

2.3

Single-electron transistor circuits

2.4

SET’s combined with other circuit elements

2.5

Conclusions

Acknowledgements

Bibliography

Chapter 3

Single-Electron Tunneling Networks