AC Characteristics

NOTES:

1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.

2. Sampled, not 100% tested.

3. OE# may be delayed up to t_ELQV  tGLQV after the falling edge of BE₀# or BE₁# without impact to t_ELQV. V_CC=2.7V-3.6V, T_A=-40°C to +85°C

Symbol Parameter Notes Min. Max. Unit

t_AVAV Read Cycle Time 90 ns

t_AVQV Address to Output Delay 90 ns

t_ELQV BE₀# or BE₁# to Output Delay 3 90 ns

t_APA Page Address Access Time 35 ns

t_GLQV OE# to Output Delay 3 20 ns

t_PHQV RST# High to Output Delay 150 ns

t_EHQZ, t_GHQZ BE₀# or BE₁# or OE# to Output in High Z, Whichever Occurs

First 2 20 ns

t_ELQX BE₀# or BE₁# to Output in Low Z 2 0 ns

t_GLQX OE# to Output in Low Z 2 0 ns

t_OH Output Hold from First Occurring Address, BE₀# or BE₁# or OE#

change 2 0 ns

tAVQV

t_EHQZ t_GHQZ

tELQV

t_PHQV

t_GLQV

t_OH V_IH

V_IL

V_IH V_IL

V_IH V_IL

V_IH V_IL

V_OH V_OL

V_IH V_IL

(P) (D/Q) (W) (G) (E) (A) A_20-0

DQ_15-0 CE#

OE#

WE#

RST#

High Z

t_ELQX

VALID OUTPUT VALID

ADDRESS

t_GLQX

A_21-0 (A)

BE₀# or BE₁# (E)

Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code

t_AVQV

t_ELQV t_EHQZ

t_GHQZ

t_OH tAPA

t_GLQV

t_PHQV

High Z

V_IH V_IL

VIH

VIL

V_IH V_IL

V_IH V_IL

V_IH V_IL

(P) (W) (G) (E) (A) A_20-3

VIH

VIL

(A) A_2-0

V_OH V_OL (D/Q) DQ_15-0

CE#

OE#

WE#

RST#

t_GLQX t_ELQX

VALID ADDRESS

VALID

ADDRESS VALID

ADDRESS VALID ADDRESS

VALID

OUTPUT VALID

OUTPUT VALID

OUTPUT VALID OUTPUT VALID

ADDRESS

A_21-3 (A)

Figure 8. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks

BE₀# or BE₁# (E)

1.2.5 AC Characteristics - Write Operations

^{(1), (2)}

NOTES:

1. The timing characteristics for reading the status register during block erase, bank erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.

2. A write operation can be initiated and terminated with either BE₀# or BE₁# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width (t_WP) is defined from the falling edge of BE₀# or BE₁# or WE# (whichever goes low last) to the rising edge of BE₀# or BE₁# or WE# (whichever goes high first). Hence, t_WP=t_WLWH=t_ELEH=t_WLEH=t_ELWH.

5. Write pulse width high (t_WPH) is defined from the rising edge of BE₀# or BE₁# or WE# (whichever goes high first) to the falling edge of BE₀# or BE₁# or WE# (whichever goes low last). Hence, t_WPH=t_WHWL=t_EHEL=t_WHEL=t_EHWL.

6. V_PP should be held at V_PP=V_PPH1/2 until determination of block erase, (page buffer) program or OTP program success (SR.1/3/4/5=0) and held at V_PP=V_PPH1 until determination of bank erase success (SR.1/3/5=0).

7. t_WHR0 (t_EHR0) after the Read Query or Read Identifier Codes/OTP command=t_AVQV+100ns.

8. Refer to Table 6 for valid address and data for block erase, bank erase, (page buffer) program, OTP program or lock bit configuration.

V_CC=2.7V-3.6V, T_A=-40°C to +85°C

Symbol Parameter Notes Min. Max. Unit

t_AVAV Write Cycle Time 90 ns

t_PHWL (t_PHEL) RST# High Recovery to WE# (BE₀# or BE₁#) Going Low 3 150 ns t_ELWL (t_WLEL) BE₀# or BE₁# (WE#) Setup to WE# (BE₀# or BE₁#)

Going Low 4 0 ns

t_WLWH (t_ELEH) WE# (BE₀# or BE₁#) Pulse Width 4 60 ns

t_DVWH (t_DVEH) Data Setup to WE# (BE₀# or BE₁#) Going High 8 40 ns t_AVWH (t_AVEH) Address Setup to WE# (BE₀# or BE₁#) Going High 8 50 ns t_WHEH (t_EHWH) BE₀# or BE₁# (WE#) Hold from WE# (BE₀# or BE₁#)

High 0 ns

t_WHDX (t_EHDX) Data Hold from WE# (BE₀# or BE₁#) High 0 ns

t_WHAX (t_EHAX) Address Hold from WE# (BE₀# or BE₁#) High 0 ns

t_WHWL (t_EHEL) WE# (BE₀# or BE₁#) Pulse Width High 5 30 ns

t_SHWH (t_SHEH) WP# High Setup to WE# (BE₀# or BE₁#) Going High 3 0 ns t_VVWH (t_VVEH) V_PP Setup to WE# (BE₀# or BE₁#) Going High 3 200 ns

t_WHGL (t_EHGL) Write Recovery before Read 30 ns

t_QVSL WP# High Hold from Valid SRD 3, 6 0 ns

t_QVVL V_PP Hold from Valid SRD 3, 6 0 ns

t_WHR0 (t_EHR0) WE# (BE₀# or BE₁#) High to SR.7 Going "0" 3, 7 t_AVQV+

50 ns

tAVAV t_AVWH (t_AVEH)

t_WHAX (tEHAX)

t_ELWL (t_WLEL)

t_PHWL (t_PHEL)

t_WLWH

t_WHWL (t_EHEL)

t_WHDX (t_EHDX) tDVWH (tDVEH)

t_SHWH (t_SHEH)

tVVWH (tVVEH)

t_WHQV1,2,3 (t_EHQV1,2,3)

tQVSL

t_QVVL t_WHEH (t_EHWH) t_WHGL (t_EHGL)

V_IH V_IL

V_IH V_IL

V_IH V_IL

V_IH V_IL

V_IH V_IL (D/Q)

(W) (G) (E) (A)

NOTES 5, 6 A_20-0

DQ_15-0

V_PP(V)

V_IH

VPPH1,2

V V_IL

(P) RST#

CE#

OE#

WE#

VIH

VIL

(S) WP#

(t_ELEH )

NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5

VALID

ADDRESS VALID

ADDRESS VALID

ADDRESS

DATA IN DATA IN VALID

SRD

"1"

"0"

(R) SR.7

tWHR0 (tEHR0)

NOTES 5, 6 A_21-0 (A)

BE₀# or BE₁# (E)

ABORT COMPLETE

tPLPH

tPLPH

t2VPH

tPLRH tPHQV

tPHQV

(A) Reset during Read Array Mode

(B) Reset during Erase or Program Mode

(C) RST# rising timing RST#

RST#

VIL

VIH

VIL

VIH

VCC

GND V_CC(min)

RST#

VIL

VIH

SR.7="1"

V_OH V_OL

(D/Q)

DQ15-0 VALID

OUTPUT High Z

(P)

(P)

(P)

V_OH V_OL

(D/Q)

DQ15-0 VALID

OUTPUT High Z

V_OH V_OL

(D/Q)

DQ15-0 VALID

OUTPUT High Z

tPHQV

tVHQV

NOTES:

1. A reset time, t_PHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for t_PHQV.

2. t_PLPH is <100ns the device may still reset but this is not guaranteed.

3. Sampled, not 100% tested.

4. If RST# asserted while a block erase, bank erase, (page buffer) program or OTP program operation is not executing, the reset will complete within 100ns.

5. When the device power-up, holding RST# low minimum 100ns is required after V_CC has been in predefined range and also has been in stable there.

Reset AC Specifications (V_CC=2.7V-3.6V, T_A=-40°C to +85°C)

Symbol Parameter Notes Min. Max. Unit

t_PLPH RST# Low to Reset during Read

(RST# should be low during power-up.) 1, 2, 3 100 ns

t_PLRH RST# Low to Reset during Erase or Program 1, 3, 4 22 µs

t_2VPH V_CC 2.7V to RST# High 1, 3, 5 100 ns

t_VHQV V_CC 2.7V to Output Delay 3 1 ms

Figure 10. AC Waveform for Reset Operations

1.2.6 Reset Operations

1.2.7 Block Erase, Bank Erase, (Page Buffer) Program and OTP Program Performance

⁽³⁾

NOTES:

1. Typical values measured at V_CC=3.0V, V_PP=3.0V or 12V, and T_A=+25°C. Assumes corresponding lock bits are not set. Subject to change based on device characterization.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

4. A latency time is required from writing suspend command (WE# or BE₀# or BE₁# going high) until SR.7 going "1".

5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than t_ERES and its sequence is repeated, the block erase operation may not be finished.

6. When the OTP program operation is executed, write the OTP Program command with BE₀# at V_IL. OTP block in Bank 1 (selected by BE₁#=V_IL) should not be used.

V_CC=2.7V-3.6V, T_A=-40°C to +85°C

Symbol Parameter Notes

Page Buffer Command is Used or not

Used

V_PP=V_PPH1 (In System)

V_PP=V_PPH2

(In Manufacturing) Unit Min. Typ.⁽¹⁾ Max.⁽²⁾ Min. Typ.⁽¹⁾ Max.⁽²⁾ t_WPB 4K-Word Parameter Block

Program Time

2 Not Used 0.05 0.3 0.04 0.12 s

2 Used 0.03 0.12 0.02 0.06 s

t_WMB 32K-Word Main Block Program Time

2 Not Used 0.38 2.4 0.31 1.0 s

2 Used 0.24 1.0 0.17 0.5 s

t_WHQV1/

t_EHQV1 Word Program Time 2 Not Used 11 200 9 185 µs

2 Used 7 100 5 90 µs

t_WHOV1/

t_EHOV1 OTP Program Time 2, 6 Not Used 36 400 27 185 µs

t_WHQV2/ t_EHQV2

4K-Word Parameter Block

Erase Time 2 - 0.3 4 0.2 4 s

t_WHQV3/ t_EHQV3

32K-Word Main Block

Erase Time 2 - 0.6 5 0.5 5 s

Bank Erase Time 2 80 700 66 700 s

t_WHRH1/ t_EHRH1

(Page Buffer) Program Suspend

Latency Time to Read 4 - 5 10 5 10 µs

t_WHRH2/ t_EHRH2

Block Erase Suspend

Latency Time to Read 4 - 5 20 5 20 µs

t_ERES

Latency Time from Block Erase Resume Command to Block Erase Suspend Command

5 - 500 500 µs

2 Related Document Information

⁽¹⁾

NOTE:

1. International customers should contact their local SHARP or distribution sales offices.

Document No. Document Name

FUM00701 LH28F128BF series Appendix

A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.

If the timing in the figure is ignored, the device may not operate correctly.

t^2VPH VCC

GND V_CC(min)

RP#

VIL

VIH

(P)

tPHQV

V_CCW ^*1

GND VCCWH1/2

(V)

CE#

VIL

VIH

(E)

WE#

VIL

VIH

(W)

OE#

VIL

VIH

(G)

WP#

VIL

V^IH

(S)

V_OH V_OL

(D/Q)

DATA High Z Valid

Output tVR

tF tELQV

tF tGLQV

ADDRESS(A) Valid

(RST#)

(V_PP)

t^Ror t^F

Address VIL

VIH

t^AVQV tRor tF

tR

tR

*1 To prevent the unwanted writes, system designers should consider the design, which applies VCCW (VPP) (VPPH1/2)

BE₀# or BE₁# (E)

A-1.1.1 Rise and Fall Time

NOTES:

1. Sampled, not 100% tested.

2. This specification is applied for not only the device power-up but also the normal operations.

Symbol Parameter Notes Min. Max. Unit

t_VR V_CC Rise Time 1 0.5 30000 µs/V

t_R Input Signal Rise Time 1, 2 1 µs/V

t_F Input Signal Fall Time 1, 2 1 µs/V

A-1.2 Glitch Noises

Do not input the glitch noises which are below V_IH (Min.) or above V_IL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).

Figure A-2. Waveform for Glitch Noises

See the “DC CHARACTERISTICS“ described in specifications for V_IH (Min.) and V_IL (Max.).

(a) Acceptable Glitch Noises Input Signal

VIH(Min.)

Input Signal

VIH(Min.)

Input Signal VIL (Max.)

Input Signal VIL (Max.)

(b) NOT Acceptable Glitch Noises

A-2 RELATED DOCUMENT INFORMATION

⁽¹⁾

NOTE:

1. International customers should contact their local SHARP or distribution sales office.

Document No. Document Name

AP-001-SD-E Flash Memory Family Software Drivers

AP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, V_PP Electric Potential Switching Circuit

NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas

5700 NW Pacific Rim Blvd.

Camas, WA 98607, U.S.A.

Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 Fast Info: (1) 800-833-9437 www.sharpsma.com

SHARP Microelectronics Europe

Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3

20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com

SHARP Corporation

Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221

Fax: (81) 6117-725300/6117-725301 www.sharp-world.com

TAIWAN SINGAPORE KOREA

SHARP Electronic Components (Taiwan) Corporation

8F-A, No. 16, Sec. 4, Nanking E. Rd.

Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341

Fax: (886) 2-2577-7326/2-2577-7328

SHARP Electronics (Singapore) PTE., Ltd.

438A, Alexandra Road, #05-01/02 Alexandra Technopark,

Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855

SHARP Electronic Components (Korea) Corporation

RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819

CHINA HONG KONG

SHARP Microelectronics of China (Shanghai) Co., Ltd.

28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office:

No. 360, Bashen Road, Xin Development Bldg. 22

Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China

Email: smc@china.global.sharp.co.jp

SHARP-ROXY (Hong Kong) Ltd.

3rd Business Division,

17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk

Shenzhen Representative Office:

Room 13B1, Tower C,

Electronics Science & Technology Building Shen Nan Zhong Road

Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735

W dokumencie LH28F128BFHED-PWTL90 (Stron 24-0)