The Am95C60 is a graphics processing chip capable of handling a" the necessary tasks for supporting a
bit-mapped display memory graphics scheme, where the display memory is constructed from Video DRAMs. As such, much of the work load in supporting the graphics SUb-system is taken from the host CPU and handled directly by this dedicated graphics processor. These features include dynamic memory refresh control, video display refresh control, line drawing and other graphic function support, and arbitration to allow other parts of the system access to the video display memory.
The Frame Buffer
The frame buffer consists of a number of memory de-vices which hold the current picture information to be supplied to the video display device (CRT).
Video DRAMs are used as the memory device for such a frame buffer. This special type of DRAM is similar to standard DRAMs, but has additional features which include a second port, ideal for supporting the interface to a video system.
In a special access cycle, called a Transfer Cycle, 1024 pixels of data can be read from the DRAM array into an on-chip shift mechanism. This shift mechanism can then be driven independently of, andconcurrentlywith, further accesses to the DRAM array from the normal (host) port, providing serial pixel data at rates of up to 100 MHz. For example, by banking four Video DRAMs in para"el to provide a 16-bit data path, pixel rates of up to 400 MHz are achievable, with the real limiting factor being the maximum clock rate of the shift registers being used (Am8177 and Am8172 - 200 MHz max).
The advantage of this scheme over a system with video memory constructed from standard DRAMs is that typi-cally the host or Am95C60 can access the video memory of Video DRAMs for update in excess of 95% of the time, compared with less than 40% of the time for a video memory of standard DRAMs. This wi" offer a greater drawing and BUTing capability, an essential feature in supporting animation and quick drawing and data trans-fer responses, key features in today's workstations.
The Am95C60 generates all the necessary signals to control such a Video DRAM array.
2.3.2 How to Address Peripheral Chips in a 68020 System
Vlnual Memory • How
to
Address Hardware ResourcesA virtual memory scheme allows a process in execution to have access to the total address space of the CPU, which for the MC68020 is 4 Gbytes (32 address lines).
The address generated by the host processor will index
. -Virtual
Address
PAGER
MC68020 (Address
Processor Translate)
Hardware Address Decode
I - - Hardware t - - - Resource I - - Enables
Other System resources
Physical SYSTEM
SCSI Address MEMORY ETHERNET
etc.
32 Bit System Bus
I I I
~
I.-
10
' - DMA Am95C60 Display
Memory
f-.: I
Figure 2.3-1 Typical Workstation Block Diagram
into a page table mechanism, or pager, which maps this 4 Gbytes of virtual address space to the physical memory within the system.
The pager system needs not only to generate the re-quired address lines to the physical memory, translated from the virtual address, but must be able to select the hardware resources within the system. A simple method of implementing this could be to configure the pager system to generate one more physical address line than is required to address the system memory. The addi-tional line is used to indicate that the access is to a hardware resource, not system memory. The page table entries can hence be set up to map a virtual address to any hardware resource within the system, offering maxi-mum flexibility. To address a number of hardware resources within this "hardware address space", the additional address line can be used to enable decode logic of the lower address lines, thus disabling any access to the system memory to select the desired hardware resource.
Using this type of scheme, the enable to any peripheral device, such as the graphics engine, can be generated
from the pager hardware system, which would include the additional address decode logic to generate individ-ual chip select lines to each hardware resource within the system. For hardware resources containing a numberof registers, some of the low order address lines can be used to address such registers, together with the chip select to that device.
The pager would also need to indicate to memory if and when the presented physical address is valid (PhyStrobe). This would be true only if a mapping of virtual address to physical address was found.
Other lines may be available on the system bus to qualify the address space (the function code lines FCO-2 for the MC68020), or to define whether the access is for code or data within user or supervisor address space. This information may also be used by the pager system to implement a memory protection scheme, but this is beyond the scope of this application note. (See Figure 2-3.2)
Typically the address decode can most simply be imple-mented using a combinatorial PAL device. (See Figures 2-3.3 and 2-3.4)
CHAPTER 2
System Bus Interface
Interrupt
PAGER Hardware Enables
I
Hardware Spacek defines the No. of Hardware Resources within system.
Enable
Figure 2_3-2 Simplified Pager System Block Diagram
(Physical Address Strobe) (Hardware Space/-Memory)
Hardware Resource {
PHYSTROBE
Note: CSOPDM Is set when any OPDM Is chip selected (used by DSACK generation loglc--see Ag. 2.3-12)
CSPLANE CSPIXEL ... ote.
Figure 2_3-3 Hardware Resource Address Decoding
Fig. 2.3-3
Figure 2_3-4 MC68020-Am95C60 System Block Diagram INT