OPERAND ADDRESSING MODES
1. Index Register Map
5.0 Instruction Set Overview (Continued)
Register (MSB) (LSB)
Integer Arithmetic Instructions
The integer arithmetic instructions operate on 8-bit signed (two’s complement) binary numbers. Two arithmetic func
tions are supported: Add and Subtract. Three versions of the Add and Subtract instructions exist: operand ± accumu
lator, operand ± accumulator ± carry, and immediate oper
and ± operand. The first two versions support both the reg
ister and indexed addressing modes for the destination op
erand. These two versions also allow the specification of a separate register or data address for the destination oper
and so that the sources may retain their integrity; (i.e., true three-operand instructions). Note that the currently active
“ B” register bank selects which accumulator is used in these instructions. The third version, immediate operand ± operand, only supports the register addressing mode for the
5.0 Instruction Set Overview
(Continued)destination operand with the register as both a source and the destination. Table VI lists the integer arithmetic instruc
tions along with their variations.
Logic Instructions
The logic instructions operate on 8-bit binary data. A full set of logic functions is supported by the BCP: AND, OR, exclu
sive OR, and Complement. All the logic functions except complement allow either an immediate operand or the cur
rently active accumulator as an implied operand. Comple
ment only allows one register operand which is both the source and destination. The other logic instructions include the following addressing modes: register, indexed, and im
mediate. As with the integer arithmetic instructions, the in
tegrity of the sources may be maintained by specifying a destination register which is different from the source. Table VII lists all the logic instructions.
TABLE VI. Integer Arithmetic Instructions
Syntax Instruction Operation Addressing Modes
ADD n, rsd register + n —► register Immediate, Limited Register
ADDA Rs, Rd Rs + accumulator —* Rd Register, Register
ADDA Rs, [mir] Rs + accumulator —► data memory Register, Indexed
ADCA Rs, Rd Rs + accumulator + carry —► Rd Register, Register
ADCA Rs, [mir] Rs + accumulator + carry —► data memory Register, Indexed
SUB n, rsd register - n —> register Immediate, Limited Register
SUBA Rs, Rd Rs - accumulator —► Rd Register, Register
SUBA Rs, [mir] Rs - accumulator data memory Register, Indexed
SBCA Rs, Rd Rs - accumulator - carry —► Rd Register, Register
SBCA Rs, [mir] Rs - accumulator - carry —► data memory Register, Indexed
TABLE VII. Logic Instructions
Syntax Instruction Operation Addressing Modes
AND n, rsd register & n —* register Immediate, Limited Register
ANDA Rs, Rd Rs & accumulator —* Rd Register, Register
ANDA Rs, [mir] Rs & accumulator —► data memory Register, Indexed
OR n, rsd register | n —► register Immediate, Limited Register
ORA Rs, Rd Rs | accumulator —* Rd Register, Register
ORA Rs, [mir] Rs | accumulator —* data memory Register, Indexed
XOR n, rsd register © n —► register Immediate, Limited Register
XORA Rs, Rd Rs © accumulator —» Rd Register, Register
XORA Rs, [mir] Rs © accumulator —* data memory Register, Indexed
CPL Rsd register —► register Register
Note: & = logical AND operation
| = logical OR operation
© = logical exclusive OR operation r = one’s complement
P 8 3 4 4 A
D P 8 3 4 4
Shift and Rotate Instructions
The shift and rotate instructions operate on any of the 8-bit CPU registers. The BCP supports shift left, shift right, and rotate operations. Table VIII lists the shift and rotate instruc
tions.
Comparison Instructions
The BCP utilizes two comparison instructions. The CMP in
struction performs a tw o’s complement subtraction between a register and immediate data. The BIT instruction tests se
lected bits in a register by ANDing it with immediate data.
Neither instruction stores its results, only the ALU flags are affected. Table IX lists both of the comparison instructions.
Program Flow Instructions
The BCP has a wide array of program flow instructions: un
conditional jumps, calls and returns; conditional jumps, calls, and returns; relative or absolute instruction addressing on jumps and calls; a specialized register field decoding
5.0 Instruction Set Overview
(Continued)jump; and software interrupt capabilities. These instructions redirect program flow by changing the Program Counter.
The unconditional jump instructions support both relative in
struction addressing, the (JuMP instruction), and absolute instruction addressing, (the Long JuMP instruction), using the following addressing modes: Immediate, Register, Abso
lute, and Indexed. Table X lists the unconditional jump in
structions and their variations.
The conditional jump instructions support both relative in
struction addressing and absolute instruction addressing us
ing the Immediate and Absolute addressing modes. The conditional relative jump instruction tests flags in the Condi
tion Code Register, {CCR}, and the Transceiver Status Register, (TSR). Two possible syntaxes are supported for the conditional relative jump instruction; see Table XI.
Table XII lists the various flags “ f” that the conditional JMP instruction can test and Table XIII lists the various condi
tions “cc” that the Jcc instruction can test for. Keep in
TABLE VIII. Shift and Rotate Instructions
Note: “ b” = the number of bit shifts/rotates to perform.
TABLE IX. Comparison Instructions Syntax Instruction Operation Addressing Mode CMP rs, n
BIT rs, n
register - n register & n
Limited Register Limited Register Note: & = logical AND operation
TABLE X. Unconditional Jump Instructions
Syntax Instruction Operation Operand Range Addressing Mode JMP n PC + n (sign extended) —> PC -1 2 8 , + 1 2 7 Immediate JMP Rs PC + Rs (sign extended) —> PC -1 2 8 , + 1 2 7 Register
LJMP nn nn —► PC 0, 64k Absolute
LJMP [lr] lr —* PC 0, 64k Indexed
Note: PC = Program Counter; contents initially points to instruction following jump.
On the other hand, the conditional absolute jump instruc
tion, LJMP, can test any bit in any currently active CPU reg
ister. Table XIV shows the conditional long jump instruction syntax.
JMP Z,NS,SKIP.IT ;If [Z]=0 goto SKIP.IT
-or-JNZ SKIP.IT ;If [Z]=0 goto SKIP.IT FIGURE 2. Coding Examples of Equivalent
Conditional Jump Instructions
TABLE XI. Conditional Relative Jump Instruction
Syntax Instruction Operation Operand Range Addressing Mode
JMP f,s,n If the flag “ f” is in the state “ s”
then PC + n (sign extended) —► PC
-1 2 8 , + 1 2 7 Immediate
Jcc n If the condition “cc” is met
then PC + n (sign extended) —► PC
-1 2 8 , + 1 2 7 Immediate
Note: PC = Program Counter; contents initially points to instruction following jump.
TABLE XII. “f” Flags
“f”(Binary) Flag Flag Name Register Containing Flag
000 z Zero (CCR}
001 c Carry (CCR)
010 V Overflow (CCR)
011 N Negative (CCR)
100 RA Receiver Active (TSR)
101 RE Receiver Error (TSR)
110 DAV Data Available (TSR}
111 TFF Transmitter FIFO Full (TSR)
TABLE XIII. “cc” Conditions Tested
“cc” Field Condition Tested for Flag “f”’s Condition
Z Zero [Z] = 1
NZ Not Zero [Z] = 0
EQ Equal [Z] = 1
NEQ Not Equal [Z] = 0
C Carry [C] = 1
NC No Carry [C] = 0
V Overflow [V] = 1
NV No Overflow [V] = 0
N Negative [N] = 1
P Positive [N] = 0
RA Receiver Active [RA] = 1
NRA Not Receiver Active [RA] = 0
RE Receiver Error [RE] = 1
NRE No Receiver Error [RE] = 0
DA Data Available [DAV] = 1
NDA No Data Available [DAV] = 0
TFF Transmitter FIFO FULL [TFF] = 1
NTFF Transmitter FIFO Not Full [TFF] = 0
TABLE XIV. Conditional Absolute Jump Instruction
Syntax Instruction Operation Operand Range Addressing Mode
LJMP Rs,p,s,nn If the bit of register “ Rs” in 0, 64k Register, Absolute
position “ p” is in the state “ s”
then nn —► PC Note: PC = Program Counter
mind that the Jcc instruction is just an optional syntax for the conditional JMP instruction.
The example in Figure 2 demonstrates two possible ways to code the conditional relative jump instruction when testing for a false [Z] flag in (CCR). In the example, assume that the symbol “ Z” equals “ 000” binary, that the symbol “ NS”
equals “ 0” binary, and that the symbol “ SKIP.IT” points to the desired instruction with which to begin execution if [Z] is
5.0 Instruction Set Overview
(Continued)P 8 3 4 4 A
D P 8 3 4 4
TABLE XV. JRMK Instruction
Syntax Instruction Operation Displacement
Range Addressing Mode JRMK Rs, b, m (a) Rotate a copy of register “ Rs” “ b” bits to the right.
(b) Mask the most significant “ m” bits and the least significant bit of the above result.
(c) PC + resulting displacement (sign extended) —* PC.
-1 2 8 , + 1 2 6 Register The BCP also has a specialized relative jump instruction
called relative Jump with Rotate and Mask on source regis
ter, JRMK. This instruction facilitates the decoding of regis
ter fields often involved in communications processing.
JRMK does this by rotating and masking a copy of its regis
ter operand to form a signed program counter displacement which usually points into a jump table. Table XV shows the syntax and operation of the JRMK instruction.
JRMK’s masking, (setting to zero), the least significant bit of the displacement allows the construction of a jump table using either one or two word instructions; for instance, a table of JMP and/or LJMP instructions, respectively. The example in Figure 3 demonstrates the JRMK instruction de
coding the address frame of the 3299 Terminal Multiplexer
5.0 Instruction Set Overview
(Continued)protocol which is located in the Receive/Transmit Register, {R T R I4 -2 ]}.
The BCP has two unconditional call instructions; CALL, which supports relative instruction addressing and LCALL, (Long CALL), which supports absolute instruction address
ing. These instructions push the following information onto the CPU’s internal Address Stack: the address of the next instruction; the status of the Global Interrupt Enable flag, [GIE]; the status of the ALU flags [Z], [C], [N], and [V]; and the status of which register banks are currently active. Table XVI lists the two unconditional call instructions. Note that the Address Stack is only twelve positions deep; therefore, the BCP allows twelve levels of nested subroutine invoca
tions, (this includes both interrupts and calls).
Note: PC = Program Counter, contents initially points to instruction following jump.
Example Code JRMK RTR, 1, 4 LJMP ADDR.O LJMP ADDR.l
LJMP ADDR.7
jdecode terminal address
;jump to device handler #0
;jump to device handler #1
;jump to device handler #7
Instruction Execution JRMK Displacement Register Contents
(a) Copy { RTR } into JRMK’s displacement register: X X X A2 A1 A0 y y
(b) Rotate displacement register 1 bit to the right: y X X X A2 A1 A0 y
(c) AND result with “ 00001110” binary mask:
(d) Sign extended resulting displacement and add
0 0 0 0 A2 A1 A0 0
it to the program counter, (PC).
If the bits A2 A1 A0 equal “ 0 0 1 ” binary then
+ 2 is added to the Program Counter; 0 0 0 0 0 0 1 0
(i.e., PC + 2 PC).
(e) Execute the instruction pointed to by the PC, which in this example is:
Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] = Global Interrupt Enable bit.
& = concatenation operator, combines operands together forming one long operand.
The BCP has one conditional call instruction capable of testing any bit in any currently active CPU register. This call only supports absolute instruction addressing. Table XVII shows the conditional call instruction syntax and operation.
The return instruction complemetns the above call instruc
tions. Two versions of the return instruction exist, the un- condtional return and the conditional return. When the un
conditional return instruction is executed, it pops the last address on the CPU’s Address Stack into the program counter and it can optionally affect the [GIE] bit, the ALU
5.0 Instruction Set Overview
(Continued)flags, and the register bank selection. Table XVIII shows the syntax and operation of the unconditional return instruction.
The conditional return instruction functions the same as the unconditional return instruction if a desired condition is met.
As with the conditional jump instruction, the conditional re
turn instruction has two possible syntaxes. Table XIX lists the syntax for the conditional return. The “ f” flags and the
“cc” conditions for the return instruction are the same as for the conditional jump instruction, therefore refer to Table XII and Table XIII for the listing of “f” and “cc”, respective
ly-TABLE XVII. Conditional Call Instruction
Syntax Instruction Operation Operand Range Addressing Mode
LCALL Rs, p, s, nn If the bit of register “ Rs” in position
“ p” is in the state “ s” then PC & [GIE] & ALU flags &
reg. bank selection —► Address Stack nn —► RC
End if
0, 64k Register, Absolute
Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] = Global Interrupt Enable bit
& = concatenation operator, combines operands together forming one long operand.
TABLE XVIII. Unconditional Return Instruction
Syntax Instruction Operation
RET ( g f.r flS Case “ g” of
0: leave [GIE] unaffected, (default) 1: restore [GIE] from Address Stack 2: set [GIE]
3: clear [GIE]
End case If “ rf” = 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack Else (the default)
leave the ALU flags and register bank selections unchanged End if
Address Stack —► PC Note: PC = Program Counter
[GIE] = Global Enable bit
{} = surrounds optional operands; not part of the instruction syntax.
Optional operands may either be specified or omitted.
TABLE XIX. Conditional Return Instruction
Syntax Instruction Operand
RETF f , s f , f g ) , { , r f i ) Rcc { g f . r f i l
If the flag “f” is in the state “ s” then perform a RET {g [, r f ) ) If the condition “cc” is met then perform a RET (g { ,rf}) Note: See Table XVIII for an explanation of “ RET [g {, r f } } ”
{} = surrounds optional operands; not part of the instruction syntax.
Optional operands may either be specified or omitted.
P 8 3 4 4 A
D P 8 3 4 4
In addition to the above jump, call and return program flow instructions, the BCP is capable of generating software in
terrupts via the TRAP instruction. This instruction generates a call to any one of 64 possible interrupt table addresses based on its vector number operand. This allows both the simulation of hardware interrupts and the construction of special software interrupts, if desired. The actual interrupt table entry address is determined by concatenating the In
terrupt Base Register, {IBR }, to an 8-bit representation of the vector number operand in the TRAP instruction. This instruction may also clear the [GIE] bit, if desired. Table XX shows the syntax and operation of the TRAP instruction.
5.0 Instruction Set Overview
(Continued)Miscellaneous Instructions
As stated in the “ CPU Register Set” section, the BCP has 44 registers with 24 of them arranged into four register banks: Main Bank A, Alternate Bank A, Main Bank B, and Alternate Bank B. The exchange instruction, EXX, selects which register banks are currently available to the CPU, for example either Main Bank A or Alternate Bank A. The dese
lected register banks retain their current values. The EXX instruction can also alter the state of [GIE], if desired. Table XXI shows the EXX instruction syntax and operation.
TABLE XX. TRAP Instruction
Syntax Instruction Operation Operand Range
TRAP v (, g '} PC & [GIE] & ALU flags &
reg. Bank selection —> Address Stack If “ g '” = 1 then clear [GIE]
Form PC address as shown below:
0, 63
i i i i i i i— i— i i i i i
{IBR} 0 0 v 1►PC
15 7 5 0
Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] = Global Interrupt Enable bit IBR = Interrupt Base Register
& = concatenation operator, combines operands together forming one long operand.
{ } = surrounds optional operands; not part of the instruction syntax.
Optional operands may either be specified or omitted.
TABLE XXL EXX Instruction Syntax Instruction Operation EXX ba, bb (,g ) Case “ ba” of
0: activate Main Bank A 1: activate Alternate Bank A End case
Case “ bb” of
0: activate Main Bank B 1: activate Alternate Bank B End case
Case “ g” of
0: leave [GIE] unaffected, (default) 1: (reserved)
2: set [GIE]
3: clear [GIE]
End case Note: [GIE] = Global Interrupt Enable bit
{ ) = surrounds optional operands; not part of the instruction syntax.
Optional operands may either be specified or omitted.
INTRODUCTION
The Instruction Set Reference section contains detailed in
formation on the syntax and operation of each BCP instruc
tion. The instructions are arranged in alphabetical order by mnemonic for easy access. Although this section is primarily intended as a reference for the assembly language pro
grammer, previous assembly language experience is not a prerequisite. The intent of this instruction set reference is to include all the pertinent information regarding each instruc
tion on the page(s) describing that instruction. The only ex
ceptions to this rule concerns the instruction addressing modes and the bus timing diagrams. The discussion of the instruction addressing modes occurs at the beginning of the BCP Instruction Set Overview section and, therefore, will not be repeated here. The figures for the bus timing dia
grams are located at the end of this introduction rather than constantly repeating them under each instruction. On the other hand, the information that is contained under each instruction is divided into eight categories titled: Syntax, Af
fected Flags, Description, Example, Instruction Format, T-states, Bus Timing, and Operation. The following para
graphs explain what information each category conveys and any special nomenclature that a category may use.
Syntax
This category illustrates the assembler syntax for each in
struction. Multiple lines are used when a given instruction supports more than one type of addressing mode or if it has an optional mnemonic. All capital letters, commas, (,) math symbols ( + , - ) , and brackets ([ ]) are entered into the as
sembler exactly as shown. Braces ({ }) surround an instruc
tion’s optional operands and their associated syntax. The text between the braces may either be entered in with or omitted from the instruction. The braces themselves should not be entered into the assembler because they are not part of the assembler syntax. Lower case characters and oper
ands that begin with the capital R represent symbols. These must be replaced with actual register names, numbers, or equated registers and numbers. Table XXII lists all the sym
bols and their associated meanings.
Affected Flags
If an instruction sets or clears any of the ALU flags, (i.e., Negative [N], Zero [Z], Carry [C], and/or Overflow [V], then those flags affected are listed under this category.
Description
The Description category contains a verbal discussion about the operation of an instruction, the operands it allows, and any notes highlighting special considerations the pro
rammer should keep in mind when using the instruction. assumes that the “ .EQU” assembler directive has been pre
viously executed to establish these relationships. Informa
tion relating register abbreviations to register names, num
bers, and purpose is located in the CPU Registers section.