Keyboard Interrupt (S08KBIV2)
10.1 Introduction
The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources.
Only four (KBI1P0–KBI1P3) of the possible interrupts are implemented on the MC9S08QD4 series MCU.
These inputs are selected by the KBIPE bits.
Figure 10-1 Shows the MC9S08QD4 series with the KBI module and pins highlighted.
Chapter 10 Keyboard Interrupt (S08KBIV2)
Figure 10-1. MC9S08QD4 Series Block Diagram Highlighting KBI Block and Pins NOTES:
1 Port pins are software configurable with pullup device if input port.
2 Port pins are software configurable for output drive strength.
3 Port pins are software configurable for output slew rate control.
4 IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6 PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
7 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device.
USER RAM HCS08 CORE
CPU BDC
2-CH 16-BIT TIMER/PWM MODULE (TPM1) HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
VOLTAGE REGULATOR
PORT A
PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 4-BIT KEYBOARD
INTERRUPT MODULE (KBI)
256 / 128 BYTES
16 MHz INTERNAL CLOCK SOURCE (ICS)
VSS VDD
VSSA VDDA
VREFL VREFH
4
ANALOG-TO-DIGITAL CONVERTER (ADC)
10-BIT
TPM1CH0 TPM1CH1 BKGD/MS
IRQ
4 1-CH 16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH0
USER FLASH 4096 / 2048 BYTES
TCLK2
TCLK1
Keyboard Interrupts (S08KBIV2)
10.1.1 Features
The KBI features include:• Up to eight keyboard interrupt pins with individual pin enable bits.
• Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity.
• One software enabled keyboard interrupt.
• Exit from low-power modes.
10.1.2 Modes of Operation
This section defines the KBI operation in wait, stop, and background debug modes.
10.1.2.1 KBI in Wait Mode
The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is enabled (KBIE = 1).
10.1.2.2 KBI in Stop Modes
The KBI operates asynchronously in stop3 mode if enabled before executing the STOP instruction.
Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of stop3 mode if the KBI interrupt is enabled (KBIE = 1).
During either stop1 or stop2 mode, the KBI is disabled. In some systems, the pins associated with the KBI may be sources of wakeup from stop1 or stop2, see the stop modes section in the Modes of Operation chapter. Upon wake-up from stop1 or stop2 mode, the KBI module will be in the reset state.
10.1.2.3 KBI in Active Background Mode
When the microcontroller is in active background mode, the KBI will continue to operate normally.
10.1.3 Block Diagram
The block diagram for the keyboard interrupt module is shown Figure 10-2.
Keyboard Interrupts (S08KBIV2)
Figure 10-2. KBI Block Diagram
10.2 External Signal Description
The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests.
The signal properties of KBI are shown in Table 10-1.
10.3 Register Definition
The KBI includes three registers:
• An 8-bit pin status and control register.
• An 8-bit pin enable register.
• An 8-bit edge select register.
Refer to the direct-page register summary in the Memory chapter for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names.
Some MCUs may have more than one KBI, so register names include placeholder characters to identify which KBI is being referenced.
10.3.1 KBI Status and Control Register (KBISC)
KBISC contains the status flag and control bits, which are used to configure the KBI.
Table 10-1. Signal Properties
Signal Function I/O
KBIPn Keyboard interrupt pins I
D Q
CK CLR VDD
KBMOD
KBIE KEYBOARD
INTERRUPT FF KBACK RESET
SYNCHRONIZER KBF
STOP BYPASS STOP
BUSCLK
KBIPEn 0
1 S
KBEDGn
KBIPE0 0
1 S
KBEDG0 KBIP0
KBIPn
KBI INTERRU PT
Keyboard Interrupts (S08KBIV2)
10.3.2 KBI Pin Enable Register (KBIPE)
KBIPE contains the pin enable control bits.10.3.3 KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.7 6 5 4 3 2 1 0
R 0 0 0 0 KBF 0
KBIE KBMOD
W KBACK
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 10-3. KBIStatus and Control Register Table 10-2. KBISC Register Field Descriptions
Field Description
7:4 Unused register bits, always read 0.
3 KBF
Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF.
0 No keyboard interrupt detected.
1 Keyboard interrupt detected.
2 KBACK
Keyboard Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads as 0.
1 KBIE
Keyboard Interrupt Enable — KBIE determines whether a keyboard interrupt is requested.
0 Keyboard interrupt request not enabled.
1 Keyboard interrupt request enabled.
0 KBMOD
Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins.0Keyboard detects edges only.
1 Keyboard detects both edges and levels.
7 6 5 4 3 2 1 0
R
KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 10-4. KBI Pin Enable Register Table 10-3. KBIPE Register Field Descriptions
Field Description
7:0 KBIPEn
Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin.
0 Pin not enabled as keyboard interrupt.
1 Pin enabled as keyboard interrupt.
Keyboard Interrupts (S08KBIV2)
10.4 Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes.
The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPEn bits in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin.
Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES).
10.4.1 Edge Only Sensitivity
Synchronous logic is used to detect edges. A falling edge is detected when an enabled keyboard interrupt (KBIPEn=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next cycle.Before the first edge is detected, all enabled keyboard interrupt input signals must be at the
deasserted logic levels. After any edge is detected, all enabled keyboard interrupt input signals must return to the deasserted level before any new edge can be detected.
A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC.
10.4.2 Edge and Level Sensitivity
A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in
7 6 5 4 3 2 1 0
R
KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
W
Reset: 0 0 0 0 0 0 0 0
Figure 10-5. KBI Edge Select Register Table 10-4. KBIES Register Field Descriptions
Field Description
7:0 KBEDGn
Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin).
0 Falling edge/low level.
1 Rising edge/high level.
Keyboard Interrupts (S08KBIV2)
KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK.
10.4.3 KBI Pullup/Pulldown Resistors
The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register. If an internal resistor is enabled, the KBIES register is used to select whether the resistor is a pullup (KBEDGn = 0) or a pulldown (KBEDGn = 1).
10.4.4 KBI Initialization
When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To prevent a false interrupt request during keyboard initialization, the user must do the following:
1. Mask keyboard interrupts by clearing KBIE in KBISC.
2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES.
3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE.
4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE.
5. Write to KBACK in KBISC to clear any false interrupts.
6. Set KBIE in KBISC to enable interrupts.
Keyboard Interrupts (S08KBIV2)