Parameter Description Notes Min Typ Max Units
T2.23.1 TX_EN to RX_DV Loopback(1) 10 Mb/s internal loopback mode 2 µs
(1) Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.
3.4.2.24 RMII Transmit Timing (Slave Mode)
Parameter Description Notes Min Typ Max Units
T2.24.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.24.2 TXD[1:0], TX_EN, Data Setup to X1 rising edge 4 ns
T2.24.3 TXD[1:0], TX_EN, Data Hold from X1 rising edge 2 ns
T2.24.4 X1 Clock to PMD Output Pair Latency (100 Mb)(1) 100BASE-TX or 100BASE-FX 11 bits (1) Latency measurement is made from the X1 rising edge to the first bit of symbol.
Symbol T2.25.1
T2.25.3 T2.25.2
T2.25.4 RX_CLK
TX_CLK CLK_OUT
TXD[1:0]
TX_EN
PMD Output Pair
Valid data
3.4.2.25 RMII Transmit Timing (Master Mode)
Parameter Description Notes Min Typ Max Units
T2.25.1 RX_CLK, TX_CLK, CLK_OUT Period 50 MHz Reference Clock 20 ns
T2.25.2 TXD[1:0], TX_EN Data Setup to RX_CLK,
4 ns
TX_CLK, CLK_OUT rising edge
T2.25.3 TXD[1:0], TX_EN Data Hold from RX_CLK, 2 ns
TX_CLK, CLK_OUT rising edge
T2.25.4 RX_CLK, TX_CLK, CLK_OUT to PMD Output Pair From RX_CLK rising edge to
11 bits
Latency(1) first bit of symbol
(1) Latency measurement is made from the RX_CLK rising edge to the first bit of symbol.
Data
IDLE (J/K) Data (TR)
T2.26.4
T2.26.1 T2.26.5
T2.26.3
T2.26.2
T2.26.2 PMD Input
Pair
X1
CRS/CRS_DV
RXD[1:0]
RX_ER
3.4.2.26 RMII Receive Timing (Slave Mode)
Parameter Description Notes Min Typ Max Units
T2.26.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.26.2 RXD[1:0], CRS_DV, and RX_ER
2 14 ns
output delay from X1 rising edge(1)
T2.26.3 100BASE-TX mode 18.5
CRS ON delay(2) (3) bits
100BASE-FX mode 9
T2.26.4 100BASE-TX mode 27
CRS OFF delay(4) bits
100BASE-FX mode 17
T2.26.5 100BASE-TX mode 38
RXD[1:0] and RX_ER latency(5) (6) bits
100BASE-FX mode 27
(1) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate CRS de-assertion.
(2) Per the RMII Specification, output delays assume a 25 pF load.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).
(6) Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive datapath.
RX_CLK
3.4.2.27 RMII Receive Timing (Master Mode)
Parameter Description Notes Min Typ Max Units
T2.27.1 RX_CLK, TX_CLK, CLK_OUT 50 MHz Reference Clock 20 ns
Clock Period
T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from
CRS OFF delay(4) bits
100BASE-FX mode 17
T2.27.5 100BASE-TX mode 38
RXD[1:0] and RX_ER latency(5) bits
100BASE-FX mode 27
(1) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate CRS de-assertion.
(2) Per the RMII Specification, output delays assume a 25 pF load.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).
3.4.2.28 RX_CLK Timing (RMII Master Mode)
Parameter Description Notes Min Typ Max Units
T2.28.1 RX_CLK High Time 12 ns
T2.28.2 RX_CLK Low Time 8 ns
T2.28.3 RX_CLK Period(1) 20 ns
(1) The High Time and Low Time will add up to 20 ns.
Symbol T2.30.1
T2.30.3 T2.30.2
T2.30.4 X1
TXD[3:0]
TX_EN
PMD Output Pair
Valid data T2.29.2
CLK_OUT
T2.29.1 X1
T2.29.1
3.4.2.29 CLK_OUT Timing (RMII Slave Mode)
Parameter Description Notes Min Typ Max Units
T2.29.1 CLK_OUT High/Low Time 10 ns
T2.29.2 CLK_OUT propagation delay Relative to X1 8 ns
3.4.2.30 Single Clock MII (SCMII) Transmit Timing
Parameter Description Notes Min Typ Max Units
T2.30.1 X1 Clock Period 25 MHz Reference Clock 40 ns
T2.30.2 TXD[3:0], TX_EN Data Setup To X1 rising edge 4 ns
T2.30.3 TXD[3:0], TX_EN Data Hold From X1 rising edge 2 ns
T2.30.4 X1 Clock to PMD Output Pair
100BASE-TX or 100BASE-FX 13 bits
Latency (100 Mb)(1)
(1) Latency measurement is made from the X1 rising edge to the first bit of symbol.
T2.32.1
TX_CLK X1
Data
IDLE (J/K) Data (TR)
T2.31.4
T2.31.1 T2.31.5
T2.31.3
T2.31.2 T2.31.2
PMD Input Pair
X1
CRS/CSR_DV
RX_DV
RXD[3:0]
RX_ER
3.4.2.31 Single Clock MII (SCMII) Receive Timing
Parameter Description Notes Min Typ Max Units
T2.31.1 X1 Clock Period 25 MHz Reference Clock 40 ns
T2.31.2 RXD[3:0], RX_DV and RX_ER output
From X1 rising edge 2 18 ns
delay(1)
T2.31.3 100BASE-TX mode 19
CRS ON delay(2) (3) bits
100BASE-FX mode 9
T2.31.4 100BASE-TX mode 26
CRS OFF delay(2) (4) bits
100BASE-FX mode 16
T2.31.5 100BASE-TX mode 56
RXD[3:0] and RX_ER latency(5) bits
100BASE-FX mode 46
(1) Output delays assume a 25 pF load.
(2) CRS is asserted and de-asserted asynchronously relative to the reference clock.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).