Propagation Delays (ns)

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3-2

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AA21

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.18 0.13

0.24 0.20

0.32 0.28

0.40 0.35

0.48 0.43

AA22

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.18 0.15

0.26 0.22

0.33 0.29

0.41 0.36

0.48 0.43

AA24

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.14 0.15

0.24 0.21

0.32 0.26

0.38 0.32

0.44 0.39

AA26

Number of Equivalent Loads 1 20 40 60 80 (max)

From: Any Input To: Q

t_PLH t_PHL

0.21 0.15

0.29 0.24

0.36 0.31

0.43 0.37

0.49 0.44

Cor e Logi c

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Description

AA3x is a family of 3-input gates which perform the logical AND function.

HDL Syntax

Verilog ... AA3x inst_name (Q, A, B, C);

VHDL... inst_name: AA3x port map (Q, A, B, C);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C Q

L X X L

X L X L

X X L L

H H H H

Pin Name Equivalent Loads

AA31 AA32 AA34 AA36

A 1.0 1.0 2.0 3.0

B 1.0 1.0 2.0 3.0

C 1.0 1.0 2.0 3.0

Cell Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AA31 2.0 3.843 2.8

AA32 3.0 4.804 3.8

AA34 6.0 9.607 7.3

AA36 8.0 14.407 9.5

AA3x

A B C A B C

Q Q

Cor e Logi c

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3-4

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AA31

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.22 0.15

0.30 0.23

0.39 0.31

0.48 0.38

0.56 0.45

AA32

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.17

0.33 0.25

0.41 0.32

0.50 0.39

0.58 0.45

AA34

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.23 0.14

0.31 0.23

0.38 0.29

0.45 0.34

0.52 0.40

AA36

Number of Equivalent Loads 1 20 40 60 80 (max)

From: Any Input To: Q

t_PLH t_PHL

0.22 0.12

0.30 0.21

0.37 0.28

0.44 0.34

0.50 0.40

Cor e Logi c

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Description

AA4x is a family of 4-input gates which perform the logical AND function.

HDL Syntax

Verilog ... AA4x inst_name (Q, A, B, C, D);

VHDL... inst_name: AA4x port map (Q, A, B, C, D);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D Q

L X X X L

X L X X L

X X L X L

X X X L L

H H H H H

Pin Name

Equivalent Loads

AA41 AA42 AA44 AA46

A 1.0 1.0 3.0 3.0

B 1.0 1.0 3.0 3.0

C 1.0 1.0 3.0 3.0

D 1.0 1.0 3.0 3.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQLpd (Eq-load)

AA41 3.0 4.804 3.1

AA42 3.0 5.764 3.9

AA44 8.0 15.368 8.5

AA46 9.0 17.291 11.7

AA4x

Q Q

D C B A D C B A

Cor e Logi c

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3-6

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AA41

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.27 0.17

0.35 0.24

0.45 0.32

0.54 0.40

0.63 0.47

AA42

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.30 0.19

0.40 0.27

0.49 0.34

0.57 0.42

0.64 0.48

AA44

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.20 0.13

0.30 0.21

0.38 0.27

0.45 0.32

0.52 0.39

AA46

Number of Equivalent Loads 1 20 40 60 80 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.14

0.36 0.22

0.44 0.28

0.51 0.34

0.57 0.40

Cor e Logi c

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Description

AN1x is a family of AND-NOR circuits consisting of two 2-input AND gates into a 2-input NOR gate.

HDL Syntax

Verilog ... AN1x inst_name (Q, A, B, C, D);

VHDL... inst_name: AN1x port map (Q, A, B, C, D);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D Q

L X L X H

L X X L H

X L L X H

X L X L H

H H X X L

X X H H L

Pin Name

Equivalent Loads

AN11 AN12 AN14 AN16

A 1.0 1.0 1.0 2.0

B 1.0 1.0 1.0 2.0

C 1.0 1.0 1.0 2.0

D 1.0 1.0 1.0 2.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN11 2.0 1.923 1.8

AN12 4.0 6.724 4.6

AN14 4.0 7.684 5.9

AN16 8.0 15.367 10.9

AN1x A

C

Q

B

D

Cor e Logi c

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3-8

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN11

Number of Equivalent Loads 1 2 5 8 10 (max)

From: Any Input To: Q

t_PLH t_PHL

0.13 0.12

0.17 0.16

0.29 0.26

0.40 0.35

0.47 0.40

AN12

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.21 0.24

0.29 0.30

0.38 0.39

0.46 0.48

0.55 0.56

AN14

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.23 0.28

0.31 0.36

0.38 0.43

0.47 0.51

0.54 0.57

AN16

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.21 0.27

0.29 0.35

0.35 0.40

0.42 0.46

0.49 0.53

Cor e Logi c

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Description

AN2x is a family of AND-NOR circuits consisting of one 2-input AND gate into a 2-input NOR gate.

HDL Syntax

Verilog ... AN2x inst_name (Q, A, B, C);

VHDL... inst_name: AN2x port map (Q, A, B, C);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C Q

H H X L

X X H L

All other combinations H

Pin Name Equivalent Loads

AN21 AN22 AN24 AN26

A 1.0 1.0 1.0 2.1

B 1.0 1.0 1.0 2.0

C 1.0 1.0 1.0 1.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN21 2.0 1.539 1.6

AN22 3.0 5.764 4.7

AN24 4.0 6.724 5.6

AN26 7.0 12.487 10.7

A AN2x

B Q

C

Cor e Logi c

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3-10

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN21

Number of Equivalent Loads 1 2 5 8 10 (max)

From: Any Input To: Q

t_PLH t_PHL

0.11 0.12

0.15 0.16

0.27 0.25

0.39 0.34

0.46 0.41

AN22

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.22 0.23

0.29 0.30

0.38 0.38

0.47 0.47

0.56 0.55

AN24

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.24 0.24

0.30 0.31

0.38 0.39

0.47 0.47

0.55 0.53

AN26

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.22 0.23

0.30 0.32

0.37 0.38

0.44 0.44

0.51 0.50

Cor e Logi c

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Description

AN3x is a family of AND-NOR circuits consisting of one 2-input AND gate into a 3-input NOR gate.

HDL Syntax

Verilog ... AN3x inst_name (Q, A, B, C, D);

VHDL... inst_name: AN3x port map (Q, A, B, C, D);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D Q

L X L L H

X L L L H

H H X X L

X X H X L

X X X H L

Pin Name

Equivalent Loads

AN31 AN32 AN34 AN36

A 1.0 1.0 1.0 2.0

B 1.0 1.0 1.0 2.0

C 1.0 1.0 1.0 2.1

D 1.0 1.0 1.0 2.1

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN31 2.0 2.308 2.0

AN32 4.0 5.764 4.7

AN34 4.0 6.724 5.9

AN36 8.0 13.448 12.3

AN3x A

C B Q

D

Cor e Logi c

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3-12

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN31

Number of Equivalent Loads 1 2 4 6 8 (max)

From: Any Input To: Q

t_PLH t_PHL

0.15 0.13

0.21 0.17

0.32 0.24

0.44 0.30

0.56 0.37

AN32

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.21 0.23

0.28 0.30

0.37 0.38

0.45 0.45

0.54 0.53

AN34

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.23 0.24

0.31 0.32

0.38 0.39

0.47 0.47

0.54 0.53

AN36

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.24 0.24

0.32 0.31

0.40 0.38

0.46 0.45

0.53 0.51

Cor e Logi c

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Description

AN4x is a family of AND-NOR circuits consisting of one 3-input AND gate into a 2-input NOR gate.

HDL Syntax

Verilog ... AN4x inst_name (Q, A, B, C, D);

VHDL... inst_name: AN4x port map (Q, A, B, C, D);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D Q

H H H X L

X X X H L

All other combinations H

Pin Name

Equivalent Loads

AN41 AN42 AN44 AN46

A 1.0 1.0 1.0 2.0

B 1.0 1.0 1.0 2.0

C 1.0 1.0 1.0 2.0

D 1.0 1.0 1.0 1.0

Cell

Equivalent Gates Size And Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN41 2.0 1.540 2.1

AN42 4.0 6.724 5.6

AN44 4.0 7.684 5.8

AN46 8.0 14.408 11.4

A AN4x

Q B

D C

Cor e Logi c

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3-14

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN41

Number of Equivalent Loads 1 2 4 6 8 (max)

From: Any Input To: Q

t_PLH t_PHL

0.11 0.15

0.16 0.19

0.24 0.28

0.31 0.36

0.38 0.44

AN42

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.30

0.32 0.37

0.41 0.45

0.49 0.53

0.58 0.61

AN44

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.24 0.29

0.31 0.35

0.39 0.43

0.47 0.51

0.55 0.58

AN46

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.23 0.27

0.31 0.36

0.38 0.43

0.45 0.49

0.51 0.56

Cor e Logi c

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Description

AN5x is a family of AND-NOR circuits consisting of one 3-input AND gate and one 2-input AND gate into a 2-input NOR gate.

HDL Syntax

Verilog ... AN5x inst_name (Q, A, B, C, D, E);

VHDL... inst_name: AN5x port map (Q, A, B, C, D, E);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E Q

H H H X X L

X X X H H L

All other combinations H

Pin Name Equivalent Loads

AN52 AN54 AN56

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.1

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN52 4.0 7.685 6.0

AN54 5.0 8.647 7.0

AN56 12.0 17.291 13.6

A AN5x

D C Q

E B

Cor e Logi c

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3-16

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN52

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.30

0.32 0.36

0.41 0.45

0.49 0.53

0.57 0.61

AN54

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.29

0.33 0.37

0.40 0.44

0.48 0.52

0.55 0.59

AN56

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.24 0.28

0.31 0.36

0.38 0.43

0.45 0.49

0.52 0.56

Cor e Logi c

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Description

AN6x is a family of AND-NOR circuits consisting of two 3-input AND gates into a 2-input NOR gate.

HDL Syntax

Verilog ... AN6x inst_name (Q, A, B, C, D, E, F);

VHDL... inst_name: AN6x port map (Q, A, B, C, D, E, F);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E F Q

H H H X X X L

X X X H H H L

All other combinations H

Pin Name

Equivalent Loads

AN62 AN64 AN66

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN62 5.0 8.647 6.6

AN64 6.0 9.607 7.5

AN66 12.0 19.212 14.1

A AN6x

D C Q

F B

E

Cor e Logi c

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3-18

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN62

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.24 0.30

0.32 0.37

0.41 0.45

0.49 0.53

0.57 0.60

AN64

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.30

0.33 0.37

0.41 0.45

0.49 0.53

0.56 0.59

AN66

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.23 0.30

0.32 0.38

0.39 0.45

0.45 0.51

0.52 0.58

Cor e Logi c

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Description

AN7x is a family of AND-NOR circuits consisting of one 3-input AND gate into a 3-input NOR gate.

HDL Syntax

Verilog ... AN7x inst_name (Q, A, B, C, D, E);

VHDL... inst_name: AN7x port map (Q, A, B, C, D, E);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E Q

H H H X X L

X X X H X L

X X X X H L

All other combinations H

Pin Name

Equivalent Loads

AN72 AN74 AN76

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.1

E 1.0 1.0 2.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN72 4.0 6.726 6.1

AN74 5.0 7.686 6.7

AN76 10.0 15.370 12.5

A AN7x

D C Q

E B

Cor e Logi c

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3-20

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN72

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.30

0.32 0.36

0.41 0.45

0.49 0.53

0.57 0.61

AN74

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.25 0.30

0.32 0.37

0.40 0.45

0.48 0.52

0.55 0.59

AN76

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.23 0.27

0.32 0.37

0.41 0.43

0.48 0.49

0.56 0.54

Cor e Logi c

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Description

AN8x is a family of AND-NOR circuits consisting of two 2-input AND gates into a 3-input NOR gate.

HDL Syntax

Verilog ... AN8x inst_name (Q, A, B, C, D, E);

VHDL... inst_name: AN8x port map (Q, A, B, C, D, E);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E Q

H H X X X L

X X H H X L

X X X X H L

All other combinations H

Pin Name

Equivalent Loads

AN82 AN84 AN86

A 1.0 1.0 2.1

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN82 5.0 8.646 7.2

AN84 5.0 9.607 7.7

AN86 11.0 19.212 15.4

A AN8x

C Q

B

D

E

Cor e Logi c

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3-22

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN82

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.28 0.26

0.36 0.33

0.45 0.41

0.53 0.49

0.62 0.57

AN84

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.28 0.25

0.36 0.33

0.44 0.40

0.53 0.48

0.60 0.55

AN86

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.28 0.24

0.35 0.32

0.42 0.39

0.50 0.45

0.58 0.51

Cor e Logi c

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Description

AN9x is a family of AND-NOR circuits consisting of one 3-input AND gate and one 2-input AND gate into a 3-input NOR gate.

HDL Syntax

Verilog ... AN9x inst_name (Q, A, B, C, D, E, F);

VHDL... inst_name: AN9x port map (Q, A, B, C, D, E, F);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E F Q

H H H X X X L

X X X H H X L

X X X X X H L

All other combinations H

Pin Name Equivalent Loads

AN92 AN94 AN96

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AN92 5.0 9.607 7.1

AN94 6.0 10.567 8.5

AN96 11.0 21.133 14.9

A AN9x

D Q

C

E

F B

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3-24

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AN92

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.27 0.28

0.34 0.36

0.44 0.44

0.53 0.52

0.62 0.60

AN94

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.30 0.31

0.39 0.39

0.47 0.46

0.56 0.54

0.62 0.61

AN96

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.27 0.25

0.35 0.35

0.43 0.42

0.50 0.48

0.57 0.54

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Description

ANAx is a family of AND-NOR circuits consisting of two 3-input AND gates into a 3-input NOR gate.

HDL Syntax

Verilog ... ANAx inst_name (Q, A, B, C, D, E, F, G);

VHDL... inst_name: ANAx port map (Q, A, B, C, D, E, F, G);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E F G Q

H H H X X X X L

X X X H H H X L

X X X X X X H L

All other combinations H

Pin Name

Equivalent Loads

ANA2 ANA4 ANA6

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

G 1.0 1.0 2.0

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

ANA2 6.0 10.567 8.4

ANA4 6.0 11.527 8.8

ANA6 12.0 23.054 15.7

ANAx

A

D Q

C

F

G B

E

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3-26

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

ANA2

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.29 0.31

0.37 0.38

0.46 0.47

0.55 0.54

0.64 0.61

ANA4

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.30 0.31

0.39 0.39

0.47 0.47

0.55 0.54

0.62 0.60

ANA6

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.27 0.26

0.37 0.36

0.43 0.43

0.50 0.49

0.58 0.55

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Description

ANBx is a family of AND-NOR circuits consisting of three 2-input AND gates into a 3-input NOR gate.

HDL Syntax

Verilog ... ANBx inst_name (Q, A, B, C, D, E, F);

VHDL... inst_name: ANBx port map (Q, A, B, C, D, E, F);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E F Q

H H X X X X L

X X H H X X L

X X X X H H L

All other combinations H

Pin Name

Equivalent Loads

ANB2 ANB4 ANB6

A 1.0 1.0 2.1

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

Cell

Equivalent Gates Size And Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

ANB2 5.0 9.607 7.4

ANB4 6.0 10.567 7.4

ANB6 12.0 21.132 15.4

ANBx A

C _Q

B

D E F

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3-28

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

ANB2

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.28 0.26

0.35 0.33

0.45 0.42

0.53 0.50

0.62 0.57

ANB4

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.27 0.26

0.35 0.34

0.44 0.41

0.53 0.49

0.60 0.55

ANB6

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.28 0.26

0.38 0.34

0.44 0.40

0.51 0.46

0.59 0.51

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Description

ANCx is a family of AND-NOR circuits consisting of one 3-input AND gate and two 2-input AND gates into a 3-input NOR gate.

HDL Syntax

Verilog ... ANCx inst_name (Q, A, B, C, D, E, F, G);

VHDL... inst_name: ANCx port map (Q, A, B, C, D, E, F, G);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

A B C D E F G Q

H H H X X X X L

X X X H H X X L

X X X X X H H L

All other combinations H

Pin Name Equivalent Loads

ANC2 ANC4 ANC6

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

G 1.0 1.0 2.0

Cell

Equivalent Gates Size And Power Characteristics^a Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

ANC2 6.0 10.567 8.4

ANC4 7.0 11.528 9.3

ANC6 12.0 23.054 15.7

A ANCx

D Q

C

E

F G B

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3-30

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

ANC2

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.29 0.31

0.37 0.38

0.46 0.47

0.55 0.55

0.64 0.62

ANC4

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.30 0.30

0.39 0.38

0.47 0.46

0.56 0.54

0.63 0.60

ANC6

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.26 0.26

0.35 0.36

0.42 0.43

0.49 0.49

0.57 0.55

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Description

ANDx is a family of AND-NOR circuits consisting of two 3-input AND gates and one 2-input AND gate into a 3-input NOR gate.

HDL Syntax

Verilog ... ANDx inst_name (Q, A, B, C, D, E, F, G, H);

VHDL... inst_name: ANDx port map (Q, A, B, C, D, E, F, G, H);

Pin Loading

Logic Symbol Truth Table

A B C D E F G H Q

H H H X X X X X L

X X X H H H X X L

X X X X X X H H L

All other combinations H

Pin Name Equivalent Loads

AND2 AND4 AND6

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

G 1.0 1.0 2.0

H 1.0 1.0 2.0

A ANDx

D

Q C

F

G H B

E

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3-32

Size And Power Characteristics

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AND2 6.0 11.528 8.9

AND4 8.0 12.488 8.8

AND6 13.0 24.974 16.6

AND2

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.29 0.31

0.37 0.38

0.47 0.46

0.55 0.54

0.63 0.61

AND4

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.30 0.30

0.39 0.39

0.47 0.47

0.56 0.54

0.63 0.60

AND6

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.28 0.30

0.36 0.37

0.43 0.42

0.50 0.49

0.57 0.56

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Description

ANEx is a family of AND-NOR circuits consisting of three 3-input AND gates into a 3-input NOR gate.

HDL Syntax

Verilog ... ANEx inst_name (Q, A, B, C, D, E, F, G, H, I);

VHDL... inst_name: ANEx port map (Q, A, B, C, D, E, F, G, H, I);

Pin Loading

Logic Symbol Truth Table

A B C D E F G H I Q

H H H X X X X X X L

X X X H H H X X X L

X X X X X X H H H L

All other combinations H

Pin Name Equivalent Loads

ANE2 ANE4 ANE6

A 1.0 1.0 2.0

B 1.0 1.0 2.0

C 1.0 1.0 2.0

D 1.0 1.0 2.0

E 1.0 1.0 2.0

F 1.0 1.0 2.0

G 1.0 1.0 2.0

H 1.0 1.0 2.0

I 1.0 1.0 2.0

ANEx A

D

Q C

F G I B

E

H

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3-34

Size And Power Characteristics

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

ANE2 7.0 12.488 9.5

ANE4 8.0 13.448 10.3

ANE6 14.0 26.895 17.4

ANE2

Number of Equivalent Loads 1 4 8 12 16 (max)

From: Any Input To: Q

t_PLH t_PHL

0.29 0.31

0.37 0.38

0.47 0.46

0.55 0.54

0.64 0.62

ANE4

Number of Equivalent Loads 1 7 14 22 29 (max)

From: Any Input To: Q

t_PLH t_PHL

0.31 0.33

0.39 0.41

0.47 0.48

0.56 0.55

0.63 0.62

ANE6

Number of Equivalent Loads 1 14 27 40 54 (max)

From: Any Input To: Q

t_PLH t_PHL

0.26 0.28

0.36 0.36

0.44 0.43

0.51 0.49

0.58 0.56

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Description

AU1x is a family of combinational one-bit full adders.

HDL Syntax

Verilog ... AU1x inst_name (CO, S, A, B, CI);

VHDL... inst_name: AU1x port map (CO, S, A, B, CI);

Pin Loading

Size And Power Characteristics

Logic Symbol Truth Table

CI A B S CO

L L L L L

L L H H L

L H L H L

L H H L H

H L L H L

H L H L H

H H L L H

H H H H H

Pin Name Equivalent Loads

AU11 AU12

A 4.1 8.3

B 4.1 8.1

CI 3.1 6.2

Cell

Equivalent Gates Power Characteristics^a

a. See page 2-13 for power equation.

Static I_DD (T_J = 85°C) (nA) EQL_pd (Eq-load)

AU11 7.0 7.688 9.0

AU12 15.0 15.377 19.6

AU1x

B S A

CI CO

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3-36

Propagation Delays (ns)

Conditions: T_J = 25°C, V_DD = 5.0V, Typical Process

Delay will vary with input conditions. See page 2-15 for interconnect estimates.

AU11

Number of Equivalent Loads 1 4 8 12 16 (max)

From: A From: Cl

To: S From: CI

To: CO

Number of Equivalent Loads 1 7 14 22 29 (max)

From: A From: Cl

To: S From: CI

To: CO

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W dokumencie AMI350HXGC (Stron 38-73)