The revision history table notes changes made between the indicated revisions of the LM3S5R31 data sheet.
Table 1. Revision History
Description Revision
Date
11425
January 2012 ■ In System Control chapter:
– Clarified that an external LDO cannot be used.
– Clarified system clock requirements when the ADC module is in operation.
– Added important note to write the RCC register before the RCC2 register.
■ In Hibernation chapter:
– Changed terminology from non-volatile memory to battery-backed memory.
– Numerous clarifications, including adding a section "System Implementation".
– Clarified Hibernation module register reset conditions.
■ In Internal Memory chapter, clarified programming and use of the non-volatile registers.
■ In GPIO chapter, corrected "GPIO Pins With Non-Zero Reset Values" table and added note that if the same signal is assigned to two different GPIO port pins, the signal is assigned to the port with the lowest letter.
■ In EPI chapter:
– Clarified table "Capabilities of Host Bus 8 and Host Bus 16 Modes".
– Corrected bit and register resets forFREQ(Frequency Range) in EPI SDRAM Configuration (EPISDRAMCFG) register.
– Corrected bit and register resets forMAXWAIT(Maximum Wait) in EPI Host-Bus 8 Configuration (EPIHB8CFG) and EPI Host-Bus 16 Configuration (EPIHB16CFG) registers. Also clarified bit descriptions in these registers.
– Corrected bit definitions for theEPSZandERSZbits in the EPI Address Map (EPIADDRMAP) register.
– Corrected size of COUNT bit field in EPI Read FIFO Count (EPIRFIFOCNT) register.
■ In Timer chapter, clarified timer modes and interrupts.
■ In ADC chapter, added "ADC Input Equivalency Diagram".
■ In UART chapter, clarified interrupt behavior.
■ In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)"
and clarified behavior of transmit bits in interrupt registers.
■ In I2C chapter, corrected bit and register reset values forIDLEbit in I2C Master Control/Status (I2CMCS) register.
■ In USB chapter:
– Clarified that when the USB module is in operation, MOSC must be provided with a clock source, and the system clock must be at least 30 MHz.
– RemovedDISCONbit from Device Mode table for USB General Interrupt Status (USBIS) register.
Table 1. Revision History (continued)
Description Revision
Date
– AddedWTIDbit to USB Connect Timing (USBCONTIM) register.
– Corrected description for the USB Device RESUME Interrupt Mask (USBDRIM) register.
■ In Analog Comparators chapter, clarified internal reference programming.
■ In PWM chapter, clarified PWM Interrupt Enable (PWMINTEN) register description.
■ In Signal Tables chapter, clarifiedVDDCand LDO pin descriptions.
■ In Electrical Characteristics chapter:
– In Maximum Ratings table, deleted parameter "Input voltage for a GPIO configured as an analog input".
– In Recommended DC Operating Conditions table, corrected values for IOHparameter.
– In JTAG Characteristics, table, corrected values for parameters "TCK clock Low time" and "TCK clock High time".
– In LDO Regulator Characteristics table, added clarifying footnote to CLDOparameter.
– In System Clock Characteristics with ADC Operation table, added clarifying footnote to Fsysadc parameter.
– Added "System Clock Characteristics with USB Operation" table.
– In Sleep Modes AC Characteristics table, split parameter "Time to wake from interrupt" into sleep mode and deep-sleep mode parameters.
– In SSI Characteristics table, corrected value for parameter "SSIClk cycle time".
– Deleted erroneously included Ethernet Controller tables, since this part does not have Ethernet.
– In Analog Comparator Characteristics table, added parameter "Input voltage range" and corrected values for parameter "Input common mode voltage range".
– In Analog Comparator Voltage Reference Characteristics table, corrected values for absolute accuracy parameters.
– Deleted table "USB Controller DC Characteristics".
– In Nominal Power Consumption table, added parameter for sleep mode.
– In Maximum Current Consumption section, changed reference value for MOSC and temperature in tables that follow.
– Deleted table "External VDDC Source Current Specifications".
■ Additional minor data sheet clarifications and corrections.
Table 1. Revision History (continued)
Description Revision
Date
■ Corrected "Reset Sources" table.
■ Added missingPICAL(PIOSC Calibrate) bit to DC4 register.
■ Added Important Note that RCC register must be written before RCC2 register.
■ Added a note that all GPIO signals are 5-V tolerant when configured as inputs except forPB0and PB1, which are limited to 3.6 V.
■ Note that the state of theHSEbit in the UARTCTL register has no effect on clock generation in ISO 7816 smart card mode (when theSMARTbit in the UARTCTL register is set).
■ Corrected LIN Mode bit names in UART Interrupt Clear (UARTICR) register.
■ Corrected pin number forRSTin table "Connections for Unused Signals" (other pin tables were correct).
■ In the "Operating Characteristics" chapter:
– In the "Thermal Characteristics" table, the Thermal resistance value was changed.
– In the "ESD Absolute Maximum Ratings" table, the VESDCDMparameter was changed and the VESDMMparameter was deleted.
■ The "Electrical Characteristics" chapter was reorganized by module. In addition, some of the Recommended DC Operating Conditions, LDO Regulator, Clock, GPIO, EPI, Hibernation Module, ADC, and SSI characteristics were finalized.
■ Added missing ordering table.
■ Additional minor data sheet clarifications and corrections.
9970 July 2011
Table 1. Revision History (continued)
Description Revision
Date
■ Clarified "Reset Control" section in the "System Control" chapter.
■ Corrected USB PLL speed in "Main Clock Tree" diagram.
■ Clarified Hibernation module initialization and configuration.
■ Corrected reset value for DMA Channel Wait-on-Request Status (DMAWAITSTAT) register.
■ Corrected "GPIO Pins With Non-Zero Reset Values" table.
■ Added diagram "Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual CSn"
to EPI chapter.
■ Clarified that that the timer reload only happens in periodic mode.
■ Clarified that only bit 0 in the Watchdog Control (WDTCTL) register is protected from writes once set.
■ Added "Sample Averaging Example" diagram to ADC chapter.
■ Corrected "SSI Timing for SPI Frame Format" figure.
■ In "Electrical Characteristics" chapter:
– Deleted TPORMINparameter from "Power Characteristics" table, and deleted corresponding diagram.
– Corrected tRDYSUparameter in "EPI General-Purpose Interface Characteristics" table and
"General-Purpose Mode iRDY Timing" diagram.
– Added tADCSAMPsample time parameter to "ADC Characteristics" table.
■ Additional minor data sheet clarifications and corrections.
9538 March 2011
■ Clarified Main Oscillator verification circuit sequence.
■ Added note that there must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed.
■ Added "Example Schematic for Muxed Host-Bus 16 Mode" figure to External Peripheral Interface (EPI) chapter.
■ Corrected reset ofDevice Mode (DEVMOD)bitfield in USB General-Purpose Control and Status (USBGPCS) register.
■ Clarified initialization and configuration procedure in "Analog Comparators" chapter.
■ In Electrical Characteristics chapter:
– Added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (VNONparameter in Maximum Ratings table).
– Replaced Preliminary Current Consumption Specifications with Nominal Power Consumption, Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections.
– Clarified Reset, and Power and Brown-out Characteristics and added a new specification for powering down before powering back up.
– Added characteristics required when using an external regulator to provide power for VDDC.
■ Additional minor data sheet clarifications and corrections.
9161 January 2011
Table 1. Revision History (continued)
Description Revision
Date
■ Information on Advanced Encryption Standard (AES) cryptography tables and Cyclic Redundancy Check (CRC) error detection functionality was inadvertently omitted from some datasheets. This has been added.
■ In APINT register, changed bit name fromSYSRESETREQtoSYSRESREQ.
■ AddedDEBUG(Debug Priority) bit field to SYSPRI3 register.
■ Clarified Flash memory caution.
■ Restructured the General-Purpose Timer chapter to combine duplicated text.
■ Combined High and Low bit fields in GPTMTAILR, GPTMTAMATCHR, GPTMTAR, GPTMTAV, GPTMTBILR, GPTMTAMATCHR, GPTMTBR and GPTMTBV registers for compatibility with future releases.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added SSI master clock restriction that SSIClk cannot be faster than 25 MHz.
■ Changed I2C master and slave register base addresses and offsets to be relative to I2C module base, so register base and offsets were changed for all I2C slave registers.
■ In Electrical Characteristics chapter:
– Added single-ended clock source input voltage values to "Recommended DC Operating Conditions" table.
– Deleted Oscillation mode value from "MOSC Oscillator Input Characteristics" table.
– Added TVDD2_3supply voltage parameter to "Reset Characteristics" table.
– Added "Power-On Reset and Voltage Parameters" timing diagram.
– Added tVDDRISE_HIBsupply voltage parameter to "Hibernation Module AC Characteristics" table.
– Added "VDD Ramp when Waking from Hibernation" timing diagram.
– Added tALEADDparameter to "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" table.
– Added "Host-Bus 8/16 Mode Muxed Read Timing" and "Host-Bus 8/16 Mode Muxed Write Timing" timing diagrams.
8832 December 2010
Table 1. Revision History (continued)
Description Revision
Date
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was added, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare®names: the Cortex-M3 Interrupt Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register.
■ In the System Control chapter:
– Corrected Reset Sources table (see Table 5-3 on page 195).
– Added section "Special Considerations for Reset."
■ In the Hibernation Module chapter, added section "Special Considerations When Using a 4.194304-MHz Crystal".
■ In the Internal Memory chapter:
– Added clarification of instruction execution during Flash operations.
– Deleted ROM Version (RMVER) register as it is not used.
■ Modified Figure 9-1 on page 428 and Figure 9-2 on page 429 to clarify operation of the GPIO inputs when used as an alternate function.
■ CorrectedGPIOAMSELbit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits wide, bits[7:0].
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In CAN chapter, clarified CAN bit timing examples.
■ In Operating Characteristics chapter, corrected Thermal resistance (junction to ambient) value to 32.
■ In Electrical Characteristics chapter:
– Added "Input voltage for a GPIO configured as an analog input" value to Table 26-1 on page 1196.
– AddedILKGparameter (GPIO input leakage current) to Table 26-21 on page 1206.
– Corrected Nom values forIHIB_NORTCandIHIB_RTCin Table 26-38 on page 1219.
– Corrected reset timing in Table 26-5 on page 1200.
– Corrected values fortWAKE_TO_HIBin Table 26-19 on page 1205.
– Specified Max value forVREFAin Table 26-27 on page 1214.
– Corrected values fortCLKRF(SSIClkrise/fall time) in Table 26-29 on page 1214.
– Added I2C Characteristics table (see Table 26-30 on page 1216).
■ Added dimensions for Tray and Tape and Reel shipping mediums.
7794 September 2010
■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
7413 June 2010
Table 1. Revision History (continued)
Description Revision
Date
■ Changed memory map ending address for EPI0 mapped peripheral and RAM from 0xCFFF.FFFF to 0xDFFF.FFFF.
■ Removed 4.194304-MHz crystal as a source for the system clock and PLL.
■ Summarized ROM contents descriptions in the "Internal Memory" chapter and removed various ROM appendices.
■ Clarified DMA channel terminology: changed name of DMA Channel Alternate Select (DMACHALT) register to DMA Channel Assignment (DMACHASGN) register, changedCHALTbit field toCHASGN, and changed terminology from primary and alternate channels to primary and secondary channels.
■ Clarified EPI Main Baud Rate (EPIBAUD) equation.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Electrical Characteristics" chapter:
– In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time.
– Clarified figure "SDRAM Initialization and Load Mode Register Timing".
– Added BSEL0n/BSEL1n to EPI timing diagrams.
7299 June 2010
■ Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21, LM3S9781, and LM3S9B81.
■ Additional minor data sheet clarifications and corrections.
7164 May 2010
■ Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based on number of possible pin assignments. This table can be used to plan how to configure the pins for a particular functionality.
■ Additional minor data sheet clarifications and corrections.
7101 May 2010
■ Corrected reset for EPIHB8CFG, EPI_HB16CFG and EPIGPCFG registers.
■ ExtendedTBRLbit field in GPTMTBR register.
■ AddedDISCONbit to Device Mode table for USBIE register
■ Additional minor data sheet clarifications and corrections.
6983 March 2010
■ Renamed the USER_DBG register to the BOOTCFG register in the Internal Memory chapter. Added information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset.
■ Added three figures to the ADC chapter on sample phase control.
■ Clarified configuration ofUSB0VBUSandUSB0IDin OTG mode.
6912 March 2010
Table 1. Revision History (continued)
Description Revision
Date
■ Added 108-ball BGA package.
■ In "System Control" chapter:
– Clarified functional description for external reset and brown-out reset.
– Clarified Debug Access Port operation after Sleep modes.
– Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register.
■ In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section on interrupts to the Flash memory description.
■ In "External Peripheral Interface" chapter:
– Added clarification about byte selects and dual chip selects.
– Added timing diagrams for continuous-read mode (formerly SRAM mode).
– Corrected reset values of EPI Write FIFO Count (EPIWFIFOCNT) and EPI Raw Interrupt Status (EPIRIS) registers.
■ Added clarification about timer operating modes and added register descriptions for the GPTM Timer n Prescale Match (GPTMTnPMR) registers.
■ Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value (GPTMTBV) registers.
■ Corrected the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers.
■ Added ADC Sample Phase Control (ADCSPC) register at offset 0x24.
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed field width to 7 bits.
■ In the "Controller Area Network" chapter, added clarification about reading from the CAN FIFO buffer.
■ AddedSession Disconnect (DISCON)bit to the USB General Interrupt Status (USBIS) and USB Interrupt Enable (USBIE) registers.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table – Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) – In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time – Added table entry for VDD3ON power consumption to Table 26-38 on page 1219.
■ Added additional DriverLib functions to appendix.
6790 February 2010
Table 1. Revision History (continued)
Description Revision
Date
■ Released new 1000, 3000, 5000 and 9000 series Stellaris®devices.
■ The IDCODE value was corrected to be 0x4BA0.0477.
■ Clarified that theNMISETbit in the ICSR register in the NVIC is also a source for NMI.
■ Clarified the use of the LDO.
■ To clarify clock operation, reorganized clocking section, changed theUSEFRACTbit to theDIV400 bit and theFRACTbit to theSYSDIV2LSBbit in the RCC2 register, added tables, and rewrote descriptions.
■ Corrected bit description of theDSDIVORIDEfield in the DSLPCLKCFG register.
■ Removed the DSFLASHCFG register at System Control offset 0x14C as it does not function correctly.
■ Removed theMAXADC1SPDandMAXADC0SPDfields from the DCGC0 as they have no function in deep-sleep mode.
■ Corrected address offsets for the Flash Write Buffer (FWBn) registers.
■ Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent power cycling when hibernation is not used.
■ Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions.
■ Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly.
■ Corrected alternate channel assignments for the µDMA controller.
■ Major improvements to the EPI chapter.
■ EPISDRAMCFG2 register was deleted as its function is not needed.
■ Clarified CAN bit timing and corrected examples.
■ Clarified PWM source for ADC triggering
■ CorrectedADDRfield in the USBTXFIFOADD register to be 9 bits instead of 13 bits.
■ Changed SSI set up and hold times to be expressed in system clocks, not ns.
■ Updated Electrical Characteristics chapter with latest data. Changes were made to Hibernation, ADC and EPI content.
■ Additional minor data sheet clarifications and corrections.
6458 October 2009
Table 1. Revision History (continued)
Description Revision
Date
■ Added "Non-Blocking Read Cycle", "Normal Read Cycle", and "Write Cycle" sections to EPI chapter.
■ Corrected values forMAXADC0SPDandMAXADC1SPDbits in DC1, RCGC0, SCGC0, and DCGC0 registers.
■ Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)".
■ ChangedHIBpin from type TTL to type OD.
■ Made a number of corrections to the Electrical Characteristics chapter:
– Deleted VBATand VREFAparameters from and added footnotes to Recommended DC Operating Conditions table.
– Modified Hibernation Module DC Characteristics table.
– Deleted Nominal and Maximum Current Specifications section.
– Modified EPI SDRAM Characteristics table:
• Changed tEPIRto tSDRAMRand deleted values for 2-mA and 4-mA drive.
• Changed tEPIFto tSDRAMFand deleted values for 2-mA and 4-mA drive.
– Changed values for tCOV, tCOI, and tCOTparameters in EPI SDRAM Interface Characteristics table.
– Deleted SDRAM Read Command Timing, SDRAM Write Command Timing, SDRAM Write Burst Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and replaced with SDRAM Read Timing and SDRAM Write Timing figures.
– Modified Host-Bus 8/16 Mode Write Timing figure.
– Modified General-Purpose Mode Read and Write Timing figure.
– Modified values for tDVand tDIparameters, and deleted tODparameter from EPI General-Purpose Interface Characteristics figure.
– Major changes to ADC Characteristics tables, including adding additonal tables and diagram.
■ Added missing ROM_I2SIntStatus function to ROM DriverLib Functions appendix.
■ Corrected ordering part numbers.
■ Additional minor data sheet clarifications and corrections.
5930 July 2009
Table 1. Revision History (continued)
Description Revision
Date
■ In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset Sources" section.
■ Added missing comparator output pin bits to DC3 register; reset value changed as well.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0 registers.
■ In Request Type Support table in DMA chapter, corrected general-purpose timer row.
■ In General-Purpose Timers chapter, clarified DMA operation.
■ Added table "Preliminary Current Consumption" to Characteristics chapter.
■ Corrected Nom and Max values in "Hibernation Detailed Current Specifications" table.
■ Corrected Nom and Max values in EPI Characteristics table.
■ Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" and figure "Host-Bus 8/16 Mode Read Timing".
■ Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table.
■ Updated ROM DriverLib appendix with RevC0 functions.
■ Updated part ordering numbers.
■ Additional minor data sheet clarifications and corrections.
5779 June 2009
Started tracking revision history.
5285 May 2009