Special Bus Cycles

The AMD-K6 processor drives special bus cycles that include stop grant, flush acknowledge, cache writeback invalidation, halt, cache invalidation, and shutdown cycles. During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and A[31:3] are driven to differentiate among the special cycles, as shown in Table 24. The system logic must return BRDY# in response to all processor special cycles.

Basic Special Bus Cycle

Figure 62 on page 159 shows a basic special bus cycle. The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same clock edge that it asserts ADS#. In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (See Table 24). A halt special cycle is generated after the processor executes the HLT instruction.

If the processor samples FLUSH# asserted, it writes back any data cache lines that are in the modified state and invalidates all lines in the instruction and data cache. The processor then drives a flush acknowledge special cycle.

If the processor executes a WBINVD instruction, it drives a wr iteback s pecial cy cle after the proces sor com plete s invalidating and writing back the cache lines.

Table 24. Encodings For Special Bus Cycles

BE[7:0]# A[4:3]* Special Bus Cycle Cause

FBh 10b Stop Grant STPCLK# sampled asserted

EFh 00b Flush Acknowledge FLUSH# sampled asserted

F7h 00b Writeback WBINVD instruction

FBh 00b Halt HLT instruction

FDh 00b Flush INVD,WBINVD instruction

FEh 00b Shutdown Triple fault

Note:

* A[31:5] = 0

Figure 62. Basic Special Bus Cycle (Halt Cycle)

Halt Cycle

A[4:3] = 00b FBh

CLK A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

BRDY#

Shutdown Cycle In Figure 63, a shutdown (triple fault) occurs in the first half of the waveform, and a shutdown special cycle follows in the second half. The processor enters shutdown when an interrupt or exception occurs during the handling of a double fault (INT 8), which amounts to a triple fault. When the processor encounters a triple fault, it stops its activity on the bus and generates the shutdown special bus cycle (BE[7:0]# = FEh).

The system logic must assert NMI, INIT, RESET, or SMI# to get the processor out of the shutdown state.

Figure 63. Shutdown Cycle

Shutdown Occurs

(Triple Fault) Shutdown Special Cycle CLK

A[31:3]

BE[7:0]#

ADS#

LOCK#

M/IO#

D/C#

W/R#

D[63:0]

KEN#

BRDY#

A[4:3] = 00b FEh

Stop Grant and Stop Clock States

Figure 64 on page 162 and Figure 65 on page 163 show the processor transition from normal execution to the Stop Grant state, then to the Stop Clock state, back to the Stop Grant state, and finally back to normal execution. The series of transitions begins when the processor samples STPCLK# asserted. On recognizing a STPCLK# interrupt at the next instruction retirement boundary, the processor performs the following actions, in the order shown:

1. Its instruction pipelines are flushed

2. All pending and in-progress bus cycles are completed

3. The STPCLK# assertion is acknowledged by executing a Stop Grant special bus cycle

4. Its internal clock is stopped after BRDY# of the Stop Grant special bus cycle is sampled asserted and after EWBE# is sampled asserted

5. The Stop Clock state is entered if the system logic stops the bus clock CLK (optional)

STPCLK# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary.

The system logic drives the signal either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. STPCLK#

must remain asserted until recognized, which is indicated by the completion of the Stop Grant special cycle.

Figure 64. Stop Grant and Stop Clock Modes, Part 1

STPCLK# Sampled Asserted Stop Grant Special Cycle CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

CACHE#

STPCLK#

D[63:0]

KEN#

BRDY#

Stop Clock

A[4:3] = 10b FBh

Figure 65. Stop Grant and Stop Clock Modes, Part 2 Stop Grant State

(Re-entered after PLL stabilization)

STPCLK# Sampled Normal Stop Clock

CLK A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

CACHE#

STPCLK#

D[63:0]

KEN#

BRDY#

Negated

INIT-Initiated Transition from Protected Mode to Real Mode

INIT is typically asserted in response to a BIOS interrupt that writes to an I/O port. This interrupt is often in response to a Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar to port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 80286 software that must return to Real mode after accessing extended memory in Protected mode.

The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFF0h—the same instruction execution starting point use d afte r R ESET. Unlike R ESET, the processo r preserves the contents of its caches, the floating-point state, the MMX state, Model-Specific Registers (MSRs), the CD and NW bits of the CR0 register, the time stamp counter, and other specific internal resources.

Figure 66 on page 165 shows an example in which the operating system writes to an I/O port, causing the system logic to assert INI T. The sampling of IN IT asserted starts an extended microcode sequence that terminates with a code fetch from FFFF_FFF0h, the reset location. INIT is sampled on every clock edge but is not recognized until the next instruction boundary.

During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY# is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.

Figure 66. INIT-Initiated Transition from Protected Mode to Real Mode

Code Fetch

FFFF_FFF0 INIT Sampled Asserted

CLK A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

D[63:0]

KEN#

BRDY#

INIT