Timer Outputs

P_INHL P_INHL P_IN

P_OUTHL P_OUTHL

P_OUT

Delay from SCK high to SC2 (wl) high - Master⁵ t_TFSWHM -1.0 — 1.0 ns Delay from SC0 high to SC1 (bl) high - Master⁵ t_RFSBHM -1.0 — 1.0 ns Delay from SC0 high to SC1 (wl) high - Master⁵ t_RFSWHM -1.0 — 1.0 ns Delay from SCK high to SC2 (bl) low - Master⁵ t_TFSBLM -1.0 — 1.0 ns Delay from SCK high to SC2 (wl) low - Master⁵ t_TFSWLM -1.0 — 1.0 ns Delay from SC0 high to SC1 (bl) low - Master⁵ t_RFSBLM -1.0 — 1.0 ns Delay from SC0 high to SC1 (wl) low - Master⁵ t_RFSWLM -1.0 — 1.0 ns SCK high to STD enable from high impedance - Master t_TXEM -0.1 — 2 ns

SCK high to STD valid - Master t_TXVM -0.1 — 2 ns

SCK high to STD not valid - Master t_TXNVM -0.1 — — ns

SCK high to STD high impedance - Master t_TXHIM -4 — 0 ns

SRD Setup time before SC0 low - Master t_SM 4 — — ns

SRD Hold time after SC0 low - Master t_HM 4 — — ns

Synchronous Operation (in addition to standard internal clock parameters)

SRD Setup time before SCK low - Master t_TSM 4 — — ns

SRD Hold time after SCK low - Master t_THM 4 — — ns

1. Master mode is internally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.

3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures.

4. 50 percent duty cycle

5. bl = bit length; wl = word length

Figure 4-29 Master Mode Timing Diagram

Table 4-12 ESSI Slave Mode

¹

Switching Characteristics

Operating Conditions: V_SS = V_SSIO = V_SSA = 0 V, V_DD = 1.62-1.98V, V_DDIO = V_DDA = 3.0–3.6V, T_A = –40° to +120°C, C_L ≤ 50pF, f_op = 120MHz

Parameter Symbol Min Typ Max Units

SCK frequency fs — — 15² MHz

SCK period³ t_SCKW 66.7 — — ns

SCK high time t_SCKH 33.4⁴ — — ns

SCK low time t_SCKL 33.4⁴ — — ns

t_THM t_TSM

t_HM t_SM

t_RFSWLM t_RFSWHM

t_RFBLM t_RFSBHM

t_TXHIM t_TXNVM

t_TXVM t_TXEM

t_TFSWLM t_TFSWHM

t_TFSBLM t_TFSBHM

t_SCKL

First Bit Last Bit

SCK output

SC2 (bl) output

SC2 (wl) output

STD

SC0 output

SC1 (bl) output

SC1 (wl) output

SRD

Delay from SCK high to SC2 (bl) high - Slave⁵ t_TFSBHS -1 — 29 ns

Delay from SCK high to SC2 (wl) high - Slave⁵ t_TFSWHS -1 — 29 ns

Delay from SC0 high to SC1 (bl) high - Slave⁵ t_RFSBHS -1 — 29 ns

Delay from SC0 high to SC1 (wl) high - Slave⁵ t_RFSWHS -1 — 29 ns

Delay from SCK high to SC2 (bl) low - Slave⁵ t_TFSBLS -29 — 29 ns

Delay from SCK high to SC2 (wl) low - Slave⁵ t_TFSWLS -29 — 29 ns

Delay from SC0 high to SC1 (bl) low - Slave⁵ t_RFSBLS -29 — 29 ns

Delay from SC0 high to SC1 (wl) low - Slave⁵ t_RFSWLS -29 — 29 ns

SCK high to STD enable from high impedance - Slave t_TXES — — 15 ns

SCK high to STD valid - Slave t_TXVS 4 — 15 ns

SC2 high to STD enable from high impedance (first bit) - Slave t_FTXES 4 — 15 ns

SC2 high to STD valid (first bit) - Slave t_FTXVS 4 — 15 ns

SCK high to STD not valid - Slave t_TXNVS 4 — 15 ns

SCK high to STD high impedance - Slave t_TXHIS 4 — 15 ns

SRD Setup time before SC0 low - Slave t_SS 4 — — ns

SRD Hold time after SC0 low - Slave t_HS 4 — — ns

Synchronous Operation (in addition to standard external clock parameters)

SRD Setup time before SCK low - Slave t_TSS 4 — — ns

SRD Hold time after SCK low - Slave t_THS 4 — — ns

1. Slave mode is externally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.

3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures.

4. 50 percent duty cycle

5. bl = bit length; wl = word length

Parameter Symbol Min Typ Max Units

Figure 4-30 Slave Mode Clock Timing

t_THS t_TSS

t_HS t_SS

t_RFSWLS t_RFSWHS

t_RFBLS t_RFSBHS

t_TXHIS t_TXNVS

t_FTXVS t_TXVS

t_FTXES

t_TXES

t_TFSWLS t_TFSWHS

t_TFSBLS t_TFSBHS

SCKL SCKH

First Bit Last Bit

SCK input

SC2 (bl) input

SC2 (wl) input

STD

SC0 input

SC1 (bl) input

SC1 (wl) input

SRD

Figure 4-31 RXD Pulse Width

Figure 4-32 TXD Pulse Width Table 4-13 SCI Timing

Operating Conditions: V_SS = V_SSIO = V_SSA = 0 V, V_DD = 1.62-1.98V, V_DDIO = V_DDA = 3.0–3.6V, T_A = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit

Baud Rate¹

1. f_MAX is the frequency of operation of the system clock in MHz.

BR — (f_MAX)/(32) Mbps

RXD² Pulse Width

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD_PW 0.965/BR 1.04/BR ns

TXD³ Pulse Width

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

TXD_PW 0.965/BR 1.04/BR ns

RXD SCI receive data pin

(Input) ^RXDPW

SCI receiveTXD data pin

(Input) ^TXDPW

Figure 4-33 Test Clock Input Timing Diagram Table 4-14 JTAG Timing

^{1, 3}

Operating Conditions: V_SS = V_SSIO = V_SSA = 0 V, V_DD = 1.62-1.98V, V_DDIO = V_DDA = 3.0–3.6V, T_A = –40° to +120°C, C_L ≤ 50pF, f_op = 120MHz

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation, T = 8.33ns.

Characteristic Symbol Min Max Unit

TCK frequency of operation²

2. TCK frequency of operation must be less than 1/4 the processor rate.

3. Parameters listed are guaranteed by design.

f_OP DC 30 MHz

TCK cycle time t_CY 33.3 — ns

TCK clock pulse width t_PW 16.6 — ns

TMS, TDI data setup time t_DS 3 — ns

TMS, TDI data hold time t_DH 3 — ns

TCK low to TDO data valid t_DV — 12 ns

TCK low to TDO tri-state t_TS — 10 ns

TRST assertion time t_TRST 35 — ns

DE assertion time t_DE 4T — ns

(Input)TCK

V_M

V_IL

V_M = V_IL + (V_IH – V_IL)/2

V_M V_IH

t_PW t_PW

t_CY

Figure 4-34 Test Access Port Timing Diagram

Figure 4-35 TRST Timing Diagram

Figure 4-36 Enhanced OnCE—Debug Event

Input Data Valid

Output Data Valid TDI

(Input)

(Output)TDO

(OutputTDO) TMS

t_TS t_DV

TRST (Input)

t_TRST

DE

t_DE

Figure 4-37 GPIO Timing Table 4-15 GPIO Timing

^{1, 2}

Operating Conditions: V_SS = V_SSIO = V_SSA = 0 V, V_DD = 1.62-1.98V, V_DDIO = V_DDA = 3.0–3.6V, T_A = –40° to +120°C, C_L ≤ 50pF, f_op = 120MHz

1. In the formulas listed, T = clock cycle. For f_op = 120MHz operation and fipb = 60MHz, T = 8.33ns 2. Parameters listed are guaranteed by design.

Characteristic Symbol Min Max Unit

GPIO input period P_IN 2T + 3 — ns

GPIO input high/low period P_INHL 1T + 3 — ns

GPIO output period P_OUT 2T - 3 — ns

GPIO output high/low period P_OUTHL 1T - 3 — ns

GPIO Inputs

GPIO Outputs

P_INHL P_INHL P_IN

P_OUTHL P_OUTHL

P_OUT

5.1 Package and Pin-Out Information 56853

W dokumencie 56858 (Stron 43-52)