VCC2DET (V CC2 Detect)

Output

Summary VCC2DET is internally tied to V_SS (logic level 0) to indicate to the system logic that it must supply the specified dual-voltage requirements to the V_CC2 and V_CC3 pins. The V_CC2 pins supply voltage to the processor core, independent of the voltage supplied to the I/O buffers on the V_CC3 pins. Upon sampling VCC2DET Low, system logic should sample VCC2H/L# to identify core voltage requirements.

Driven VCC2DET always equals 0 and is never floated — even during the Tri-State Test mode.

4.52 VCC2H/L# (V

High/Low)

Output

Summary VCC2H/L# is internally tied to V_SS (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the V_CC2 pins. The V_CC2 pins supply voltage to the

samples VCC2H/L# should design a weak pullup resistor for this signal.

4.53 W/R# (Write/Read)

Output

Summary The processor drives W/R# to indicate whether it is performing a write or a read cycle on the bus. In addition, W/R# is used to define other bus cycles, including interrupt acknowledge and special cycles. See Table 23 on page 126 for more details.

Driven and Floated W/R# is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. W/R# is driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles.

W/R# is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD.

Table 17. Output Pin Float Conditions

Name Floated At: Note

VCC2DET Always Driven *

VCC2H/L# Always Driven *

Note:

* All outputs except VCC2DET, VCC2H/L#, and TDO float during the Tri-State Test mode.

4.54 WB/WT# (Writeback or Writethrough)

Input

Summary WB/WT#, together with PWT, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines.

If WB/WT# = 0 or PWT = 1 during a cacheable read miss or write hit to a shared cache line, the accessed line is cached in the shared state. This is referred to as the writethrough state because all write cycles to this cache line are driven externally on the bus.

If WB/WT# = 1 and PWT = 0 during a cacheable read miss or a write hit to a shared cache line, the accessed line is cached in the exclusive state. Subsequent write hits to the same line cause its state to transition from exclusive to modified. This is referred to as the writeback state because the L1 data cache and the L2 cache can contain modified cache lines that are subject to be written back—referred to as a writeback cycle—as the result of an inquire cycle, an internal snoop, a flush operation, or the WBINVD instruction.

Sampled WB/WT# is sampled on the clock edge that the first BRDY# or NA# of a bus cycle is sampled asserted. If the cycle is a burst read, WB/WT# is ignored during the last three assertions of B R DY # . W B / W T # i s s a m p l e d d u r i n g m e m o ry re a d a n d non-writeback write cycles and is ignored during all other types of cycles.

Table 18. Input Pin Types

Name Type Note Name Type Note

A20M# Asynchronous 1 IGNNE# Asynchronous 1

AHOLD Synchronous INIT Asynchronous 2

BF[2:0] Synchronous 4 INTR Asynchronous 1

BOFF# Synchronous INV Synchronous

BRDY# Synchronous KEN# Synchronous

BRDYC# Synchronous NA# Synchronous

CLK Clock NMI Asynchronous 2

EADS# Synchronous RESET Asynchronous 5, 6

EWBE# Synchronous 7 SMI# Asynchronous 2

FLUSH# Asynchronous 2, 3 STPCLK# Asynchronous 1

HOLD Synchronous WB/WT# Synchronous

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.

3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sam-pled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of RESET.

4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.

5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V_CC reach specification before it is negated.

6. During a warm reset, while CLK and V_CC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation.

7. On the AMD-K6-III processor, if EFER[3] is set to 1, then EWBE# is ignored by the processor.

Table 19. Output Pin Float Conditions

Name Floated At: (Note 1) Note Name Floated At: (Note 1) Note

A[4:3] HLDA, AHOLD, BOFF# 2, 3 HLDA Always Driven

ADS# HLDA, BOFF# 2 LOCK# HLDA, BOFF# 2

ADSC# HLDA, BOFF# 2 M/IO# HLDA, BOFF# 2

APCHK# Always Driven PCD HLDA, BOFF# 2

BE[7:0]# HLDA, BOFF# 2 PCHK# Always Driven

BREQ Always Driven PWT HLDA, BOFF# 2

CACHE# HLDA, BOFF# 2 SCYC HLDA, BOFF# 2

D/C# HLDA, BOFF# 2 SMIACT# Always Driven

FERR# Always Driven VCC2DET Always Driven

HIT# Always Driven VCC2H/L# Always Driven

HITM# Always Driven W/R# HLDA, BOFF# 2

Notes:

1. All outputs except VCC2DET, VCC2H/L#, and TDO float during the Tri-State Test mode.

2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.

3. Floated off the clock edge that AHOLD is sampled asserted.

Table 20. Input/Output Pin Float Conditions

Name Floated At: (Note 1) Note

A[31:5] HLDA, AHOLD, BOFF# 2,3

AP HLDA, AHOLD, BOFF# 2,3

D[63:0] HLDA, BOFF# 2

DP[7:0] HLDA, BOFF# 2

Notes:

1. All outputs except VCC2DET and TDO float during the Tri-State Test mode.

2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.

3. Floated off the clock edge that AHOLD is sampled asserted.

Table 22. Bus Cycle Definition

Bus Cycle Initiated Generated by the Processor Generated by the System

M/IO# D/C# W/R# CACHE# KEN#

Code Read, L1 Instruction Cache and L2 Cache Line Fill 1 0 0 0 0

Code Read, Noncacheable 1 0 0 1 x

Code Read, Noncacheable 1 0 0 x 1

Encoding for Special Cycle 0 0 1 1 x

Interrupt Acknowledge 0 0 0 1 x

I/O Read 0 1 0 1 x

I/O Write 0 1 1 1 x

Memory Read, L1 Data Cache and L2 Cache Line Fill 1 1 0 0 0

Memory Read, Noncacheable 1 1 0 1 x

Memory Read, Noncacheable 1 1 0 x 1

Memory Write, L1 Data Cache or L2 Cache Writeback 1 1 1 0 x

Memory Write, Noncacheable 1 1 1 1 x

Note:

x means “don’t care”

Table 23. Special Cycles Special Cycle

A4 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# M/IO# D/C# W/R# CACHE# KEN#

Stop Grant 1 1 1 1 1 1 0 1 1 0 0 1 1 x

Flush Acknowledge

(FLUSH# sampled asserted) 0 1 1 1 0 1 1 1 1 0 0 1 1 x

Writeback

(WBINVD instruction) 0 1 1 1 1 0 1 1 1 0 0 1 1 x

Halt 0 1 1 1 1 1 0 1 1 0 0 1 1 x

Flush (INVD, WBINVD

instruction) 0 1 1 1 1 1 1 0 1 0 0 1 1 x

Shutdown 0 1 1 1 1 1 1 1 0 0 0 1 1 x

Note:

x means “don’t care”