ADS58B18

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www.ti.com SBAS487D–NOVEMBER 2009–REVISED JANUARY 2011

11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer

Check for Samples:ADS58B18,ADS58B19

1

FEATURES DESCRIPTION

23• ADS58B18: 11-Bit, 200MSPS The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC)

• ADS58B19: 9-Bit, 250MSPS

family that features integrated analog buffers and

• Integrated High-Impedance Analog Input

SNRBoost technology. The ADS58B18 and Buffer

ADS58B19 are 11-bit and 9-bit ADCs with sampling

• Ultralow Power: rates up to 200MSPS and 250MSPS, respectively.

Innovative design techniques are used to achieve – Analog Power: 258mW at 200MSPS

high dynamic performance while consuming – I/O Power: 69mW (DDR LVDS, low LVDS

extremely low power. The analog input pins have swing)

buffers with constant performance and input

• High Dynamic Performance: impedance across a wide frequency range. This architecture makes these parts well-suited for – ADS58B18: 66dBFS SNR and 81dBc SFDR

multi-carrier, wide bandwidth communications at 150MHz

applications such as PA linearization.

– ADS58B19: 55.7dBFS SNR and 76dBc

The ADS58B18 uses TI-proprietary SNRBoost SFDR at 150MHz

technology that can be used to overcome SNR

• Enhanced SNR Using TI-Proprietary SNRBoost

limitation as a result of quantization noise for Technology (ADS58B18 Only)

bandwidths less than Nyquist (f_S/2).

– –77.7dBFS SNR in 20MHz Bandwidth

Both devices have gain options that can be used to

• Dynamic Power Scaling with Sample Rate

improve SFDR performance at lower full-scale input

• Output Interface: ranges, especially at very high input frequencies.

They also include a dc offset correction loop that can – Double Data Rate (DDR) LVDS with

be used to cancel the ADC offset. At lower sampling Programmable Swing and Strength

rates, the ADC automatically operates at scaled-down – Standard Swing: 350mV

power with no loss in performance.

– Low Swing: 200mV

These devices support both double data rate (DDR) – Default Strength: 100ΩTermination low-voltage differential signaling (LVDS) and parallel – 2x Strength: 50Ω Termination CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes – 1.8V Parallel CMOS Interface Also

it possible to use low-cost field-programmable gate Supported

array (FPGA)-based receivers. They have a

• Programmable Gain for SNR/SFDR Trade-Off low-swing LVDS mode that can be used to further

• DC Offset Correction reduce the power consumption. The strength of the LVDS output buffers can also be increased to support

• Supports Low Input Clock Amplitude

50Ωdifferential termination.

• Package: QFN-48 (7mm×7mm)

The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

SPECIFIED

PACKAGE- PACKAGE TEMPERATURE LEAD/BALL PACKAGE ORDERING TRANSPORT

PRODUCT LEAD DESIGNATOR RANGE ECO PLAN⁽²⁾ FINISH MARKING NUMBER MEDIA

ADS58B18IRGZR Tape and reel GREEN (RoHS,

ADS58B18 QFN-48 RGZ –40°C to +85°C Cu/NiPdAu AZ58B18

no Sb/Br) ADS58B18IRGZT Tape and reel

ADS58B19IRGZR Tape and reel GREEN (RoHS,

ADS58B19 QFN-48 RGZ –40°C to +85°C Cu/NiPdAu AZ58B19

no Sb/Br) ADS58B19IRGZT Tape and reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder atwww.ti.com.

(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to theQuality and Lead-Free (Pb-Free) Dataweb site for more information.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ADS58B18, ADS58B19

MIN MAX UNIT

Supply voltage range, AVDD –0.3 2.1 V

Supply voltage range, AVDD_BUF –0.3 3.9 V

Supply voltage range, DRVDD –0.3 2.1 V

Voltage between AGND and DRGND –0.3 0.3 V

Voltage between AVDD to DRVDD (when AVDD leads DRVDD) –2.4 2.4 V

Voltage between DRVDD to AVDD (when DRVDD leads AVDD) –2.4 2.4 V

Voltage between AVDD_BUF to DRVDD/AVDD –4.2 4.2 V

minimum

INP, INM –0.3 V

(1.9, AVDD + 0.3) Voltage applied to input pins

CLKP, CLKM⁽²⁾, RESET, SCLK, –0.3 AVDD + 0.3 V

SDATA, SEN, DFS, SNRBoost_En

Operating free-air temperature range, TA –40 +85 °C

Operating junction temperature range, TJ +125 °C

Storage temperature range, T_stg –65 +150 °C

ESD, human body model (HBM) 2 kV

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.

Doing so prevents the ESD protection diodes at the clock input pins from turning on.

THERMAL INFORMATION

ADS58B18

THERMAL METRIC⁽¹⁾ RGZ UNITS

48 PINS

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RECOMMENDED OPERATING CONDITIONS

ADS58B18, ADS58B19

MIN TYP MAX UNIT

SUPPLIES

AVDD Analog supply voltage 1.7 1.8 1.9 V

AVDD_BUF Analog buffer supply voltage 3 3.3 3.6 V

DRVDD Digital supply voltage 1.7 1.8 1.9 V

ANALOG INPUTS

Differential input voltage range 1.5 V_PP

Input common-mode voltage 1.7±0.05 V

Maximum analog input frequency with 1.5VPPinput amplitude⁽¹⁾ 400 MHz

Maximum analog input frequency with 1VPPinput amplitude⁽¹⁾ 600 MHz

CLOCK INPUT

Input clock sample rate: ADS58B18

Enable low speed mode⁽²⁾ 30 80 MSPS

Low speed mode disabled (default mode after reset) >80 200 MSPS

Input clock sample rate: ADS58B19

Enable low speed mode⁽²⁾ 30 80 MSPS

Low speed mode disabled (default mode after reset) >80 250 MSPS

Input clock amplitude differential (V_CLKP–V_CLKM)

Sine wave, ac-coupled 0.2 1.5 VPP

LVPECL, ac-coupled 1.6 VPP

LVDS, ac-coupled 0.7 V_PP

LVCMOS, single-ended, ac-coupled 1.8 V

Input clock duty cycle 35 50 65 %

DIGITAL OUTPUTS

Maximum external load capacitance from each output pin to

C_LOAD 5 pF

DRGND

Differential load resistance between the LVDS output pairs

RLOAD (LVDS mode) 100 Ω

T_A Operating free-air temperature –40 +85 °C

(1) See theTheory of Operationsection in theApplication Information.

(2) See theSerial Interfacesection for details on the low-speed mode.

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ELECTRICAL CHARACTERISTICS: ADS58B18/ADS58B19

Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 50% clock duty cycle,–1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full

temperature range:

T_MIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.8V.

ADS58B18 ADS58B19

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

Resolution 11 9 Bits

fIN= 10MHz 66.3 55.8 dBFS

SNR (signal-to-noise ratio), LVDS fIN= 100MHz 66.1 55.8 dBFS

f_IN= 170MHz 64.5 66 54.7 55.8 dBFS

fIN= 300MHz 65.3 55.8 dBFS

f_IN= 70MHz 66.1 55.8 dBFS

SINAD (signal-to-noise and distortion ratio),

fIN= 100MHz 66 55.8 dBFS

LVDS

fIN= 170MHz 64 65.8 54.2 55.8 dBFS

f_IN= 300MHz 64.8 55.7 dBFS

fIN= 10MHz 87.5 76.5 dBc

fIN= 70MHz 87 76.2 dBc

Spurious-free dynamic range SFDR fIN= 100MHz 87 76.1 dBc

f_IN= 170MHz 71 81 68.5 76 dBc

fIN= 300MHz 75 75.7 dBc

fIN= 10MHz 86.5 85 dBc

f_IN= 70MHz 85 80 dBc

Total harmonic distortion THD fIN= 100MHz 84 79 dBc

fIN= 170MHz 70 81 67.5 80.5 dBc

f_IN= 300MHz 74.5 71.5 dBc

fIN= 10MHz 90 88 dBc

Second-harmonic distortion HD2 fIN= 100MHz 92 85 dBc

f_IN= 170MHz 71 87 68.5 85 dBc

fIN= 10MHz 87.5 89 dBc

Third-harmonic distortion HD3 fIN= 100MHz 87 82 dBc

fIN= 170MHz 76 81 68.5 85 dBc

Worst spur

fIN= 100MHz 90 76.1 dBc

(other than second and third harmonics)

f_IN= 170MHz 76 89 68.5 76 dBc

Two-tone intermodulation f1= 185MHz, f2= 190MHz,

IMD –86 –86 dBFS

distortion each tone at–7dBFS

Recovery to within 1% (of final

Clock

Input overload recovery value) for 6dB overload with 1 1

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ELECTRICAL CHARACTERISTICS: GENERAL

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted.

Minimum and maximum values are across the full temperature range: T_MIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.8V.

ADS58B18 ADS58B19

PARAMETER MIN TYP MAX MIN TYP MAX UNIT

ANALOG INPUTS

Differential input voltage range 1.5 1.5 VPP

Differential input resistance (at dc); seeFigure 59 4 4 kΩ

Differential input capacitance; seeFigure 60 2.1 2.1 pF

Analog input bandwidth 550 550 MHz

Analog input common-mode current (per input pin) <2 <2 µA

Common-mode output voltage VCM 1.7 1.7 V

VCM output current capability 4 4 mA

DC ACCURACY

Offset error –15 2 15 –15 2 15 mV

Temperature coefficient of offset error 0.003 0.003 mV/°C

Gain error as a result of internal reference

EGREF –2 2 –2 2 %FS

inaccuracy alone

Gain error of channel alone E_GCHAN –0.2 –1 –0.2 –1 %FS

Temperature coefficient of EGCHAN 0.001 0.001 Δ%/°C

POWER SUPPLY IAVDD

88 105 103 113 mA

Analog supply current IAVDD_BUF

30 40 31 42 mA

Input buffer supply current IDRVDD⁽¹⁾

Output buffer supply current

38 47 mA

LVDS interface with 100Ωexternal termination Low LVDS swing (200mV)

IDRVDD

Output buffer supply current

62 75 64 82 mA

LVDS interface with 100Ωexternal termination Standard LVDS swing (350mV)

IDRVDD output buffer supply current^{(1) (2)} CMOS interface⁽²⁾

26 35 mA

8pF external load capacitance f_IN= 2.5MHz

Analog power:

260 287 mW

AVDD + AVDD_BUF supplies Digital power:

68.7 84.6 mW

LVDS interface, low LVDS swing Digital power:

CMOS interface⁽²⁾

47 63 mW

8pF external load capacitance f_IN= 2.5MHz

Global power-down 10 35 10 35 mW

Standby 185 185 mW

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DIGITAL CHARACTERISTICS

The dc specifications refer to the condition where the digital outputs are not switching but are permanently at a valid logic level'0'or'1'. AVDD = 1.8V and DRVDD = 1.8V.

ADS58B18, ADS58B19

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE, SNRBoost_En)

High-level input voltage RESET, SCLK, SDATA, 1.3 V

SNRBoost_En, and SEN support 1.8V and 3.3V CMOS

Low-level input voltage 0.4 V

logic levels

High-level input voltage OE only supports 1.8V CMOS 1.3 V

logic levels

Low-level input voltage 0.4 V

High-level input current: SDATA, SCLK⁽¹⁾ V_HIGH= 1.8V 10 µA

High-level input current: SEN⁽²⁾ VHIGH= 1.8V 0 µA

Low-level input current: SDATA, SCLK VLOW= 0V 0 µA

Low-level input current: SEN V_LOW= 0V –10 µA

DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)

High-level output voltage DRVDD–0.1 DRVDD V

Low-level output voltage 0 0.1 V

DIGITAL OUTPUTS (LVDS INTERFACE: D0P/M TO D9_10_P/M, CLKOUTP/M)

High-level output voltage⁽³⁾ VODH Standard swing LVDS 270 +350 430 mV

Low-level output voltage⁽³⁾ VODL Standard swing LVDS –430 –350 –270 mV

High-level output voltage⁽³⁾ V_ODH Low swing LVDS +200 mV

Low-level output voltage⁽³⁾ VODL Low swing LVDS –200 mV

Output common-mode voltage VOCM 0.85 1.05 1.25 V

(1) SDATA and SCLK have an internal 180kΩpull-down resistor.

(2) SEN has an internal 180kΩpull-up resistor to AVDD.

(3) With an external 100Ωtermination.

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36 35 34 33 32 31 30 29 28 27 26 25

DRGND DRVDD NC NC NC NC RESET SCLK SDATA SEN AVDD AGND

D9_D10_PVCM D9_D10_MAGND D7_D8_PINP D7_D8_MINM D5_D6_PAGND D5_D6_MAVDD D3_D4_PAGND D3_D4_MAVDD D1_D2_PAVDD_BUF D1_D2_MAVDD D0_PSNRBoost_En D0_MAVDD

1 2 3 4 5 6 7 8 9 10 11 12 DRGND

DRVDD OVR_SDOUT CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23 37

24

PIN CONFIGURATION (LVDS MODE)

RGZ PACKAGE⁽³⁾ QFN-48 (TOP VIEW)

(1) The PowerPAD™is connected to DRGND.

Figure 1. ADS58B18 LVDS Pinout

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36 35 34 33 32 31 30 29 28 27 26 25

VCM AGND

D7_D8_P INP

D7_D8_M INM

D5_D6_P AGND

D5_D6_M AVDD

D3_D4_P AGND

D3_D4_M AVDD

D1_D2_P AVDD_BUF

D1_D2_M AVDD

D0_P UNUSED

D0_M AVDD

1 2 3 4 5 6 7 8 9 10 11 12 DRGND

DRVDD OVR_SDOUT CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23 37

24

NC NC

RGZ PACKAGE⁽⁴⁾ QFN-48 (TOP VIEW)

(2) The PowerPAD is connected to DRGND.

Figure 2. ADS58B19 LVDS Pinout

ADS58B18, ADS58B19 Pin Assignments (LVDS Mode)

# OF

PIN NAME PIN NUMBER PINS FUNCTION DESCRIPTION

AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply

AVDD_BUF 21 1 I 3.3V input buffer supply

AGND 9, 12, 14, 17, 19, 25 6 I Analog ground

CLKP 10 1 I Differential clock input, positive

CLKM 11 1 I Differential clock input, negative

INP 15 1 I Differential analog input, positive

INM 16 1 I Differential analog input, negative

Outputs the common-mode voltage that can be used externally to bias the analog input

VCM 13 1 O

pins.

Serial interface RESET input.

When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset

RESET 30 1 I option; refer to theSerial Interfacesection.

When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin.

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ADS58B18, ADS58B19 Pin Assignments (LVDS Mode) (continued)

# OF

Output buffer enable input, active high; this pin has an internal 180kΩpull-up resistor to

OE 7 1 I

DRVDD.

Data format select input. This pin sets the DATA FORMAT (twos compliment or offset

DFS 6 1 I

binary) and the LVDS/CMOS output interface type. SeeTable 4for detailed information.

ADS58B18: Digital control pin for SNRBoost mode, active high.

SNRBoost_En 23 1 I

ADS58B19: Unused.

CLKOUTP 5 1 O Differential output clock, true

CLKOUTM 4 1 O Differential output clock, complement

Refer toFigure 1and

D0_P 1 O Differential output data D0 and logic low multiplexed, true

Figure 2 Refer toFigure 1and

D0_M 1 O Differential output data D0 and logic low multiplexed, complement

D1_D2_P 1 O Differential output data D1 and D2 multiplexed, true

D1_D2_M 1 O Differential output data D1 and D2 multiplexed, complement

Figure 2

This pin functions as an out-of-range indicator after reset, when register bit SERIAL READOUT = 0, and functions as a serial register readout pin when SERIAL

OVR_SDOUT 3 1 O

READOUT = 1.

This pin is a CMOS output level that runs off DRVDD supply.

DRVDD 2, 35 2 I 1.8V digital and output buffer supply

DRGND 1, 36, PAD 2 I Digital and output buffer ground

Refer toFigure 1and

NC — — Do not connect

Figure 2

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36 35 34 33 32 31 30 29 28 27 26 25

VCM AGND

D10 INP

D9 INM

D8 AGND

D7 AVDD

D6 AGND

D5 AVDD

D4 AVDD_BUF

D3 AVDD

D2 SNRBoost_En

D1 AVDD

1 2 3 4 5 6 7 8 9 10 11 12 DRGND

DRVDD OVR_SDOUT UNUSED CLKOUT DFS OE AVDD AGND CLKP CLKM AGND

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23 37

24

D0 NC

PIN CONFIGURATION (CMOS MODE)

RGZ PACKAGE⁽⁵⁾ QFN-48 (TOP VIEW)

Figure 3. ADS58B18 CMOS Pinout

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36 35 34 33 32 31 30 29 28 27 26 25

VCM AGND INP INM

D8 AGND

D7 AVDD

D6 AGND

D5 AVDD

D4 AVDD_BUF

D3 AVDD

D2 UNUSED

D1 AVDD

1 2 3 4 5 6 7 8 9 10 11 12 DRGND

DRVDD OVR_SDOUT UNUSED CLKOUT DFS OE AVDD AGND CLKP CLKM AGND

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23 37

24

D0 NCNCNC

RGZ PACKAGE⁽⁶⁾ QFN-48 (TOP VIEW)

Figure 4. ADS58B19 CMOS Pinout

ADS58B18, ADS58B19 Pin Assignments (CMOS Mode)

# OF

AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply

AVDD_BUF 21 1 I 3.3V input buffer supply

AGND 9, 12, 14, 17, 19, 25 6 I Analog ground

CLKP 10 1 I Differential clock input, positive

CLKM 11 1 I Differential clock input, negative

INP 15 1 I Differential analog input, positive

INM 16 1 I Differential analog input, negative

Outputs the common-mode voltage that can be used externally to bias the analog input

VCM 13 1 O

pins.

Serial interface RESET input.

When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset

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ADS58B18, ADS58B19 Pin Assignments (CMOS Mode) (continued)

# OF

Data format select input. This pin sets the DATA FORMAT (twos compliment or offset

DFS 6 1 I

binary) and the LVDS/CMOS output interface type. SeeTable 4for detailed information.

ADS58B18: Digital control pin for SNRBoost mode, active high.

SNRBoost_En 23 1 I

ADS58B19: Unused.

CLKOUT 5 1 O Differential output clock, true

Output buffer enable input, active high; this pin has an internal 180kΩpull-up resistor to

OE 7 1 I

DRVDD.

Refer toFigure 1and

D0 1 O Differential output data D0 and logic low multiplexed, true

D1 1 O Differential output data D1 and D2 multiplexed, true

D2 1 O Differential output data D1 and D2 multiplexed, complement

Figure 2

This pin functions as an out-of-range indicator after reset, when register bit SERIAL READOUT = 0, and functions as a serial register readout pin when SERIAL

OVR_SDOUT 3 1 O

READOUT = 1.

This pin is a CMOS output level that runs off DRVDD supply.

DRVDD 2, 35 2 I 1.8V digital and output buffer supply

DRGND 1, 36, PAD 2 I Digital and output buffer ground

UNUSED 4 1 — Not used in CMOS mode

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14-Bit ADC

OVR_SDOUT D9_D10_M D9_D10_P D7_D8_M D7_D8_P D5_D6_M D5_D6_P D3_D4_M D3_D4_P D1_D2_M D1_D2_P D0_M D0_P CLKOUTM CLKOUTP CLKM

CLKP

CLOCKGEN

INM

VCM INP

Sampling Circuit

Digital Functions

DDR Serializer

Reference

ADS58B18

AVDD AGND DRVDD DRGND

DDR LVDS Interface

Analog Buffers AVDD_BUF

SNRBoost

Control Interface

SDATA DFS

SENSCLK

RESET SNRBoost_En

OE

FUNCTIONAL BLOCK DIAGRAMS

Figure 5. ADS58B18 Block Diagram

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9-Bit ADC

OVR_SDOUT D7_D8_M D7_D8_P D5_D6_M D5_D6_P D3_D4_M D3_D4_P D1_D2_M D1_D2_P D0_M D0_P CLKOUTM CLKOUTP CLKM

CLKP

CLOCKGEN

INM

VCM INP

Sampling Circuit

Digital Functions

DDR Serializer

Reference

ADS58B19

AVDD AGND DRVDD DRGND

DDR LVDS Interface

Analog Buffers AVDD_BUF

Control Interface

SDATA DFS

SENSCLK

RESET OE

Figure 6. ADS58B19 Block Diagram

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Dn_Dn + 1_P

Dn_Dn + 1_M

GND

Logic 0 V_OD= 350mV-

Logic 1 V_OD= +350mV

V_OCM

TIMING CHARACTERISTICS

(1) With external 100Ωtermination.

Figure 7. LVDS Output Voltage Levels

TIMING REQUIREMENTS: LVDS and CMOS Modes⁽¹⁾

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, C_LOAD= 5pF⁽²⁾, and R_LOAD= 100Ω⁽³⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.

PARAMETER CONDITIONS MIN TYP MAX UNIT

t_A Aperture delay⁽⁴⁾ 0.6 0.8 1.2 ns

Variation of aperture Between two devices at the same temperature and

±100 ps

delay DRVDD supply

t_J Aperture jitter 100 f_Srms

Time to valid data after coming out of STANDBY

5 25 µs

Wakeup time mode

Time to valid data after coming out of PDN GLOBAL

100 500 µs

mode

After reset, gain enabled and offset correction 16 Clock

disabled cycles

ADC latency⁽⁵⁾

Clock

Gain and offset correction enabled 17 cycles

DDR LVDS MODE⁽⁶⁾

t_SU Data setup time⁽⁷⁾ Data valid to zero-crossing of CLKOUTP 0.75 1.1 ns

tH Data hold time⁽⁷⁾ Zero-crossing of CLKOUTP to data becoming invalid 0.35 0.6 ns Input clock rising edge cross-over to output clock

Clock propagation

t_PDI rising edge cross-over 3 4.2 5.4 ns

delay

1MSPS≤sampling frequency≤250MSPS Between two devices at the same temperature and

Variation of t_PDI ±0.6 ns

DRVDD supply

(1) Timing parameters are ensured by design and characterization but are not production tested.

(2) C_LOADis the effective external single-ended load capacitance between each output pin and ground.

(3) RLOADis the differential load resistance between the LVDS output pair.

(4) This parameter is specified by design.

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TIMING REQUIREMENTS: LVDS and CMOS Modes⁽¹⁾(continued)

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, C_LOAD= 5pF⁽²⁾, and R_LOAD= 100Ω⁽³⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.

PARAMETER CONDITIONS MIN TYP MAX UNIT

DDR LVDS MODE (continued)

Duty cycle of differential clock, (CLKOUTP– LVDS bit clock duty

CLKOUTM) 42 48 54 %

cycle

1MSPS≤sampling frequency≤250MSPS Rise time measured from–100mV to +100mV Data rise time,

t_RISE, t_FALL Fall time measured from +100mV to–100mV 0.14 ns

Data fall time

1MSPS≤sampling frequency≤250MSPS Output clock rise Rise time measured from–100mV to +100mV

tCLKRISE, time, Fall time measured from +100mV to–100mV 0.14 ns

t_CLKFALL

Output clock fall time 1MSPS≤sampling frequency≤250MSPS Output enable (OE) to

t_OE Time to valid data after OE becomes active 50 100 ns

data delay PARALLEL CMOS MODE⁽⁸⁾

Input clock to data Input clock rising edge cross-over to start of data

t_START 1.1 ns

delay valid⁽⁹⁾

t_DV Data valid time Time interval of valid data⁽⁹⁾ 2.5 3.2 ns

Input clock rising edge cross-over to output clock Clock propagation

t_PDI rising edge cross-over 4 5.5 7 ns

delay

1MSPS≤sampling frequency≤200MSPS

Output clock duty Duty cycle of output clock, CLKOUT 47 %

cycle 1MSPS≤sampling frequency≤200MSPS

Rise time measured from 20% to 80% of DRVDD Data rise time,

t_RISE, t_FALL Fall time measured from 80% to 20% of DRVDD 0.35 ns

Data fall time

1≤sampling frequency≤250MSPS Output clock rise Rise time measured from 20% to 80% of DRVDD t_CLKRISE,

time, Fall time measured from 80% to 20% of DRVDD 0.35 ns

tCLKFALL Output clock fall time 1≤sampling frequency≤200MSPS Output enable (OE) to

t_OE Time to valid data after OE becomes active 20 40 ns

data delay

(8) For fS>200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT).

(9) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.

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Table 1. LVDS Timing Across Sampling Frequencies

SAMPLING SETUP TIME (ns) HOLD TIME (ns)

FREQUENCY

(MSPS) MIN TYP MAX MIN TYP MAX

230 0.85 1.25 0.35 0.6

200 1.05 1.55 0.35 0.6

185 1.1 1.7 0.35 0.6

160 1.6 2.1 0.35 0.6

125 2.3 3 0.35 0.6

80 4.5 5.2 0.35 0.6

Table 2. CMOS Timing Across Sampling Frequencies (Default, After Reset)

TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK SAMPLING

t_SETUP(ns) t_HOLD(ns) t_PDI(ns)

FREQUENCY

(MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX

200 1 1.6 2 2.8 4 5.5 7

185 1.3 2 2.2 3 4 5.5 7

160 1.8 2.5 2.5 3.3 4 5.5 7

125 2.5 3.2 3.5 4.3 4 5.5 7

80 4.8 5.5 5.7 6.5 4 5.5 7

Table 3. CMOS Timing Across Sampling Frequencies (Default, After Reset)

TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK

tSTART(ns) tDV(ns)

SAMPLING FREQUENCY

(MSPS) MIN TYP MAX MIN TYP MAX

250 1.6 2.5 3.2

230 1.1 2.9 3.5

200 0.3 3.5 4.2

185 0 3.9 4.5

170 –1.3 4.3 5

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O E O E O E O E O E

E O E O E O E O

E O

N + 1 N + 2 Input Clock

CLKOUTM

CLKOUTP

Output Data⁽²⁾ (DXP, DXM) DDR LVDS

N-1 N N + 1

CLKOUT

Output Data Parallel CMOS

Input Signal

Sample N N + 1 N + 2 N + 3 N + 4

N + 16

N + 17 N + 18

t_A

t_SU

t_SU t_H

t_H t_PDI

tPDI CLKP

CLKM

N-16 N-15 N-14 N-13

N-16 N-15 N-14 N-13 N-12

16 Clock Cycles⁽¹⁾

N 16 Clock Cycles⁽¹⁾

(1) At higher sampling frequencies, t_DPIis greater than one clock cycle, which then makes the overall latency = ADC latency + 1.

(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).

Figure 8. Latency Diagram

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CLKOUTP

CLKOUTM

Output

Data Pair Dn_Dn + 1_P Dn⁽¹⁾ Dn + 1⁽¹⁾ Dn_Dn + 1_M

CL MK

CL PK

Output Clock Input Clock

t_SU t_H t_SU t_H

t_PDI

CLKOUT

Output

Data Dn Dn⁽¹⁾

CL MK

CL PK

Output Clock Input Clock

Output

Data Dn Dn⁽¹⁾

t_START CL MK

CL PK Input

Clock

t_DV

t_SU t_H

t_PDI

(1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc.

Figure 9. LVDS Mode Timing

Dn = bits D0, D1, D2, etc.

Figure 10. CMOS Mode Timing

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AVDD

(5/8) AVDD

(3/8) AVDD 3R

2R

3R (3/8) AVDD

(5/8) AVDD

AVDD GND

To Parallel Pin

DEVICE CONFIGURATION

The ADS58B18/9 have several modes that can be configured using a serial programming interface, as described in Table 4 through Table 7. In addition, the devices have three dedicated parallel pins for quickly configuring commonly-used functions. The parallel pins are DFS (analog 4-level control pin), OE (digital control pin), and SNRBoost_En (digital control pin). The analog control pin can be easily configured using a simple resistor divider (with 10% tolerance resistors).

Table 4. DFS: Analog Control Pin

DESCRIPTION

VOLTAGE APPLIED ON DFS (Data Format/Output Interface)

0, +100mV/–0mV Twos complement/DDR LVDS

(3/8) AVDD±100mV Twos complement/parallel CMOS

(5/8) AVDD±100mV Straight binary/parallel CMOS

AVDD, +0mV/–100mV Straight binary/DDR LVDS

Table 5. OE: Digital Control Pin

VOLTAGE APPLIED ON OE DESCRIPTION

0 Output data buffers disabled

AVDD Output data buffers enabled

Table 6. SNRBoost_En: Digital Control Pin (ADS58B18 Only)

VOLTAGE APPLIED ON SNRBoost_En DESCRIPTION

0 SNRBoost disabled

Logic high SNRBoost enabled

When the serial interface is not used, the SDATA pin can also be used as a standby control pin. To enable this, the RESET pin must be tied high.

Table 7. SDATA: Digital Control Pin

VOLTAGE APPLIED ON SDATA DESCRIPTION

0 Normal operation

Logic high Device enters standby

Figure 11. Simplified Diagram to Configure DFS Pin

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t_SCLK t_DSU

t_DH

t_SLOADS t_SLOADH

SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SCLK

SEN

RESET

Register Address Register Data

SERIAL INTERFACE

The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. When SEN is low, the serial shift of bits into the device is enabled, the serial data (on SDATA) are latched at every falling edge of SCLK, and the serial data are loaded into the register at every 16th SCLK falling edge.

In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle.

Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways:

1. Either through hardware reset by applying a high pulse on the RESET pin (of width greater than 10ns), as shown inFigure 12; or

2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.

This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is held low.

Figure 12. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

Typical values at +25°C, minimum and maximum values across the full temperature range: TMIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.

PARAMETER MIN TYP MAX UNIT

f_SCLK SCLK frequency (equal to 1/t_SCLK) >DC 20 MHz

tSLOADS SEN to SCLK setup time 25 ns

tSLOADH SCLK to SEN hold time 25 ns

t_DSU SDATA setup time 25 ns

t_DH SDATA hold time 25 ns