• Nie Znaleziono Wyników

HFA0001

N/A
N/A
Protected

Academic year: 2022

Share "HFA0001"

Copied!
10
0
0

Pełen tekst

(1)

Ultra High Slew RateOperational Amplifier

The HFA-0001 is an all bipolar op amp featuring high slew rate (1000V/µs), and high unity gain bandwidth (350MHz).

These features combined with fast settling time (25ns) make this product very useful in high speed data acquisition systems as well as RF, video, and pulse amplifier designs.

Other outstanding characteristics include low bias currents (15µA), low offset current (18µA), and low offset voltage (6mV).

The HFA-0001 offers high performance at low cost. It can replace hybrids and RF transistor amplifiers, simplifying designs while providing increased reliability due to

monolithic construction. To enhance the ease of design, the HFA-0001 has a 50Ω ±20% resistor connected from the output of the op amp to a separate pin. This can be used when driving 50Ω strip line, microstrip, or coax cable.

Features

• Unity Gain Bandwidth. . . 350MHz

• Full Power Bandwidth . . . 53MHz

• High Slew Rate . . . 1000V/µs

• High Output Drive. . . ±50mA

• Monolithic Construction

Applications

• RF/IF Processors

• Video Amplifiers

• High Speed Cable Drivers

• Pulse Amplifiers

• High Speed Communications

• Fast Data Acquisition Systems

Pinouts

Part Number Information

PART NUMBER

TEMPERATURE

RANGE PACKAGE

HFA1-0001-5 0oC to +75oC 14 Lead Ceramic Sidebraze DIP HFA1-0001-9 -40oC to +85oC 14 Lead Ceramic Sidebraze DIP HFA3-0001-5 0oC to +75oC 8 Lead Plastic DIP

HFA3-0001-9 -40oC to +85oC 8 Lead Plastic DIP HFA9P0001-5 0oC to +75oC 16 Lead Widebody SOIC

HFA-0001 (PDIP) TOP VIEW

HFA-0001 (CDIP) TOP VIEW

HFA-0001 (300 MIL SOIC)

TOP VIEW

NC

+IN V-

2 3 4

1 RSENSE

V+

OUT NC 7 6 5 8

+ -IN

NC NC NC

+IN

NC

NC NC

V+

NC NC 1

2 3 4 5 6 7

14 13 12 11 10 9 8

RSENSE

+ OUT -IN

V-

14 15 16

9 13 12 11 10 1

2 3 4 5

7 6

8 NC NC NC -IN +IN V-

NC NC

NC

RSENSE V+

OUT NC NC NC NC

+

September 1998 File Number 2916.3 OBSOLETE PRODUCT

Recommended Replacements: HFA1100, HFA1105 or contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

(2)

Absolute Maximum Ratings (Note 1) Operating Conditions

Supply Voltage (Between V+ and V- Terminals) . . . .12V Differential Input Voltage . . . .5V Input Voltage. . . ±4V Output Current . . . 60mA Junction Temperature (Note 9) . . . .+175oC Junction Temperature (Plastic Package) . . . .+150oC Lead Temperature (Soldering 10 Sec.) . . . .+300oC

Operating Temperature Range

HFA-0001-9 . . . .-40oC ≤ TA ≤ +85oC HFA-0001-5 . . . 0oC ≤ TA ≤ +75oC Storage Temperature Range . . . .-65oC ≤ TA ≤ +150oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications V+ = +5V, V- = -5V, Unless Otherwise Specified

PARAMETER TEMP

HFA-0001-9 HFA-0001-5

UNITS

MIN TYP MAX MIN TYP MAX

INPUT CHARACTERISTICS

Offset Voltage +25oC - 6 15 - 6 30 mV

High - 4.5 20 - 4.5 30 mV

Low - 12.5 45 - 12.5 35 mV

Average Offset Voltage Drift High - 50 - - 50 - µV/oC

Low - 100 - - 100 - µV/oC

Bias Current +25oC - 15 50 - 15 100 µA

Full - 20 50 - 20 100 µA

Offset Current +25oC - 18 25 - 18 50 µA

Full - 22 50 - 22 50 µA

Common Mode Range +25oC ±3 - - ±3 - - V

Differential Input Resistance +25oC - 10 - - 10 - kΩ

Input Capacitance +25oC - 2 - - 2 - pF

Input Noise Voltage 0.1Hz to 10Hz +25oC - 3.5 - - 3.5 - µVrms

10Hz to 1MHz +25oC - 6.7 - - 6.7 - µVrms

Input Noise Voltage fO = 10Hz +25oC - 640 - - 640 - nV/√Hz

fO = 100Hz +25oC - 170 - - 170 - nV/√Hz

fO = 100kHz +25oC - 6 - - 6 - nV/√Hz

Input Noise Current fO = 10Hz +25oC - 2.35 - - 2.35 - nA/√Hz

fO = 100Hz +25oC - 0.57 - - 0.57 - nA/√Hz

fO = 1000Hz +25oC - 0.16 - - 0.16 - nA/√Hz

TRANSFER CHARACTERISTICS

Large Signal Voltage Gain (Note 2) +25oC 150 200 - 150 200 - V/V

High 150 170 - 100 170 - V/V

Low 150 220 - 150 220 - V/V

Common Mode Rejection Ratio (Note 3) +25oC 45 47 - 42 47 - dB

High 40 45 - 40 45 - dB

Low 45 48 - 42 48 - dB

Unity Gain Bandwidth +25oC - 350 - - 350 - MHz

Minimum Stable Gain Full 1 - - 1 - - V/V

OUTPUT CHARACTERISTICS

(3)

RL = 1kΩ +25oC ±3.5 ±3.7 - ±3.5 ±3.7 - V

High ±3.0 ±3.6 - ±3.0 ±3.6 - V

Low ±3.5 ±3.7 - ±3.5 ±3.7 - V

Full Power Bandwidth (Note 5) +25oC - 53 - - 53 - MHz

Output Resistance, Open Loop +25oC - 3 - - 3 -

Output Current Full ±30 ±50 - ±30 ±50 - mA

TRANSIENT RESPONSE

Rise Time (Note 4, 6) +25oC - 480 - - 480 - ps

Slew Rate (Note 4, 7) RL = 1kΩ +25oC - 1000 - - 1000 - V/µs

RL = 100Ω +25oC - 875 - - 875 - V/µs

Settling Time (3V Step) 0.1% +25oC - 25 - - 25 - ns

Overshoot (Note 4, 6) +25oC - 36 - - 36 - %

POWER SUPPLY CHARACTERISTICS

Supply Current Full - 65 75 - 65 75 mA

Power Supply Rejection Ratio (Note 8) +25oC 40 42 - 37 42 - dB

High 35 41 - 35 41 - dB

Low 40 42 - 37 42 - dB

NOTES:

1. Absolute Maximum Ratings are limiting values applied individually beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied.

2. VOUT = 0 to ±2V, RL = 1kΩ.

3. ∆VCM = ±2V.

4. RL = 100Ω.

5. Full Power Bandwidth is calculated by equation: .

6. VOUT = ±200mV, AV = +1.

7. VOUT = ±3V, AV = +1.

8. ∆VS = ±4V to ±6V.

9. See Thermal Constants in ‘Applications Information’ text. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below +175oC for hermetic packages, and below +150oC for plastic packages.

Electrical Specifications V+ = +5V, V- = -5V, Unless Otherwise Specified (Continued)

PARAMETER TEMP

HFA-0001-9 HFA-0001-5

UNITS

MIN TYP MAX MIN TYP MAX

FPBW Slew R ate 2πVPEAK

---, VPEAK 3.0V

= =

Schematic Diagram Die Characteristics

Thermal Constants (oC/W) θJA θJC

HFA1-0001-5/-9 75 13

HFA3-0001-5 98 36

HFA9P-0001-5/-9 96 27

V+

+IN

RSENSE

VOUT -IN

V-

(4)

Test Circuits

FIGURE 1. LARGE SIGNAL RESPONSE TEST CIRCUIT FIGURE 2. SMALL SIGNAL RESPONSE TEST CIRCUIT

LARGE SIGNAL RESPONSE VOUT = 0V to 3V Vertical Scale: 1V/Div.

Horizontal Scale: 2ns/Div.

SMALL SIGNAL RESPONSE VOUT = 0mV to 200mV Vertical Scale: 100mV/Div.

Horizontal Scale: 2ns/Div.

NOTE: Initial Step In Output Is Due To Fixture Feedthrough

PROPAGATION DELAY Vertical Scale: 500mV/Div.

Horizontal Scale: 2ns/Div.

AV = +1, RL = 100Ω, VOUT = 0V to 3V VIN

VOUT +

1kΩ 50Ω

50Ω 20pF

VIN

VOUT +

100Ω 50Ω

50Ω

VIN

VOUT

VIN

VOUT

VIN

+ 1kΩ

VSETTLE

VOUT 1kΩ

100Ω

100Ω

(5)

Typical Performance Curves

VS = ±5V, TA = +25oC, Unless Otherwise Specified

FIGURE 4. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE 5. CLOSED LOOP GAIN vs FREQUENCY

FIGURE 6. CLOSED LOOP GAIN vs FREQUENCY FIGURE 7. CLOSED LOOP GAIN vs FREQUENCY

FIGURE 8. RISE TIME vs TEMPERATURE FIGURE 9. CMRR vs FREQUENCY

GAIN (dB)

50 40 30 20 10 0

100K 1M 10M 100M

FREQUENCY (Hz)

1G 0 45 90 135 180

PHASE MARGIN (DEGREES)

GAIN

PHASE

RL = 100Ω

10M 100M 1G

1M

FREQUENCY (Hz)

GAIN (dB)

0 -10 -20

0 45 90 135 180

PHASE MARGIN (DEGREES)

20 10

GAIN

PHASE VIN

50Ω 100Ω

VOUT

50Ω

AV = +1, RL = 100Ω, RF = 50Ω

10M 100M 1G

1M

FREQUENCY (Hz)

GAIN (dB) PHASE MARGIN (DEGREES)

0 45 90 135 180 20

10 0 -10 -20

VIN

50Ω 100Ω

VOUT

100Ω

100K 1M 10M 100M

FREQUENCY (Hz)

1G

GAIN (dB) PHASE MARGIN (DEGREES)

0 45 90 135 180 30

20 10 0 -10

VIN VOUT

900Ω 100Ω 100Ω 50Ω

AV = +10 RL = 100Ω

700

600

500

400

300

200

100

RISE TIME (ps)

-60 -40 -20 0 20 40 60 80 100 120

TEMPERATURE (oC) AV = +1, RL = 100Ω

VOUT = 0mV to 200mV

100K 1M 10M 100M

FREQUENCY (Hz)

1G

CMRR (dB) 50

40

30

20 10 0 60 70 80

(6)

FIGURE 10. PSRR vs FREQUENCY FIGURE 11. OFFSET VOLTAGE vs TEMPERATURE (3 REPRESENTATIVE UNITS)

FIGURE 12. BIAS CURRENT vs TEMPERATURE (3 REPRESENTATIVE UNITS)

FIGURE 13. OFFSET CURRENT vs TEMPERATURE (3 REPRESENTATIVE UNITS)

Typical Performance Curves

VS = ±5V, TA = +25oC, Unless Otherwise Specified (Continued)

100K 1M 10M 100M

FREQUENCY (Hz)

1G

PSRR (dB) 50

40

30

20

10

0 80

70

60

+PSRR

-PSRR

OFFSET VOLTAGE (mV)

-20

TEMPERATURE (oC)

0 20 40 60 80 100 120

-60 -40 -20 25

20 15 10

0 5

-5 -10 -15

TEMPERATURE (oC)

0 20 40 60 80 100 120

-60 -40 -20 -20

-10 30

20

10

0 40

BIAS CURRENT (µA)

TEMPERATURE (oC)

0 20 40 60 80 100 120

-60 -40 -20

OFFSET CURRENT (µA)

-20 20 15 10 5 0 -5 -10 -15

-25

OPEN LOOP GAIN (V/V)

0 20 40 60 80 100 120

-60 -40 -20 300

280 260 240 220 200 180 160 140 120 100 80 60 40 20 0

-AVOL

+AVOL

RL = 1kΩ, VOUT = 0V to ±2V

OUTPUT VOLTAGE (V)

4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0

0 20 40 60 80 100 120

-60 -40 -20

-VOUT

+VOUT

RL = 1kΩ

(7)

FIGURE 16. SLEW RATE vs TEMPERATURE FIGURE 17. CMRR vs TEMPERATURE

FIGURE 18. PSRR vs TEMPERATURE FIGURE 19. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 20. SUPPLY CURRENT vs TEMPERATURE FIGURE 21. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY

Typical Performance Curves

VS = ±5V, TA = +25oC, Unless Otherwise Specified (Continued)

TEMPERATURE (oC)

0 20 40 60 80 100 120

-60 -40 -20

SLEW RATE (V/µs)

1200

1100

1000

900

800

700

600

500

+SLEW RATE -SLEW RATE AV = +1, RL = 100Ω

VOUT = ±3V

TEMPERATURE (oC)

CMRR (dB)

0 20 40 60 80 100 120

-60 -40 -20 60

58 56 54 52 50 48 46 44 42 40 38 36 34

-CMRR

+CMRR

TEMPERATURE (oC)

0 20 40 60 80 100 120

-60 -40 -20

PSRR (dB)

10 90 80 70 60 50

30 20

0

40 +PSRR

-PSRR

∆VS = ±4V TO ±6V

SUPPLY CURRENT (mA)

70

60

50

40

30

20

10

0

5

1 2 3 4

0

SUPPLY VOLTAGE (±V)

SUPPLY CURRENT (mA)

0 20 40 60 80 100 120

-60 -40 -20 70

68 66 64 62 60 58 56 54 52 50 48 46 44

TEMPERATURE (oC)

10M 100M 1G

1M

FREQUENCY (Hz) 5.0

4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0

PEAK OUTPUT VOLTAGE SWING (V) AV = +1, RL = 100Ω THD < 1%

(8)

FIGURE 22. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 23. OPEN LOOP GAIN vs LOAD RESISTANCE

FIGURE 24. INPUT NOISE vs FREQUENCY FIGURE 25. INPUT NOISE vs FREQUENCY

Typical Performance Curves

VS = ±5V, TA = +25oC, Unless Otherwise Specified (Continued)

100 1K 10K

10

PEAK OUTPUT VOLTAGE SWING (V)

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0

LOAD RESISTANCE (Ω) AV = +1, fO = 50kHz

THD < 1%

240 220 200 180 160 140 120 100 80 60 40

OPEN LOOP GAIN (V/V)

LOAD RESISTANCE (Ω)

100 1K 10K

10

VOUT = ±2V

-AVOL +AVOL

NOISE VOLTAGE (µV/Hz)

8

7 6

5 4 3 2 1

0

FREQUENCY (Hz)

1 10 100 1K 10K 100K

NOISE CURRENT (nA/Hz)

8

7 6

5 4 3 2 1

0 NOISE CURRENT

NOISE VOLTAGE

FREQUENCY (Hz)

NOISE VOLTAGE (nV/Hz)

100 1K 10K 100K

600

500

400

300

200

100

0

NOISE CURRENT (pA/Hz)

600

500

400

300

200

100

0 NOISE CURRENT

NOISE VOLTAGE

(9)

Applications Information

Offset Adjustment

When applications require the offset voltage to be as low as possible, the figure below shows two possible schemes for adjusting offset voltage.

For a voltage follower application, use the circuit in Figure 29 without R2 and with RI shorted. R1 should be 1MΩ to 10MΩ.

The adjustment resistors will cause only a very small gain error.

FIGURE 28. INVERTING GAIN

FIGURE 29. NON-INVERTING GAIN

PC Board Layout Guidelines

When designing with the HFA-0001, good high frequency (RF) techniques should be used when making a PC board. A massive ground plane should be used to maintain a low impedance ground. Proper shielding and use of short interconnection leads are also very important.

To achieve maximum high frequency performance, the use of low impedance transmission lines with impedance matching is recommended: 50Ω lines are common in communications and 75Ω lines in video systems. Impedance matching is important to minimize reflected energy therefore minimizing transmitted signal distortion. This is

accomplished by using a series matching resistor (50Ω or 75Ω), matched transmission line (50Ω or 75Ω), and a matched terminating resistor, as shown in Figure 30. Note that there will be a 6dB loss from input to output.The HFA- 0001 has an integral 50Ω ±20% resistor connected to the op amps output with the other end of the resistor pinned out.

This 50Ω resistor can be used as the series resistor instead of an external resistor.

FIGURE 30.

PC board traces can be made to look like a 50Ω or 75Ω transmission line, called microstrip. Microstrip is a PC board trace with a ground plane directly beneath, on the opposite side of the board, as shown in Figure 31.

FIGURE 31.

When manufacturing pc boards, the trace width can be calculated based on a number of variables. The following equation is reasonably accurate for calculating the proper trace width for a 50Ω transmission line.

Power supply decoupling is essential for high frequency op amps. A 0.01µF high quality ceramic capacitor at each supply pin in parallel with a 1µF tantalum capacitor will provide excellent decoupling as shown in Figure 32.

FIGURE 32. POWER SUPPLY DECOUPLING +

RI 50kΩK

R1 100kΩ +5V

VOUT

100 R2

RF

-5V

VIN -

Adjustment Range V R2 R1 ---

±

RI

+

50kΩ +V

-V R1 100kΩ

100Ω

R2 RF

VOUT VIN

-

Adjustment Range V R2 R1 ---

±

Gain 1

RF RI+R2 ---

+

50+

RF

VOUT VIN

50Ω COAX CABLE 50Ω

50Ω

SIGNAL TRACE

GROUND PLANE

DIELECTRIC (PC BOARD) h

w

t

ER

ZO

87 ER+1.41

---ln 5.98h 0.8w+t ---

 Ω

=

+ V+

1.0µF

V- 0.01µF

0.01µF 1.0µF

(10)

FIGURE 33. IMPROVED DECOUPLING/CURRENT LIMITING Chip capacitors produce the best results due to ease of placement next to the op amp and they have negligible lead inductance. If leaded capacitors are used, the leads should be kept as short as possible to minimize lead inductance.

Figures 32 and 33 illustrate two different decoupling schemes. Figure 33 improves the PSRR because the resistor and capacitors create low pass filters. Note that the supply current will create a voltage drop across the resistor.

Saturation Recovery

When an op amp is over driven output devices can saturate and sometimes take a long time to recover. By clamping the input to safe levels, output saturation can be avoided. If output saturation cannot be avoided, the recovery time from 25% over-drive is 20ns and 30ns from 50% over-drive.

Thermal Management

The HFA-0001 can sink and source a large amount of current making it very useful in many applications. Care must be taken not to exceed the power handling capability of the part to insure proper performance and maintain high reliability. The following graph shows the maximum power handling capability of the HFA-0001 without exceeding the maximum allowable junction temperature of +175oC. The curves also show the improved power handling capability when heatsinks are used based on AVVID heatsink #5801B for the 8 lead Plastic DIP and IERC heatsink #PEP50AB for the 14 lead Sidebraze DIP. These curves are based on natural convection. Forced air will greatly improve the power dissipation capabilities of a heatsink.

FIGURE 34.

+

V- V+

R

R C

C C

C

3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0

POWER DISSIPATION (W)

AMBIENT TEMPERATURE (oC)

20 40 60 80 100 120

A

D B

C

A: 8 LEAD PLASTIC DIP WITH HEATSINK B: 14 LEAD SIDEBRAZE DIP WITH HEATSINK C: 8 LEAD PLASTIC DIP ONLY

D: 14 LEAD SIDEBRAZE DIP ONLY

Cytaty

Powiązane dokumenty

(b) Find the gradient of a line perpendicular to the line segment [AB]... (ii) Write down the coordinates of A

courses, uncharacteristic for the tested elements, what can indicates for the hardware limitations for the highest frequency measurements. Iso- frequency dependencies are

sporządzania mieszanin wykorzystano trzy rodzaje cementu (G – stosowany m.in. w otworach kawernowych w Mogil- nie i Kosakowie oraz CEM II B/V 42,5 i CEM I 52,5 R – ze względu

ta, (2) ogół nieoficjalnych stron stworzonych przez sympatyków kandydata, (3) strony internetowe mediów, gdzie cytuje się wypowiedzi kandydata lub pojawia się fraza z

in Toruń), Zdzisław Kędzia (Adam Mickiewicz University in Poznań), Mária Kiovská (Pavol Jozef Šafárik University in Košice), Cezary Kosikowski (University of Białystok),

Inserted below an integrated coplanar transmission line, the artificial dielectric layer blocks the electric field of the line from entering the silicon substrateI. Shielded

This is explained by the activation of a Cu In ⬙ acceptor state in n-type CuInS 2 and a thermally activated hole trap in p-type CuInS 2..

Decreasing the loss from corona discharge for bundled conductors has an influence on decreasing the noise and interference with radio engineering coming from transmission