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National

Sem iconductor

54LS299/DM74LS299

8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

General Description

The ’LS299 is an 8-bit universal shift/storage register with TRI-STATE® outputs. Four modes of operation are possi­

ble: hold (store), shift left, shift right and load data. The par­

allel load inputs and flip-flop outputs are multiplexed to re­

duce the total number of package pins. Separate outputs are provided for flip-flops QO and Q7 to allow easy cascad­

ing. A separate active LOW Master Reset is used to reset the register.

Features

■ Common I/O for reduced pin count

■ Four operation modes: shift left, shift right, load and store

■ Separate shift right serial input and shift left serial input for easy cascading

■ TRI-STATE outputs for bus oriented applications

Connection Diagram

Dual-ln-Line Package

vcc si

DS7 -Q 7 -1 /0 7 -1 /0 5 -1 /0 3

- 1/01 - C P

— DS0

TL/F/9827-1 Order Number 54LS299DMQB, 54LS299FMQB, 54LS299LMQB, DM74LS299WM or DM74LS299N See NS Package Number E20A, J20A, M20B, N20A or W20A

s o - 1 20

0E1 — 2 19

0E2 — 3 18

I/06 — 4 17

I / 0 4 - 5 16

I/02 — 6 15

1/00 — 7 14

Q0 — 8 13

MR- 9 12

GND — 10 11

Pin Names Description

CP Clock Pulse Input (Active Rising Edge) DS0 Serial Data Input for Right Shift Ds7 Serial Data Input for Left Shift SO, S1 Mode Select Inputs

MR Asynchronous Master Reset Input (Active LOW)

OE1,OE2 TRI-STATE Output Enable Inputs (Active LOW)

I/O 0-I/O 7 Parallel Data Inputs or TRI-STATE Parallel Outputs

Q0-Q7 Serial Outputs

S 29 9

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L S 29 Absolute Maximum Ratings

(Note)

If Military /Aerospace specified devices are required, Note: The "Absolute Maximum Ratings” are those values please contact the National Semiconductor Sales beyond which the safety o f the device cannot be guaran- Office/Distributors for availability and specifications. teed. The device should not be operated a t these limits. The Supply Voltage 7V param etric values defined in the "Electrical Characteristics”

I t voltaae 10V ta^ e are not 9uaranteecf at the absolute maximum ratings.

P 9 The "Recommended Operating Conditions” table w ill define

Operating Free Air Temperature Range //?e conditions for actual device operation.

54 LS — 55°Cto + 125°C

DM74LS 0°C to+70°C

Storage T emperature Range - 65°C to + 1 50°C

Recommended Operating Conditions

Symbol Parameter 54LS299 DM74LS299

Units

Min Norn Max Min Norn Max

Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

V|H High Level Input Voltage 2 2 V

V|L Low Level Input Voltage 0.7 0.8 V

oh High Level Output Current -0 .4 -0 .4 mA

•OL Low Level Output Current 4 8 mA

t a Free Air Operating Temperature - 5 5 125 0 70 °C

ts(H) ts(L)

Setup Time HIGH or LOW SOorSI to CP

24 24

24

24 ns

th(H) th(L)

Hold Time HIGH or LOW SOorSI to CP

5 5

0

0 ns

ts(H) ts(L)

Setup Time HIGH or LOW l/O n, Dso. Ds7 to CP

15 15

10

10 ns

th(H) th(L)

Hold Time HIGH or LOW l/O n, Dso. Ds7 to CP

5 5

0

0 ns

tw(H) tw(L)

CP Pulse Width HIGH or LOW 15 15

15

15 ns

tw(L) MR Pulse Width LOW 15 15 ns

tree Recovery Time

MR to CP 10 10 ns

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ

(Note 1) Max Units

V| Input Clamp Voltage Vcc = Min, l| = “ 18 mA -1 .5 V

VOH High Level Output Voltage

Vcc == Min, Ioh = Max V|l= Max

54 LS 2.5

V

DM74 2.7 3.4

VOL Low Level Output Voltage

Vcc = Min, Iol = Max V|h= Min

54LS 0.4

V

DM74 0.35 0.55

ol = A mA, Vcc = Min DM74 0.25 0.4

•l Input Current @ Max Input Voltage

VCc = Max, V| = 10V Inputs 0.1 mA

Sn 0.2 mA

•lH High Level Input Current VCc = Max, V| = 2.7V Sn 40 juA

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Electrical Characteristics

(continued)

Over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ

(Note 1) Max Units

los Short Circuit

Output Current

Vcc = Max (Note 2)

54 LS - 2 0 -1 0 0

mA

DM74 - 2 0 -1 0 0

Icc Supply Current VCc = Max, OE = 4.5V 60 mA

IOZH TRI-STATE Output Off Current High

Vcc = V CCH

VoZH = 2.7V 40 juA

•OZL TRI-STATE Output Off Current Low

Vcc = V CCH

VqZL “ °-4V -4 0 0 ju,A

Note 1: All typicals are at Vcc = 5V, Ta = 25°C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics

Vcc = +5.0V, Ta = + 25°C (See Section 1 for waveforms and load configurations)

Symbol Parameter RL = 2 k a

CL = 15 pF Units

Min Max

fmax Maximum Input Frequency 35 MHz

tpLH tpHL

Propagation Delay CP to QO or Q7

26

28 ns

tpLH tpHL

Propagation Delay CPtol/O n

25

35 ns

tpHL Propagation Delay

MR to QO or Q7 28 ns

tpHL Propagation Delay

MR to l/O n 35 ns

tpZH tpZL

Output Enable Time 18

25 ns

tpHZ tpLZ

Output Disable Time 15

20 ns

Logic Symbol

11 18

I I

1--- --- 19---

so DS0 DS7

SI

CP Q7

0E MR QO 1/00 1/01 1/02 1/03 1/04 1/05 1/06 1/07

17

2- Cl \

3 - o

L J

? I I I I

9 8 7 13 6 Vcc : GND

I I I I I

14 5 15 4 1(

= Pin 20

= Pin 10

TL/F/9827-2

S 29 9

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L S 29

Functional Description

The ’LS299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by the SO and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. QO and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE1 or OE2 disables the TRI­

STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset opera­

tions can still occur. The TRI-STATE buffers are also dis­

abled by HIGH signals on both SO and S1 in preparation for a parallel load operation.

Mode Select Table Inputs

Response MR S1 SO CP

L X X X Asynchronous Reset; Q0-Q7 = LOW H H H _ /■ Parallel Load; l/O n Qn

H L H Shift Right; Dso QO, QO —► Q1, etc.

H H L Shift Left; DS7 - > Q7, Q7 - * Q6, etc.

H L L X Hold

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

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S 29 9

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