DAC34SH84

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Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

Check for Samples:DAC34SH84

1

FEATURES DESCRIPTION

The DAC34SH84 is a very low-power, high-dynamic

• Low Power: 1.8 W at 1.5 GSPS, Full Operating

range, quad-channel, 16-bit digital-to-analog Condition

converter (DAC) with a sample rate as high as

• Multi-DAC Synchronization 1.5 GSPS.

• Selectable 2×, 4×, 8×, 16× Interpolation Filter

The device includes features that simplify the design – Stop-Band Attenuation > 90 dBc of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band

• Flexible On-Chip Complex Mixing

attenuation simplify the data interface and – Two Independent Fine Mixers With 32-Bit

reconstruction filters. Independent complex mixers

NCOs allow flexible carrier placement. A high-performance

– Power-Saving Coarse Mixers: ±n × f_S/ 8 low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic

• High-Performance, Low-Jitter Clock-

range. The digital quadrature modulator correction Multiplying PLL

(QMC) enables complete IQ compensation for gain,

• Digital I and Q Correction

offset and phase between channels in direct – Gain, Phase and Offset upconversion applications.

• Digital Inverse Sinc Filters

Digital data is input to the device through a 32-bit

• 32-Bit DDR Flexible LVDS Input Data Bus wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth – 8-Sample Input FIFO

signals. The device includes a FIFO, data pattern – Supports Data Rates up to 750 MSPS

checker, and parity test to ease the input interface.

– Data Pattern Checker The interface also allows full synchronization of multiple devices.

– Parity Check

• Temperature Sensor The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C

• Differential Scalable Output: 10 mA to 30 mA

and is available in a 196-ball, 12-mm × 12-mm, 0.8-

• 196-Ball, 12-mm × 12-mm BGA

mm pitch BGA package.

The DAC34SH84 low-power, high-bandwidth support,

APPLICATIONS

superior crosstalk, high dynamic range, and features

• Cellular Base Stations are an ideal fit for next-generation communication

• Diversity Transmit systems.

• Wideband Communications Space

Space Space Space Space Space

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

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100100 PatternTestPatternTest De-interleave 16 16 16

100100

Control Interface Temp

Sensor DCD15P

DCD15N

•

DCD0P

DCD0N

ISTR/PARITYABP PARITYCDP

CD-Data BusAB-Data Bus

ISTR/PARITYABN PARITYCDN

OSTRP

OSTRN

SDO SDIO SDENB SCLK TXENB RESETB

AVDD

GND

LVDS

LVPECL LVDS

LVDS LVDS

8 Sample FIFO

16

ALARM

SLEEP

100

SYNCP

SYNCN LVDS

100100

DAB0P DAB15P

DAB0N DAB15N

LVDS LVDS

Programmable Delay TESTMODE IOVDD

IOVDD2 Complex Mixer (FMIX or CMIX) AB-QMC Gain and Phase _16-b

DACB 16-b DACA

IOUTA1 IOUTA2

IOUTB1 IOUTB2 QMC

B-offset QMC A-offset

x2 x2 x2 x2

FIR1 FIR0

x sin(x)

DAC Gain FIR3

FIR2

AB-Channel

FIR4

2x–16x Interpolation

AB 32-Bit NCO

cos sin

CMIX Control (±n*Fs/8)

59 taps 23 taps 11 taps 11 taps 9 taps

Clock Distribution EXTIO

BIASJ DACCLKP

DACCLKN

DATACLKP

DATACLKN

CLKVDD DIGVDD VFUSE DACVDD

LVPECL

100

LVDS

Programmable Delay

Low Jitter PLL

LPF

PLLAVDD

1.2-V Reference

CD 32-Bit NCO

cos sin

Complex Mixer (FMIX or CMIX) CD-QMC Gain and Phase _16-b

DACD 16-b DACC

IOUTC1 IOUTC2

IOUTD1 IOUTD2 QMC

D-offset QMC C-offset

x2 x2 x2 x2

FIR1 FIR0

x sin(x)

x sin(x) FIR3

FIR2

CD-Channel

FIR4

59 taps 23 taps 11 taps 11 taps 9 taps

B0460-01

FUNCTIONAL BLOCK DIAGRAM

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GND

OSTR N GND

SYNC N

DAB 15N

DAB 14N

DAB 13N

DAB 12N

DAB 11N

DAB 10N

DAB 9N OSTR

P

SYNC P GND

DAC CLKP

DAC CLKN

GND

DAB 15P

DAB 14P

DAB 13P

DAB 12P

DAB 11P

DAB 10P

DAB 9P

GND IOUT AP

IOUT

AN GND IOUT

BN

IOUT

BP GND GND IOUT

CP

IOUT

CN GND IOUT

DN

IOUT

DP GND

GND GND GND GND GND GND GND GND GND GND GND GND

PLL AVDD

LPF GND GND EXTIO BIASJ GND IO

VDD2 GND ALARM SDO

AVDD AVDD AVDD AVDD AVDD AVDD TEST MODE

RESET

B SDENB

AVDD DAC VDD

DAC VDD

DAC

VDD AVDD GND

TXENA SCLK DAC

VDD DAC

GND VDD GND GND DAC

VDD DAC

VDD GND

PLL AVDD

CLK VDD

GND

GND GND

GND

SLEEP SDIO

GND GND GND GND GND GND GND GND GND

VFUSE DIG

GND VDD GND GND DIG

VDD VFUSE GND

GND GND

GND PARITY

CDP

PARITY CDN

DCD 0P

DCD 0N

GND IO

VDD DIG

VDD GND GND GND GND DIG

VDD IO

VDD GND DCD

1P

DCD 1N

GND IO

VDD DIG VDD

DIG VDD

IO VDD

DIG VDD

IO

VDD GND DCD

2P

DCD 2N

DAB 8P

DAB 6P

DAB 8N

DAB 6N

DAB 7P

DAB 5P

DAB 7N

DAB 5N

DAB 4P

DAB 2P

DAB 4N

DAB 2N

DAB 3P

DAB 1P

DAB 3N

DAB 1N

DAB 0P

DAB 0N

DCD 15P

DCD 15N

DCD 14P

DCD 12P

DCD 14N

DCD 12N

DCD 13P

DCD 11P

DCD 13N

DCD 11N

DCD 10P

DCD 8P

DCD 10N

DCD 8N

DCD 9P

DCD 7P

DCD 9N

DCD 7N

DCD 3P

DCD 3N

DCD 4P

DCD 4N

DCD 5P

DCD 5N

DCD 6P

DCD 6N DATA

CLKP

DATA CLKN

ISTR/

PARITY ABP ISTR/

PARITY ABN

A B C D E F G H J K L M N P

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ZAY Package (Top View)

DAC Output

Clock Input

Sync/Parity Input

Data Input

CMOS Pins

Miscellaneous

3.3V Supply

Ground

P0134-01

CLK VDD

1.2V Supply (except for IOVDD2) PINOUT

Submit Documentation Feedback 3

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PIN FUNCTIONS

PIN I/O DESCRIPTION

NAME NO.

D10, E11, F11, G11,

AVDD I Analog supply voltage. (3.3 V)

H11, J11, K11, L10

CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 ALARM N12 O register. Default polarity is active-high, but can be changed to active-low via the config0

alarm_out_pol control bit.

Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩto ground.

BIASJ H12 O Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>.

Internal clock buffer supply voltage. (1.35 V). It is recommended to isolate this supply from DIGVDD

CLKVDD C12, K12 I

and DACVDD.

LVDS positive input data bits 0 through 15 for the AB-channel path. Internal 100-Ωtermination A7, A6, A5,

resistor. Data format relative to DATACLKP/N clock is double data rate (DDR).

A4, A3, A2,

A1, C4, C2, DAB15P is the most-significant data bit (MSB).

DAB[15..0]P D4, D2, E4, I

DAB0P is the least-significant data bit (LSB).

E2, F4, F2,

G4 The order of the bus can be reversed via the config2 revbus bit.

B7, B6, B5, B4, B3, B2,

B1, C3, C1, LVDS negative input data bits 0 through 15 for the AB-channel path. (See the preceding DAB[15:0]P

DAB[15..0]N I

D3, D1, E3, description.) E1, F3, F1,

G3

H4, J4, J2, LVDS positive input data bits 0 through 15 for the CD-channel path. Internal 100-Ωtermination K4, K2, L4, resistor. Data format relative to DATACLKP/N clock is double data rate (DDR).

L2, M4, M2, DCD15P is the most-significant data bit (MSB).

DCD[15..0]P N1, N2, N3, I

DCD0P is the least-significant data bit (LSB).

N4, N5, N6,

The order of the bus can be reversed via the config2 revbus bit.

N7 H3, J3, J1, K3, K1, L3,

L1, M3, M1, LVDS negative input data bits 0 through 15 for the CD-channel path. (See the preceding DCD[15:0]P

DCD[15..0]N I

P1, P2, P3, description.) P4, P5, P6,

P7

DACCLKP A12 I Positive external LVPECL clock input for DAC core with a self-bias

DACCLKN A11 I Complementary external LVPECL clock input for DAC core. (See the DACCLKP description.) D9, E9, E10,

F10, G10, DAC core supply voltage. (1.35 V). It is recommended to isolate this supply from CLKVDD and

DACVDD I

H10, J10, DIGVDD.

K10, K9, L9

LVDS positive input data clock. Internal 100-Ωtermination resistor. Input data DAB[15:0]P/N and

DATACLKP G2 I

DCD[15:0]P/N are latched on both edges of DATACLKP/N (double data rate).

DATACLKN G1 I LVDS negative input data clock. (See the DATACLKP description.) E5, E6, E7,

DIGVDD F5, J5, K5, I Digital supply voltage. (1.3 V). It is recommended to isolate this supply from CLKVDD and DACVDD.

K6, K7

Used as an external reference input when the internal reference is disabled through config27 EXTIO G12 I/O extref_ena = 1. Used as an internal reference output when config27 extref_ena = 0 (default).

Requires a 0.1-μF decoupling capacitor to AGND when used as a reference output.

LVDS input strobe positive input. Internal 100-Ωtermination resistor

The main functions of this input are to sync the FIFO pointer, to provide a sync source to the digital blocks, and/or to act as a parity input for the AB-data bus.

ISTRP/ H2 I These functions are captured with the rising edge of DATACLKP/N. This signal should be edge- PARITYABP

aligned with DAB[15:0]P/N and DCD[15:0]P/N.

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PIN FUNCTIONS (continued)

NAME NO.

A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8,

GND G9, G13, I These pins are ground for all supplies.

G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14

IOUTAP B14 O A-channel DAC current output. Connect directly to ground if unused.

IOUTAN C14 O A-channel DAC complementary current output. Connect directly to ground if unused.

IOUTBP F14 O B-channel DAC current output. Connect directly to ground if unused.

IOUTBN E14 O B-channel DAC complementary current output. Connect directly to ground if unused.

IOUTCP J14 O C-channel DAC current output. Connect directly to ground if unused.

IOUTCN K14 O C-channel DAC complementary current output. Connect directly to ground if unused.

IOUTDP N14 O D-channel DAC current output. Connect directly to ground if unused.

IOUTDN M14 O D-channel DAC complementary current output. Connect directly to ground if unused.

D5, D6, G5,

IOVDD I Supply voltage for all LVDS I/O. (3.3 V) H5, L5. L6

Supply voltage for all CMOS I/O. (1.8 V to 3.3 V) This supply can range from 1.8 V to 3.3 V to change

IOVDD2 L12 I

the input and output levels of the CMOS I/O.

LPF D12 I/O PLL loop filter connection. If not using the clock-multiplying PLL, the LPF pin can be left unconnected.

Optional LVPECL output strobe positive input. This positive-negative pair is captured with the rising OSTRP A9 I edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in dual-

sync-sources mode. If unused it can be left unconnected.

OSTRN B9 I Optional LVPECL output strobe negative input. (See the OSTRP description.)

Optional LVDS positive input parity bit for the CD-data bus. The PARITYCDP/N LVDS pair has an internal 100-Ωtermination resistor. If unused, it can be left unconnected.

PARITYCDP N8 I

The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1.

PARITYCDN P8 I Optional LVDS negative input parity bit for the CD-data bus.

PLLAVDD C11, D11 I PLL analog supply voltage (3.3 V) SCLK P9 I Serial interface clock. Internal pulldown

SDENB P10 I Active-low serial data enable, always an input to the DAC34SH84. Internal pullup

Serial interface data. Bidirectional in 3-pin mode (default) and unidirectional 4-pin mode. Internal

SDIO P11 I/O

pulldown

Unidirectional serial interface data in 4-pin mode. The SDO pin is in the high-impedance state in 3-pin

SDO P12 O

interface mode (default).

SLEEP N11 I Active-high asynchronous hardware power-down input. Internal pulldown

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PIN FUNCTIONS (continued)

NAME NO.

LVDS SYNC positive input. Internal 100-Ωtermination resistor. If unused it can be left unconnected.

SYNCP A8 I The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1.

SYNCN B8 I LVDS SYNC negative input

RESETB N10 I Active-low input for chip RESET. Internal pullup Transmit enable active-high input. Internal pulldown

To enable analog output data transmission, set sif_txenable in register config3 to 1 or pull the CMOS

TXENA N9 I TXENA pin to high.

To disable analog output, set sif_txenable to 0 and pull the CMOS TXENA pin to low. The DAC output is forced to midscale.

TESTMODE L11 I This pin is used for factory testing. Internal pulldown. Leave unconnected for normal operation Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to

VFUSE D7, L7 I

DACVDD or DIGVDD for normal operation

ORDERING INFORMATION⁽¹⁾

T_A ORDER CODE PACKAGE DRAWING/TYPE TRANSPORT MEDIA QUANTITY

DAC34SH84IZAY Tray 160

–40°C to 85°C ZAY / 196 NFBGA

DAC34SH84IZAYR Tape and reel 1000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder atwww.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE MIN MAX UNIT

DACVDD, DIGVDD, CLKVDD –0.5 1.5 V

VFUSE –0.5 1.5 V

Supply voltage

range⁽²⁾ IOVDD, IOVDD2 –0.5 4 V

AVDD, PLLAVDD –0.5 4 V

DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N,

–0.5 IOVDD + 0.5 V

SYNCP/N

DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V

ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE,

–0.5 IOVDD2 + 0.5 V

Pin voltage range⁽²⁾ TXENA

IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N –1.0 AVDD + 0.5 V

EXTIO, BIASJ –0.5 AVDD + 0.5 V

LPF –0.5 PLLAVDD + 0.5 V

Peak input current (any input) 20 mA

Peak total input current (all inputs) –30 mA

Absolute maximum junction temperature, TJ 150 °C

Storage temperature range, T_stg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND

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THERMAL INFORMATION

DAC34SH84

THERMAL METRIC⁽¹⁾ BGA UNIT

(196 ball) PINS

θ_JA Junction-to-ambient thermal resistance⁽²⁾ 37.6 °C/W

θJCtop Junction-to-case (top) thermal resistance⁽³⁾ 6.8 °C/W

θJCbot Junction-to-case (bottom) thermal resistance⁽⁴⁾ N/A °C/W

θ_JB Junction-to-board thermal resistance⁽⁵⁾ 16.8 °C/W

ψ_JT Junction-to-top characterization parameter⁽⁶⁾ 0.2 °C/W

ψ_JB Junction-to-board characterization parameter⁽⁷⁾ 16.4 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(6) The junction-to-top characterization parameter,ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtainingθ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-board characterization parameter,ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtainingθ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Recommended operating junction temperature 105

T_J °C

Maximum rated operating junction temperature⁽¹⁾ 125

T_A Recommended free-air temperature –40 25 85 °C

(1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.

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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS⁽¹⁾

over recommended operating free-air temperature range, nominal supplies, IOUT_FS= 20 mA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 16 Bits

DC ACCURACY

DNL Differential nonlinearity ±2 LSB

1 LSB = IOUTFS/ 2¹⁶

INL Integral nonlinearity ±4 LSB

ANALOG OUTPUT

Coarse gain linearity ±0.04 LSB

Offset error Mid-code offset ±0.001 %FSR

With external reference ±2 %FSR

Gain error

With internal reference ±2 %FSR

Gain mismatch With internal reference ±2 %FSR

Full-scale output current 10 20 30 mA

Output compliance range –0.5 0.6 V

Output resistance 300 kΩ

Output capacitance 5 pF

REFERENCE OUTPUT

V_REF Reference output voltage 1.2 V

Reference output current⁽²⁾ 100 nA

REFERENCE INPUT

VEXTIO Input voltage range 0.6 1.2 1.25 V

External reference mode

Input resistance 1 MΩ

Small-signal bandwidth 472 kHz

Input capacitance 100 pF

TEMPERATURE COEFFICIENTS

Offset drift ±1 ppm / °C

With external reference ±15 ppm / °C

Gain drift

With internal reference ±30 ppm / °C

Reference voltage drift ±8 ppm / °C

POWER SUPPLY⁽³⁾

AVDD, IOVDD, PLLAVDD 3.14 3.3 3.46 V

DIGVDD 1.25 1.3 1.35 V

CLKVDD, DACVDD 1.3 1.35 1.4 V

IOVDD2 1.71 3.3 3.45 V

PSRR Power-supply rejection ratio DC tested ±0.25 %FSR / V

(1) Measured differentially across IOUTP/N with 25Ωeach to GND.

(2) Use an external buffer amplifier with high-impedance input to drive any external load.

(3) To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended.

(9)

ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (continued)

POWER CONSUMPTION

I_(AVDD) Analog supply current⁽⁴⁾ 135 165 mA

Mode 1

I_(DIGVDD) Digital supply current 885 950 mA

f_DAC= 1.5 GSPS, 2× interpolation,

I(DACVDD) DAC supply current 45 60 mA

mixer on, QMC on, invsinc on,

I(CLKVDD) Clock supply current PLL enabled, 20-mA FS output, IF = 200 MHz 127 145 mA

P Power dissipation 1828 2056 mW

I_(AVDD) Analog supply current⁽⁴⁾ 115 mA

Mode 2

I_(DIGVDD) Digital supply current 770 mA

f_DAC= 1.47456 GSPS, 2× interpolation,

I(DACVDD) DAC supply current 40 mA

mixer on, QMC on, invsinc on,

I(CLKVDD) Clock supply current PLL disabled, 20-mA FS output, IF = 7.3 MHz 95 mA

P Power dissipation 1562 mW

Mode 3

f_DAC= 737.28 MSPS, 2x interpolation,

mixer on, QMC on, invsinc off,

Mode 4

I_(DIGVDD) Digital supply current f_DAC= 1.47456 GSPS, 2× interpolation, 710 mA

I(DACVDD) DAC supply current mixer on, QMC on, invsinc on, 50 mA

PLL enabled, IF = 7.3 MHz, channels A/B/C/D

I(CLKVDD) Clock supply current 90 mA

output sleep

Mode 5

I_(DIGVDD) Digital supply current Power-down mode: no clock, DAC on sleep 17 mA

I(DACVDD) DAC supply current mode (clock receiver sleep), 0 mA

channels A/B/C/D output sleep, static data

pattern

Mode 6

f_DAC= 1 GSPS, 2x interpolation,

mixer off, QMC off, invsinc off,

I(CLKVDD) Clock supply current PLL enabled, 20-mA FS output, IF = 7.3 MHz 98 mA

P Power dissipation 1336 mA

Mode 7

f_DAC= 1 GSPS, 2x interpolation,

mixer off,QMC off, invsinc off,

Mode 8

I_(DIGVDD) Digital supply current f_DAC= 1.47456 GSPS, 2× interpolation, 655 mA

I(DACVDD) DAC supply current mixer on, QMC on, invsinc on, 30 mA

PLL disabled, IF = 7.3 MHz, channels A/B/C/D

output sleep

(4) Includes AVDD, PLLAVDD, and IOVDD

(10)

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS

over operating free-air temperature range (unless otherwise noted)

LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N⁽¹⁾ Logic-high differential

VA,B+ input voltage 200 mV

threshold

Logic-low differential

V_A,B– input voltage –200 mV

threshold

VCOM Input common mode 1 1.2 1.6 V

ZT Internal termination 85 110 135 Ω

LVDS input

C_L 2 pF

capacitance Interleaved LVDS

f_INTERL 1500 MSPS

data transfer rate

f_DATA Input data rate 750 MSPS

CLOCK INPUT (DACCLKP/N)

Duty cycle 40% 60%

Differential voltage⁽²⁾ |DACCLKP - DACCLKN| 0.4 1 V

Internally biased

common-mode 0.2 V

voltage

Single-ended swing

–0.4 V

level

DACCLKP/N input

1500 MHz frequency

OUTPUT STROBE (OSTRP/N)

f_OSTR= f_DACCLK/ (n × 8 × interp) where n is any positive f_DACCLK/

fOSTR Frequency integer, (8× MHz

f_DACCLKis DACCLK frequency in MHz interp)

Duty cycle 50%

Differential voltage |OSTRP-OSTRN| 0.4 1.0 V

Internally biased

common-mode 0.2 V

voltage

Single-ended swing –0.4 V

level

CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA

High-level input 0.7 ×

V_IH V

voltage IOVDD2

Low-level input 0.3 ×

VIL voltage IOVDD2 V

High-level input

I_IH –40 40 µA

current Low-level input

I_IL –40 40 µA

current CMOS input

CI capacitance 2 pF

IOVDD2 –

Iload= –100μA V

VOH ALARM, SDO, SDIO 0.2

0.8 ×

I_load= –2 mA V

IOVDD2

(11)

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)

DIGITAL INPUT TIMING SPECIFICATIONS

Timing LVDS inputs: DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, PARITYCDP/N, double edge latching Config36 Setting

datadly clkdly

0 0 30

0 1 –10

0 2 –50

0 3 –90

Setup time, 0 4 –130

DAB[15:0]P/N,

0 5 –170

DCD[15:0]P/N,

ISTRP/N and SYNCP/N reset latched

t_s(DATA) ISTRP/N, SYNCP/N, 0 6 –210 ps

only on rising edge of DATACLKP/N

and PARITYCDP/N, 0 7 –250

valid to either edge of

1 0 50

DATACLKP/N

2 0 90

3 0 130

4 0 170

5 0 210

6 0 250

7 0 290

Config36 Setting datadly clkdly

0 0 200

0 1 240

0 2 280

0 3 320

Hold time, 0 4 360

DAB[15:0]P/N,

0 5 400

DCD[15:0]P/N,

ISTRP/N and SYNCP/N reset latched

t_h(DATA) ISTRP/N, SYNCP/N 0 6 440 ps

only on rising edge of DATACLKP/N and PARITYCDP/N

0 7 480

valid after either edge

1 0 190

of DATACLKP/N

2 0 150

3 0 110

4 0 70

5 0 30

6 0 –10

7 0 –50

ISTRP/N and

t(ISTR_SYNC) SYNCP/N pulse fDATACLKis DATACLK frequency in MHz 2f_DATACLK1 / ns

duration

(12)

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)

TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING⁽³⁾ Setup time, OSTRP/N

ts(OSTR) valid to rising edge of –80 ps

DACCLKP/N Hold time, OSTRP/N

t_h(OSTR) valid after rising edge 220 ps

of DACCLKP/N

TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING⁽⁴⁾ Setup time, SYNCP/N

ts(SYNC_PLL) valid to rising edge of 150 ps

DACCLKP/N Hold time, SYNCP/N

th(SYNC_PLL) valid after rising edge 250 ps

of DACCLKP/N TIMING SERIAL PORT

Setup time, SDENB to

ts(SDENB) rising edge of SCLK 20 ns

Setup time, SDIO

ts(SDIO) valid to rising edge of 10 ns

SCLK

Hold time, SDIO valid

th(SDIO) to rising edge of 5 ns

SCLK

Register config6 read (temperature sensor read) 1 µs

t(SCLK) Period of SCLK

All other registers 100 ns

Data output delay

t_d(Data) after falling edge of 10 ns

SCLK

Minimum RESETB

t_RESET 25 ns

pulsewidth PHASE-LOCKED LOOP

PLL_vco = 011110 (30) 2940 2957

PLL_vco = 100010 (34) 2957 3000

PLL_vco = 100110 (38) 3000 3043

PLL_vco = 101010 (42) 3034 3086

PLL/VCO operating

PLL_vco = 101110 (46) 3069 3120 MHz

frequency

PLL_vco = 110010 (50) 3103 3163

PLL_vco = 110110 (54) 3128 3215

PLL_vco = 111010 (58) 3170 3257

PLL_vco = 111111 (63) 3215 3300

(3) OSTR is required in dual-sync-sources mode. In order to minimize the skew, it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC34SH84 devices in the system.

Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.

(4) SYNC is required to synchronize the PLL circuit in mulitple devices. The SYNC signal must meet the timing relationship with respect to the reference clock (DACCLKP/N) of the on-chip PLL circuit.

(13)

ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS

PARAMETER TEST CONDITIONS / COMMENTS MIN TYP MAX UNIT

ANALOG OUTPUT⁽¹⁾

fDAC Maximum DAC rate 1500 MSPS

ts(DAC) Output settling time to 0.1% Transition: code 0x0000 to 0xFFFF 10 ns

DAC outputs are updated on the falling edge of the DAC

t_pd Output propagation delay 2 ns

clock. Does not include digital latency (see following).

tr(IOUT) Output rise time 10% to 90% 220 ps

tf(IOUT) Output fall time 90% to 10% 220 ps

No interpolation, FIFO on, mixer off, QMC off, inverse sinc off 128

2× interpolation 216

DAC clock

Digital latency

cycles

Fine mixer 24

QMC 16

Inverse sinc 20

DAC wake-up time IOUT current settling to 1% of IOUTFSfrom output sleep 2 Power-up

IOUT current settling to less than 1% of IOUTFSin output μs

time DAC sleep time 2

sleep AC PERFORMANCE⁽²⁾

fDAC= 1.5 GSPS, fOUT= 20 MHz 78

Spurious-free dynamic range,

SFDR fDAC= 1.5 GSPS, fOUT= 50 MHz 74 dBc

(0 to fDAC/ 2) tone at 0 dBFS

f_DAC= 1.5 GSPS, f_OUT= 30 ± 0.5 MHz 87

Third-order two-tone intermodulation distortion,

IMD3 fDAC= 1.5 GSPS, fOUT= 50 ± 0.5 MHz 85 dBc

each tone at –12 dBFS fDAC= 1.5 GSPS, fOUT= 100 ± 0.5 MHz 78

f_DAC= 1.5 GSPS, f_OUT= 10 MHz 160

Noise spectral density,⁽³⁾

NSD dBc / Hz

tone at 0 dBFS fDAC= 1.5 GSPS, fOUT= 80 MHz 158

Adjacent-channel leakage ratio, single

carrier f_DAC= 1.47456 GSPS, f_OUT= 153 MHz 75

ACLR⁽³⁾ dBc

Alternate-channel leakage ratio, single

carrier fDAC= 1.47456 GSPS, fOUT= 153 MHz 82

Channel isolation fDAC= 1.5 GSPS, fOUT= 40 MHz 101 dBc

(1) Measured single-ended into 50-Ωload.

(2) 4:1 transformer output termination, 50-Ωdoubly terminated load

(3) Single carrier, W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, PAR = 12 dB. TESTMODEL 1, 10 ms

(14)

30 40 50 60 70 80 90 100 110

0 100 200 300 400 500 600

Output Frequency (MHz)

Third−Order Harmonic Distortion (dB)

0dBFS

−6dBFS

−12dBFS

G005

30 40 50 60 70 80 90 100 110

0 100 200 300 400 500 600

SFDR (dBc)

FDAC = 750 MSPS, 1x interpolation FDAC = 1500 MSPS, 2x interpolation FDAC = 1500 MSPS, 4x interpolation FDAC = 1500 MSPS, 8x interpolation FDAC = 1500 MSPS, 16x interpolation

G006

10 20 30 40 50 60 70 80 90

0 100 200 300 400 500 600

Output Frequency (dB)

SFDR (dBc)

0dBFS

−6dBFS

−12dBFS

G003

20 30 40 50 60 70 80 90 100

0 100 200 300 400 500 600

Second Order Harmonic Distortion (dB)

0dBFS

−6dBFS

−12dBFS

G004

−6

−5

−4

−3

−2

−1 0 1 2 3 4 5 6

0 10k 20k 30k 40k 50k 60k

Code

Integral Nonlinearity Error (LSB)

−5

−4

−3

−2

−1 0 1 2 3 4 5

0 10k 20k 30k 40k 50k 60k

Code

Differential Nonlinearity Error (LSB)

TYPICAL CHARACTERISTICS

All plots are at 25°C, nominal supply voltage, f_DAC= 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer

(unless otherwise noted)

Figure 1. Integral Nonlinearity Figure 2. Differential Nonlinearity

Figure 3. SFDR vs Output Frequency Over Input Scale Figure 4. Second-Harmonic Distortion vs Output Frequency Over Input Scale

Figure 5. Third Harmonic Distortion vs Output Frequency Figure 6. SFDR vs Output Frequency Over Interpolation Over Input Scale

(15)

−90

−80

−70

−60

−50

−40

−30

−20

−10 0 10

10 110 210 310 410 510 610 710 800

Frequency (MHz)

Power (dBm)

fDAC = 1500 MSPS fout = 150 MHz

G011

−90

−80

−70

−60

−50

−40

−30

−20

−10 0 10

10 110 210 310 410 510 610 710 800

Frequency (MHz)

Power (dBm)

fDAC = 1500 MSPS fout = 200 MHz

G012

−90

−80

−70

−60

−50

−40

−30

−20

−10 0 10

10 110 210 310 410 510 610 710 800

Frequency (MHz)

Power (dBm)

NCO bypassed QMC bypassed fDAC = 1500 MSPS fout = 20 MHz

G009

−90

−80

−70

−60

−50

−40

−30

−20

−10 0 10

10 110 210 310 410 510 610 710 800

Frequency (MHz)

Power (dBm)

NCO bypassed QMC bypassed fDAC = 1500 MSPS fout = 70 MHz

G010

20 30 40 50 60 70 80 90 100

0 100 200 300 400 500

SFDR (dBc)

fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1200 MSPS fDAC = 1500 MSPS

G007

20 30 40 50 60 70 80 90 100

0 100 200 300 400 500

SFDR (dBc)

Iout FS = 10 mA, 4:1 Transformer Iout FS = 20 mA, 4:1 Transformer Iout FS = 30 mA, 2:1 Transformer

G008

TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, nominal supply voltage, f_DAC= 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted)

Figure 7. SFDR vs Output Frequency Over f_DAC Figure 8. SFDR vs Output Frequency Over I_OUTFS

Figure 9. Single-Tone Spectral Plot Figure 10. Single-Tone Spectral Plot

Figure 11. Single-Tone Spectral Plot Figure 12. Single-Tone Spectral Plot