MOS FIELD EFFECT TRANSISTOR
2SJ598
SWITCHING
P-CHANNEL POWER MOS FET
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Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
DESCRIPTION
The 2SJ598 is P-channel MOS Field Effect Transistor designed for solenoid, motor and lamp driver.
FEATURES
• Low on-state resistance:
RDS(on)1 = 130 mΩ MAX. (VGS = –10V, ID = –6A) RDS(on)2 = 190 mΩ MAX. (VGS = –4.0V, ID = –6 A)
• Low Ciss: Ciss = 720 pF TYP.
• Built-in gate protection diode
• TO-251/TO-252 package
ABSOLUTE MAXIMUM RATINGS (T
A= 25°C)
Drain to Source Voltage (VGS = 0V) VDSS –60 V Gate to Source Voltage (VDS = 0V) VGSS m20 V Drain Current (DC) (TC = 25°C) ID(DC) m12 A Drain Current (pulse) Note1 ID(pulse) m30 A Total Power Dissipation (TC = 25°C) PT 23 W Total Power Dissipation(TA = 25°C) PT 1.0 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg –55 to +150 °C
Single Avalanche Current Note2 IAS –12 A
Single Avalanche Energy Note2 EAS 14.4 mJ
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = –30 V, RG = 25 Ω, VGS = –20 → 0 V
ORDERING INFORMATION
PART NUMBER PACKAGE
2SJ598 TO-251
2SJ598-Z TO-252
(TO-251)
(TO-252)
ELECTRICAL CHARACTERISTICS (T
A= 25°C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Zero Gate Voltage Drain Current IDSS VDS = –60V, VGS = 0V –10 µA
Gate Leakage Current IGSS VGS = m16V, VDS = 0V m10 µA
Gate Cut-off Voltage VGS(off) VDS = –10V, ID = –1mA –1.5 –2.0 –2.5 V
Forward Transfer Admittance | yfs| VDS = –10V, ID = –6A 5 11 S
Drain to Source On-state Resistance RDS(on)1 VGS = –10V, ID = –6A 102 130 mΩ
RDS(on)2 VGS = –4.0V, ID = –6A 131 190 mΩ
Input Capacitance Ciss VDS = –10V 720 pF
Output Capacitance Coss VGS = 0V 150 pF
Reverse Transfer Capacitance Crss f = 1MHz 50 pF
Turn-on Delay Time td(on) ID = –6A 7 ns
Rise Time tr VGS = –10V 4 ns
Turn-off Delay Time td(off) VDD = –30V 35 ns
Fall Time tf RG = 0Ω 10 ns
Total Gate Charge QG ID = –12A 15 nC
Gate to Source Charge QGS VDD= –48V 3 nC
Gate to Drain Charge QGD VGS = –10V 4 nC
Body Diode Forward Voltage VF(S-D) IF = 12A, VGS = 0V 0.98 V
Reverse Recovery Time trr IF = 12A, VGS = 0V 50 ns
Reverse Recovery Charge Qrr di/dt = 100A/µs 100 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
RG = 25 Ω PG 50 Ω
L
VDD
VGS = –20 → 0 V
BVDSS
IAS
ID
VDS
Starting Tch
VDD
D.U.T.
TEST CIRCUIT 3 GATE CHARGE
TEST CIRCUIT 2 SWITCHING TIME
PG. RG
0 VGS (−)
D.U.T.
RL
VDD
τ = 1 sµ Duty Cycle ≤ 1%
VGS Wave Form
VDS Wave Form
VGS (−) 10%
VGS 90%
0 10%
VDS (−)
90%
90%
td(on) tr td(off) t f 10%
τ
VDS
0
ton toff
PG. 50 Ω
D.U.T.
RL
VDD
IG = −2 mA
−
★
★
TYPICAL CHARACTERISTICS (T
A= 25°C )
TC - Case Temperature - ˚C
PT - Total Power Dissipation - W
0 20 40 60 80 100 120 140 160 TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE 30
25
20
15
10
5
0
FORWARD BIAS SAFE OPERATING AREA
ID - Drain Current - A
VDS - Drain to Source Voltage - V –1
–10 –100
–0.1 –1 –10
TC = 25˚C Single Pulse –0.1
–100
Power D issipation Lim
ited RDS(
on) Lim ited ID(DC)
ID(pulse) PW = 10 µs 100
µs 1 m 10 ms s DC
DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA
TC - Case Temperature - ˚C
dT - Percentage of Rated Power - %
0 20 40 60 80 100 120 140 160 100
80
60
40
20
0
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
10
0.01 0.1 1 100 1000
1 m 10 m 100 m 1 10 100 1000
Single Pulse
10 100
Rth(ch-C) = 5.43˚C/W
µ µ
Rth(ch-A) = 125˚C/W
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
0 –5 –10 –15 –20
Pulsed 200
150
100
50
0
ID = –6 A FORWARD TRANSFER CHARACTERISTICS
VGS - Gate to Source Voltage - V
ID - Drain Current - A
Pulsed
–1 –2 –3 –4 –5
VDS = –10 V –10
–1
–0.1 –100
TA = −55˚C 25˚C 75˚C 150˚C
–0.01
DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT
ID - Drain Current - A
RDS(on) - Drain to Source On-state Resistance - mΩ
–1 –0.1
300
200
100
0
–10 –100
Pulsed
VGS = –4.0 V –4.5 V –10 V
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
VDS - Drain to Source Voltage - V
ID - Drain Current - A
0 –4 –6 –8
–50
–40
–30
–20
–10
0 –2
Pulsed VGS = –10 V
–10 –4.0 V
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
ID - Drain Current - A
| yfs | - Forward Transfer Admittance - S
–0.01 –0.1 –1
10 100
–10 –100
0.1 1
Pulsed VDS = –10 V TA = 150˚C 75˚C 25˚C −50˚C
0.01
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
Tch - Channel Temperature - ˚C
VGS(off) - Gate Cut-off Voltage - V
VDS = –10 V ID = –1 mA
–1.0 –2.0 –3.0
–50 0 50 100
0 150
–4.0
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
Tch - Channel Temperature - ˚C
RDS(on) - Drain to Source On-state Resistance - mΩ
−50 0 50 100 150
ID = –6 A 300
250
200
150
100
50
0
–10 V VGS = –4.0 V Pulsed
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
–1.0
ISD - Diode Forward Current - A
0 –1.5
VSD - Source to Drain Voltage - V –0.5
Pulsed
–0.01 –0.1 –1 –10 –100
0 V VGS = –10 V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
VGS - Gate to Source Voltage - V
QG - Gate Charge - nC
VDS - Drain to Source Voltage - V
0 2 4 6 8 10 12 14 16
–60
–50
–40
–30
–20
–10
0
VDS
VGS
VDD = –48 V –30 V –12 V
ID = –12 A –12 –10
–8
–6
–4
–2
0 REVERSE RECOVERY TIME vs.
DRAIN CURRENT
IF - Drain Current - A
trr - Reverse Recovery Time - ns
di/dt = 100 A/ s VGS = 0 V
1 0.1 10
1 10 100
1000
100
µ CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
VDS - Drain to Source Voltage - V
Ciss, Coss, Crss - Capacitance - pF
10 100 1000 10000
–0.1 –1 –10
VGS = 0 V f = 1 MHz
Coss
Crss
Ciss
–100
SWITCHING CHARACTERISTICS
ID - Drain Current - A
td(on), tr, td(off), tf - Switching Time - ns
10
1
–1 –0.1
100 1000
–10 –100
tf
tr
td(on)
td(off)
VDD = –30 V RG = 0 Ω VGS = –10 V
SINGLE AVALANCHE ENERGY DERATING FACTOR
Starting Tch - Starting Channel Temperature - ˚C
Energy Derating Factor - %
25 50 75 100
160 140 120 100 80 60 40 20
0 125 150
VDD = –30 V RG = 25 Ω VGS = –20 → 0 V IAS ≤ –12 A SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
L - Inductive Load - H
IAS - Single Avalanche Current - A
–1 –10 –100
1 m 10 m
VDD = –30 V RG = 25 Ω VGS = –20 → 0V
IAS = –12 A
10µ 100µ
–0.1
EAS = 14.4 mJ
PACKAGE DRAWINGS (Unit : mm)
1) TO-251 (MP-3)
1.Gate 2.Drain 3.Source 4.Fin (Drain) 2
1 3
6.5±0.2 5.0±0.2 4
1.5-0.1+0.2 5.5±0.27.0 MAX. 13.7 MIN.
2.3 2.3
0.75
0.5±0.1 2.3±0.2
1.6±0.2
1.1±0.2
0.5-+0.20.1
0.5-+0.20.1
2) TO-252 (MP-3Z)
1. Gate 2. Drain 3. Source 4. Fin (Drain)
1 2 3
4 6.5±0.2 5.0±0.2
4.3 MAX.0.8
2.3 2.3 0.9 MAX.
5.5±0.2 10.0 MAX.
2.0 MIN.
1.5-0.1+0.2 2.3±0.2 0.5±0.1
0.8 MAX.
0.8 1.0 MIN. 1.8 TYP.0.7
1.1±0.2
EQUIVALENT CIRCUIT
Source Body Diode
Gate Protection Diode Gate
Drain
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
M8E 00. 4
The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.
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