DG406-883

Features

• This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.

• ON-Resistance 100Ω (Max)

• Low Power Consumption (P

_D

<1.2mW)

• Fast Transition Time (300ns Max)

• Low Charge Injection

• TTL, CMOS Compatible

• Single or Split Supply Operation

Applications

• Battery Operated Systems

• Data Acquisition

• Medical Instrumentation

• Hi-Rel Systems

• Communication Systems

• Automatic Test Equipment

Description

The DG406/883 and DG407/883 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A/883 and DG507A/883 series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selec- tion, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplex- ers are present.

These multiplexers feature lower signal ON resistance (<100Ω) and faster transition time (t

_TRANS

<250ns) compared to the DG506A/883 and DG507A/883. Charge injection has been reduced, simplifying sample and hold applications.

The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technolo- gies. The 44V maximum voltage range permits controlling 30V

_P-P

signals when operating with ±15V power supplies.

The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range.

Pinouts

Ordering Information

PART NUMBER

TEMP. RANGE

(^oC) PACKAGE

PKG.

NO.

DG406AK/883 -55 to 125 28 Ld CERDIP F28.6 DG407AK/883 -55 to 125 28 Ld CERDIP F28.6

DG406/883 (CERDIP) TOP VIEW

DG407/883 (CERDIP) TOP VIEW

V+

NC NC S₁₆ S₁₅ S₁₄ S₁₃ S₁₂ S₁₁ S₁₀ S₉ GND NC A₃

D

S₈ S₇ S₆ S₅

S₃

S₁ EN A₀ A₁ A₂ V-

S₄

S₂ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1

2 3 4 5 6 7 8 9 10 11 12 13 14

V+

D_B NC S_8B S_7B S_6B S_5B S_4B S_3B S_2B S_1B GND NC NC

D_A

S_8A S_7A S_6A S_5A

S_3A

S_1A EN A₀ A₁ A₂ V-

S_4A

S_2A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1

2 3 4 5 6 7 8 9 10 11 12 13 14

April 1997

DG406/883, DG407/883

Single 16-Channel/Differential

8-Channel CMOS Analog Multiplexers

Functional Block Diagrams

DG406 DG407

DG406 TRUTH TABLE

A₃ A₂ A₁ A₀ EN ON SWITCH

X X X X 0 None

0 0 0 0 1 1

0 0 0 1 1 2

0 0 1 0 1 3

0 0 1 1 1 4

0 1 0 0 1 5

0 1 0 1 1 6

0 1 1 0 1 7

0 1 1 1 1 8

1 0 0 0 1 9

1 0 0 1 1 10

1 0 1 0 1 11

1 0 1 1 1 12

1 1 0 0 1 13

1 1 0 1 1 14

1 1 1 0 1 15

1 1 1 1 1 16

S₁ S₂ S₃ S₄ S₅ S₆ S₇ S₈ S₉ S₁₀ S₁₁ S₁₂ S₁₃ S₁₄ S₁₅ S₁₆

D

TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING

ADDRESS DECODER

1 OF 16 ENABLE

A₀ A₁ A₂ A₃ EN

DG407 TRUTH TABLE

A₂ A₁ A₀ EN ON SWITCH PAIR

X X X 0 None

0 0 0 1 1

0 0 1 1 2

0 1 0 1 3

0 1 1 1 4

1 0 0 1 5

1 0 1 1 6

1 1 0 1 7

1 1 1 1 8

Logic “0” = V_AL < 0.8V Logic “1” = V_AH > 2.4V X = Don’t Care

S_2A S_3A S_4A S_5A S_6A S_7A S_8A

S_1B S_2B S_3B S_4B S_5B S_6B S_7B S_8B

D_A

TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING

ADDRESS DECODER

1 OF 8 ENABLE

A₀ A₁ A₂ EN

S_1A

D_B

Absolute Maximum Ratings Thermal Information

Voltages Referenced to V-

V+ . . . +44.0V GND . . . 25V Digital Inputs, V_S, V_D (Note 1) . . . (V-) -2V to (V+) +2V or 20mA, Whichever Occurs First Current (Any Terminal) . . . 30mA Peak Current, S or D . . . 100mA

(Pulsed 1ms, 10% Duty Cycle Max)

Operating Conditions

Temperature Range . . . -55^oC to 125^oC

Thermal Resistance (Typical, Note 2)

θ

JA (^oC/W)

θ

JC (^oC/W) CERDIP Package . . . 55 12 Maximum Junction Temperature. . . 150^oC Maximum Storage Temperature Range . . . -65^oC to 150^oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Signals on S_X, D_X or IN_X exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.

2. θ_JA is measured with the component mounted on an evaluation PC board in free air.

TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +V_SUPPLY = +15V, -V_SUPPLY = -15V, V_AL = 0.8V, V_AH = 2.4V, Unless Otherwise Specified

PARAMETER SYMBOL CONDITIONS

GROUP A SUB- GROUP

DEVICE TYPE

(NOTE 3) MIN

(NOTE 3)

MAX UNITS Drain-Source ON Resistance r_DS(ON) V_D = 10V, I_S = -10mA

VD = -10V, IS = 10mA (Note 4)

1, 3 All - 90 Ω

2 All - 120 Ω

Matching Between Channels ∆r_DS(ON) r_DS(ON) Max - r_DS(ON) Min (Note 3)

1 All - 15 Ω

Source OFF Leakage Current I_S(OFF) V_EN = 0V, V_S = ±10V, V_D = +10V

1 All -0.5 0.5 nA

2, 3 All -50 50 nA

Drain OFF Leakage Current I_D(OFF) V_EN = 0V, V_S = ±10V, V_D = +10V

DG406 1 DG406 -1 1 nA

2, 3 -200 200 nA

DG407 1 DG407 -1 1 nA

2, 3 -100 100 nA

Drain ON Leakage Current I_D(ON) V_S = V_D = ±10V

Sequence Each Switch ON (Note 4)

DG406 1 DG406 -1 1 nA

2, 3 -200 200 nA

DG407 1 DG407 -1 1 nA

2, 3 -100 100 nA

Logic High Input Current I_AH V_A = 2.4V, 15V 1, 2, 3 All -1 1 µA

Logic Low Input Current I_AL V_EN = 0V, 2.4V, V_A = 0V 1, 2, 3 All -1 1 µA

Positive Supply Current I_CC V_EN = 2.4V, V_A = 0V 1 All - 100 µA

2, 3 All - 500 µA

Negative Supply Current I_EE 1 All -1 - µA

2, 3 All -10 - µA

Positive Standby Current I_CC Standby

V_EN = V_A = 0V or 5V 1 All - 30 µA

2, 3 All - 75 µA

Negative Standby Current I_EE Standby

1 All -1 - µA

2, 3 All -10 - µA

NOTES:

3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

4. Room = 25^oC, Cold and Hot = as determined by the operating temperature suffix.

TABLE 1A. ELECTRICAL PERFORMANCE SPECIFICATIONS (SINGLE SUPPLY) Devices tested at +V_SUPPLY = +12V, -V_SUPPLY = 0V, V_AL = 0.8V, V_AH = 2.4V, Unless Otherwise Specified

PARAMETER SYMBOL CONDITIONS

GROUP A SUB- GROUP

DEVICE

TYPE MIN MAX UNITS

Drain-Source ON Resistance r_DS(ON) V_D = 3V, 10V IS = -1mA

1 All - 120 Ω

Positive Current I_CC V_EN = 0V or 5V,

V_A = 0V or 5V

1 All - 30 µA

2, 3 All - 75 µA

Negative Current I_EE 1 All -1 - µA

2, 3 All -5 - µA

Switching Time of Multiplexer t_TRANS V_S1 = 8V, V_SS - 0V, V_IN = 2.4V

1 All - 450 ns

Enable Turn-ON Time t_ON(EN) V_INH = 2.4V, V_INL = 0V,

V_S1 = 5V 1 All - 600 ns

Enable Turn-OFF Time t_OFF(EN) 1 All - 300 ns

TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Devices tested at +V_SUPPLY = +15V, -V_SUPPLY = -15V, V_AL = 0.8V, V_AH = 2.4V, Unless Otherwise Specified (Continued)

PARAMETER SYMBOL CONDITIONS

GROUP A SUB- GROUP

DEVICE TYPE

(NOTE 3) MIN

(NOTE 3)

MAX UNITS

TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +V_SUPPLY = +15V, -V_SUPPLY = -15V, V_AL = 0.8V, V_AH = 2.4V, Unless Otherwise Specified

PARAMETER SYMBOL CONDITIONS

GROUP A SUB- GROUP

DEVICE

TYPE MIN MAX UNITS

Transition Time t_TRANS C_L = 35pF, R_L = 300Ω, See Figure 1

9 All - 300 ns

10, 11 All - 400 ns

Enable Turn-ON Time t_ON(EN) C_L = 35pF, R_L = 300Ω, See Figure 2

9 All - 200 ns

10, 11 All - 400 ns

Enable Turn-OFF Time t_OFF(EN) 9 All - 150 ns

10, 11 All - 300 ns

Break Before Leakage Current t_OPEN C_L = 35pF, R_L = 300Ω, See Figure 3

9 All 25 - ns

10, 11 All 10 - ns

TABLE 3. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +V_SUPPLY = +15V, -V_SUPPLY = -15V, V_AL = 0.8V, V_AH = 2.4V, Unless Otherwise Specified

PARAMETER SYMBOL CONDITIONS NOTE TEMP (^oC) MIN TYP MAX UNITS

Off Isolation Time V_ISO V_EN = 0V, R_L = 1K, f = 100kHz, GEN = 1VP-P Sine Wave, See Figure 5

5 25 50 - - dB

Charge Transfer Error V_CTE C_L = 10nF, V_S = 0V, R_S = 0Ω, See Figure 4

5 25 - - 10 mV

Crosstalk V_CT R_L = 1K, f = 100kHz,

GEN = 1V_P-P Sine Wave, See Figure 5

5 25 50 - - dB

Source OFF Capacitance C_S(OFF) V_EN = 0V, V_S = 0V, f = 1MHz 65 25 - - 10 pF

Drain OFF Capacitance C_D(OFF) V_EN = 0V, V_D = 0V, f = 1MHz

DG406 5 25 - - 200 pF

DG407 5 25 - - 100 pF

Drain ON Capacitance CD(ON) VEN = 0V, VD = 0V, f = 1MHz

DG406 5 25 - - 400 pF

DG407 5 25 - - 200 pF

NOTE:

5. Parameters listed via process parameters and are not directly tested at final production. These parameters are lab characterized upon design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple produc- tion rich reflect lot to lot and within lot variation.

TABLE 4. ELECTRICAL TEST REQUIREMENTS

MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2)

Interim Electrical Parameters (Pre Burn0In) 1

Final Electrical Test Parameters 1 (Note 6), 2, 3, 9, 10, 11

Group A Test Requirements 1, 2, 3, 9, 10, 11

Group C and D Endpoints 1

NOTE:

6. PDA applied to Subgroup 1 only.

Test Circuits and Waveforms

FIGURE 1A. FIGURE 1B.

FIGURE 1C.

FIGURE 1. TRANSITION TIME

FIGURE 2A. FIGURE 2B.

FIGURE 2C.

EN A3

DG406

GND A₂ A₁

S₁ S₂ - S₁₅ S₁₆ V- D V+

±

±10V

V_O 300Ω 35pF

50Ω

+15V

+2.4V

-

15V A₀

10V

EN

A₀ DG407

GND A₁ A₂

S_1B

†

S_8B D_B V-

V+ ±10V

V_O 300Ω 35pF

50Ω

+15V

+2.4V

-

15V

†

= S_1A - S_8A, S_2B - S_7B, D_A

± 10V

LOGIC INPUT

SWITCH OUTPUT V_O

3V

V_S1B

50%

t_r < 20ns t_f < 20ns

t_TRANS 0V 50%

0V V_S8B

t_TRANS

S₈ ON 80%

80%

S₁ ON

EN A3

DG406

GND A₂ A₁

S₁ S₂ - S₁₆

V- D

V+ -5V

V_O 300Ω 35pF

50Ω

+15V

-

15V

A₀ EN

A₀ DG407

GND A₁

A₂ S_1B

†

D_B V-

V+ -5V

V_O 300Ω 35pF

50Ω

+15V

-

15V

†

= S_1A - S_8A, S_2B - S_8B, D_A

LOGIC INPUT

SWITCH OUTPUT V_O

3V

V_O

50%

t_r < 20ns t_f < 20ns

t_ON(EN) 0V

50%

t_OFF(EN)

90%

0V

FIGURE 2. ENABLE SWITCHING TIME

FIGURE 3A. FIGURE 3B.

FIGURE 3. BREAK-BEFORE-MAKE INTERVAL

FIGURE 4. CHARGE INJECTION

FIGURE 5. OFF ISOLATION FIGURE 6. CROSSTALK

Test Circuits and Waveforms

(Continued)

EN A3

DG406

GND A₂ A₁

ALL S

D, V-

V+ +5V

V_O 300Ω 35pF

50Ω

+15V

+2.4V

-

15V A₀

DG407 AND D_A

D_B

LOGIC INPUT

SWITCH OUTPUT V_O

3V

V_D

t_r < 20ns t_f < 20ns

t_OPEN 0V

0V

80%

50%

S_X

A₀ DG406

GND A₁ A₂

D

V- V+

V_O C_L +15V

-

15V A₃

DG407 EN V_GEN = 0-3V

10nF

5V

∆V_O OFF OFF

ON 3V

0V LOGIC

INPUT

SWITCH OUTPUT

S_X1

A₀ DG406

GND A₁ A₂

D

V- V+

V_O R_L R_G = 50Ω

+15V

-

15V A₃

DG407 S_X16 V_GEN = 1V_P-P

1kΩ

OFF ISOLATION = 20LOG V_OUT V_IN EN

V_S

A₀ DG406

GND A₁ A₂

D

V- V+

V_O R_L R_G = 50Ω

+15V

-

15V A₃

DG407 1V_P-P

1kΩ EN

S₁

1kΩ V_S

CROSSTALK = 20LOG V_OUT V_IN S_X2

S_X16

Burn-In Circuit

CERDIP BURN-IN SCHEMATIC DG406/407AK/883

NOTE:

R₁, R₂ = 10kΩ ±5%, 1/2W or 1/4W (Per Socket)

C₁, C₂ = 0.01µF (Min, Per Socket) or 0.1µF (Min, Per Row) D1, D2 = IN402 (or Equivalent, Per Board)

Schematic Diagram (Typical Channel)

+15V

D₁ C₁

R₁

28 27 26 25 24 23 22 21 20 19 18 17 16 15 1

2 3 4 5 6 7 8 9 10 11 12 13 14

OUT/OUTA -V IN 8/8A IN 7/7A IN 6/6A IN 5/5A IN 4/4A IN 3/3A IN 2/2A IN 1/1A EN A0 A1 A2 A3/NC

VREF GND IN 9/1B IN 10/2B IN 11/3B IN 12/4B IN 13/5B IN 14/6B IN 15/7B IN 16/8B NC NC/OUT B +V

R₂

-15V

D₂ C₂

+5V

V+

GND

A₀

A_X

EN

V-

V_REF

LEVEL

SHIFT DECODE/

DRIVE

V+

V+ V-

D

S₁

S_N

Typical Design Information

The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as applica- tion and design information only. No guarantee is implied.

Typical Performance Curves

FIGURE 7. r_DS(ON) vs V_D AND SUPPLY FIGURE 8. r_DS(ON) vs V_D AND TEMPERATURE

FIGURE 9. r_DS(ON) vs V_D AND SUPPLY FIGURE 10. I_D, I_S LEAKAGE CURRENTS vs ANALOG VOLT- AGE

±5V

±10V±8V

±15V±12V

±20V 160 140 120 100 80 60 40 20

0-20 -16 -12 -8 -4 0 4 8 12 16 20

V_D, DRAIN VOLTAGE (V)

rDS(ON), ON RESISTANCE (Ω) 125^oC

-40^oC

-55^oC 25^oC 85^oC

0^oC

V+ = 15V V- = -15V 80

70 60 50 40 30 20 10

0-15 -10 -5 0 5 10 15

V_D, DRAIN VOLTAGE (V) rDS(ON), ON-RESISTANCE (Ω)

V- = 0V

V+ = 7.5V

10V 12V

15V 20V

22V 240

200

160

120

80

40

00 4 8 12 16 20

V_D, DRAIN VOLTAGE (V) rDS(ON), ON-RESISTANCE (Ω)

-10 -5 0 5 10 15

V_S, V_D, SOURCE DRAIN VOLTAGE (V) V+ = 15V, V- = -15V

V_S = -V_D FOR I_D(OFF) V_D = V_S(OPEN) FOR I_D(ON)

I_S(OFF)

DG406 I_D(ON), I_D(OFF)

-15 120

80

40

0

-40

-80

-120 ID, IS, CURRENT (pA)

DG407 I_D(ON), I_D(OFF)

FIGURE 11. I_D, I_S LEAKAGE vs TEMPERATURE FIGURE 12. SWITCHING TIMES vs BIPOLAR SUPPLIES

FIGURE 13. SWITCHING TIMES vs SINGLE SUPPLY FIGURE 14. OFF-ISOLATION vs FREQUENCY

FIGURE 15. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 16. t_ON/t_OFF vs TEMPERATURE

Typical Performance Curves

(Continued)

V+ = 15V, V- = -15V V_S OR V_D = ±10V

I_S(OFF) I_D(ON), I_D(OFF)

100nA

10nA

1nA

100pA

10pA

1pA

0.1pA ID, IS, CURRENT (A)

-55 -35 -15 5 25 45 65 85 105 125

TEMPERATURE (^oC)

350

300

250

200

150

100

50

05 10 15 20

V_SUPPLY, SUPPLY VOLTAGE (±V)

TIME (ns)

t_TRANS

t_ON(EN)

t_OFF(EN)

700

600

500

400

300

200

100

05 10 15 20

V+, SUPPLY VOLTAGE (V)

TIME (ns) t_TRANS

t_ON(EN)

t_OFF(EN)

V- = 0V

1K 10K 100K 1M 10M

f, FREQUENCY (Hz) 100

-140

-120

-100

-80

-60

-40

-20

ISOL (dB)

0

100 1K 10K 100K 1M 10M

f, FREQUENCY (Hz) E_N = 5V, A_X = 0V OR 5V

I_GND

10 10

8 6

0

-4

-8 -10

I, CURRENT (mA)

I+

I- 4

2

-2

-6

300 280 260 240 220 200

140 120

60-55 -35 -15 5 25 45 65 85 105 125

TEMPERATURE (^oC)

TIME (ns)

180 160

100 80

t_TRANS

t_ON(EN)

t_OFF(EN) V+ = 15V, V- = -15V

FIGURE 17. SWITCHING THRESHOLD vs SUPPLY VOLTAGE

Typical Performance Curves

(Continued)

5 10 15 20

V_SUPPLY, SUPPLY VOLTAGE (±V) 00

1 2 3

VA(V)

Die Characteristics

DIE DIMENSIONS:

2490µm x 4560µm x 485µm ±25µm METALLIZATION:

Type: SiAl

Thickness: 12k Å ±1k Å

PASSIVATION:

Type: Nitride

Thickness: 8k Å ±1k Å

WORST CASE CURRENT DENSITY:

9.1 x 10

⁴

A/cm

²

Metallization Mask Layout

DG406/883

Die Characteristics

DIE DIMENSIONS:

2490µm x 4560µm x 485µm ±25µm

V-

S₁₆

D

NC V+

S₈

A₀ EN

S₇

S₆

S₅

S₄

S₃

S₂

S₁

A₁ A₂ A₃

GND S₁₅

S₁₄

S₁₃

S₁₂

S₁₁

S₁₀

S₉

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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Intersil Corporation 2401 Palm Bay Rd.

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NOTES:

1. Index area: A notch or a pin one identification mark shall be lo- cated adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass overrun.

6. Dimension Q shall be measured from the seating plane to the base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb S C A - B

c Q

L SEATING A

BASE

D

PLANE

PLANE

-A- -D-

-C- -B-

α D

E

S1 b2

b A

e

M c1

b1

(c)

(b) SECTION A-A

BASE LEAD FINISH

METAL

eA/2 A

M

S S

ccc M C A - B S DS aaaM C A - B S DS eA

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

F28.6

MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTES

MIN MAX MIN MAX

A - 0.232 - 5.92 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 1.490 - 37.85 5

E 0.500 0.610 12.70 15.49 5

e 0.100 BSC 2.54 BSC -

eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

α

^{90o 105o 90o 105o -}

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N 28 28 8

Rev. 0 4/94