Analog IC Design Techniques for Nanopower Biomedical Signal Processing

Analog IC Design Tecliniciues for Nanopower Biomedical

Signal Processing

Analog IC Design Techniques for Nanopower Biomedical

Signal Processing

P R O E F S C H R I F T

ter verkrijging van de graad van doetor aan de T(!elniiseli<; Universiteit Delft,,

op gezag van de Reetor Magnifieus prof. ir. K . C . A . M . Luyben, voorzitter van het College voor Promoties,

in het openbaar te verdedigen op maandag 17 maart 2014 om 12:30 nur

door

C I I U l ' H A M S A W I G U N

M.Eng. Ul Eleetrieal Engineering, Mahanakorn University of Teehnology, Thailand geboren t(; Udonlhani, Thailand

TU Delft Library

Prometheuspiein 1

D i l ])ro(;rs(:hrift is gocdgekeuixl door de promotor: Prof.dr. .T.1^.. Long

Copromotor Dr.ir. W . A . S(;rdijn

Samenstelling inomotieeonnnissie: Rector Maginöciis,

Prof.dr. .7.R. Long, D r . i r . W . A . Serdijn, P r o f d r . A . Deniosthcnons, Prof.dr.ir. A . H . M . van Roerirmnd, P r o f d r . P..L Freneh,

P r o f d r . E. Charboti, Dr. R.F. Yazieioghi, P r o f d r . R . B . Staszewski,

voorzitter

Tcchnisch<; Univc^rsiteit Delft,, promotor Technische Universiteit D e l f t , copromotor University College London

TechnisclK^ Universiteit Eindhoven Tef:lniische Universiteit D e l f t Teclniische Universiteit D e l f t nvlEC, Belgium

T(H:lmische Uiiiver.siteit D e l f t , reservclid

I S B N 978-94-6180-277-8

Copyright © 2014 by Chutham Sawigrm

A U rights reserved. No part of this publication may be reproduced, stored on a retrieval system, or transmitted i n any f o r m or by any means w i t h o n t i j r i o r pernussioii of the copyright owner. Print(!il in tlic^ Netherlands.

Contents

1 I n t r o d u c t i o n 1 1.1 Motivations 1

1.1.1 Understanding the Hmnan Nei-vous System 1

1.1.2 Paradigm Shift i n Bio-Medicine 2 1.2 Analog Signal Processmg m Wearable and Implantable Devices 3

1.3 Nanopower CMOS I C Design Challenges 3

1.4 Materials and Metliods 4 1.5 Thesis Organization 5

2 R e v i e w of R e l e v a n t T e c h n i q u e s a n d M O S F E T M o d e l 7

2.1 Introduction 7 2.2 Switclied-Current T<:chuique 7

2.2.1 P ' and 2'"'-Geuc;ration SI M(!mory Cells 7 2.2.2 Switcluug Error Cancellation in a SI Mcniiory Cells 8

2.3 G'„, - a Fih(;rs 1Ü 2.3.1 Basie Concept mid Design CoiLsiderations 10

2.3.2 Power-Efficient 6',„ - C filters 11

2.4 TiaiLslinear Circuits 12 2.4.1 T L Principle 12 2.4.2 Exponential and suili Tianscoiiductors 13

ii CONTENTS

2.4.;i Ciirieiit-Mo(i(^ Analog Miilti])lior 14 2.5 E K V M O S Model for Low-Current Analog Design 15

2.5.1 Large-Sigual E(i\iatious K i 2.5.2 Sniall-Sigual Model 17

2.(i Couehrsions 18

I Analog Sampled-Data Circuit Technique 19

3 S w i t c h e d - C u r r e n t T e c h n i q u e i n S u b t h r e s h o l d C M O S 21

3.1 Introduetion 21 3.2 F(-<Klback Analysis of a 2"'"'-Generation SI Memory CeU 21

3.2.1 0(X!xa.muiation of a 2"''-Gcneration SI M e m o r y Cell 22 3.2.2 R.<;consideration of the Performance Enhancement Techniques 23

3.2.3 Stability aud ^D'ausieut T3eliavior 25 3.3 Design Consideration: Class-A aud Class-AB 27

3.3.1 Cmrent Consmnption 27 3.3.2 Signal Excursion aud Drivability 28

3.3.3 Noiso 30 3.3.4 Effects of Tr ansistor Mismatch, I n p u t Current Imbalance and Switehüig Error

Cancellation 32 3.3.5 Supply Noise Rejection 34

3.4 Conclusions 34

4 A C l a s s - A B C u r r e n t - M o d e S u b t h r e s h o l d S H C i r c u i t 35

4.1 I n t r o d u c t i o n 35 4.2 D('sign of a Class-AB CSH Circuit 35

4.2.1 Bias Condition 37 4.2.2 I n p u t Current L i m i t a t i o n and Settling Behavior 37

4.3 Circuit SuniUations 39 4.4 Conclusions 42

CONTENTS iii

I I Compact Continuous-Time Filters 45

5 N a n o p o w e r B P F U s i n g S i n g l e - B r a n c h B i q u a d s 4 7

5.1 I n t r o d u c t i o n 47 5.2 Single Bianch Filtcirs 49

5.2.1 Filter Topology Using Fe(!dback Traiisconductors 49 5.2.2 Snpply Voltage R.eciuirenient and Current Consunii)tion 51

5.2.:i Noise 52 5.,'i Cascaded Bandpass Filter 54

5.3.1 Filter Topology Considerations 54 5.3.2 Transistor Level Realization 55

5.3.3 Dyiiainic Range 55 5.3.4 Coiunion-Mode Behavior 57

5.4 Design Methodology 57 5.4.1 Filter Order 57 5.4.2 M i d b a n d Gain and Dynamic Rangr; 58

5.4.3 Center Frequency, Bias Current and T i m i n g 58

5.4.4 'IVansLstor Dimensions 59 5.5 Measurement Results 59 5.6 ConehLsions (;(;;

6 F o l l o w e r - I n t e g r a t o r - B a s e d L P F for E G G D e t e c t i o n 69

6.1 I n t r o d u c t i o n (iq 6.2 ECG Dete<;tor L P F Design 70

6.3 Follower-hitcgrator-Based Lowpass Filter- 71

6.3.1 Conc<;pt 7I 6.3.2 TiaiLsistoi-Level Consideration 72

iv CONTENTS

().4.1 Filter Topology 74 6.4.2 Supply Voltage Requirement, Signal Swing aud Tuning 76

6.4.:i SignaTto-Noi,s(! Ratio 77 G.4.4 Supply Noise Rejection and Stalnlity 77

6.5 Design Procedur<! 78 6.5.1 Dynanric Range 78 6.5.2 Cutoff Fnxiuency, Bias Ciurent and Power Coiisuinptioii 78

6.5.3 Tuning 78 6.5.4 Tiausistor DimensioiLS 78

6.6 Measurement Results 7!)

6.7 Conclusions 85

I I I Very Low-Piequency Filtering and Large-Swing Multiplication 87

7 T r a n s c o n d u c t a n c e R e d u c t i o n T e c h n i q u e for V L F F i l t e r s 89

7.1 h i t r o d u c t i o n 89 7.2 Rcvitnv of Tianseoudnctance Reduction Techniques 89

7.3 Wide-Luiear Range Low-G,,, Transconductor 91

7.3.1 Concept 91 7.3.2 Noise and Dyuaniic Range 92

7.3.3 Ciurent Consumption and Circuit Complexity 93

7.4 1'^ilter Design and its Measured Results 94 7.4.1 B u t t e r w o r t h 2"''-order L P F 94 7.4.2 Supply Voltage Rcxiuirement and Signal Swing 94

7.4.3 Design Procedure 95 7.4.4 Measurement Results 98

CONTENTS V

8 L a i g e - S w i i i g C u r r e n t M u l t i p l i e r for A P D e t e c t i o n 103

8.1 hitroduction 103 8.2 Cla.ss-AB Current M i d t i j j l i e r 105

8.3 Subtluesliold Class-AB B u i l d i n g Blocks 106

8.4 Simulations 109 8.5 ConchisioiLS 110 9 C o n c l u s i o n s a n d F u t u r e W o r k 111 9.1 General GouclusioiLS I l l 9.2 List of Aeliievements 112 9.3 Future Work 113 A p p e n d i x A P h a s e - L o c k e d P e a k - P i c k i n g S p e e c h P r o c e s s o r 115 A . 1 I n t r o d u e t i o n 115 A.2 Sijeeeli Processing i n Cochlear Iiiii)lants 116

A.3 Review and Gomparison of Existing Proee.s.suig Strategies 117

A.3.1 CoutinuoiLS hiteik^aved Sampling 117 A.3.2 Zero-Crossuig Detection 117 A.3.3 Peak-Picking Tecimique 117 A.3.4 Race-to-Spike AsyndiroiioiLS Interleaved Saniiiluig 118

A.4 System Simulations U g A.5 Discr(4,e-Time Peak-Instant Detector 121

A.5.1 Switched-CmTent P I D Concept 122 A.5.2 Switclied-Curr(:nt P I D Circuit 123

A.5.3 Giixaiit Simulation 124 A. 6 Diseussion and Conclusions 126

A p p e n d i x B H a r n i o n i c Di.stortion C a l c u l a t i o n for C h a p t e r 3 129

B . 1 Cla.ss A CSH Circuit 129 B.2 Class-AB CSH Circuit L31

v i A c k n o w l e d g e m e n t s S a m e n v a t t i n g S u m i n a i y A b o u t the A u t h o r B i b l i o g r a p h y CONTENTS 133 135 137 139 141

Chapter 1

Introduction

1.1 Motivations

This tlicsis describes the IC design teeliiiitincs For nanopower analog signal processing u i biomedical a p p l i e a t i o i L S presented m [1-9]. A i m i n g to iiiaxiimzc the capability of a single M O S t r a i L s i s t o r to serve the requirements of extremely low-power operation and reasonable physical size for wear-able and iniiilautwear-able medical devices, b o t h discrete and continuous-time design techniques are investigated and developed. The thesis also emjiloys the uonhnear behavior o f conventional circuit builduig blocks t o serve stringent reqiuremcnts such as the very low cutolf fi-equency needed for slowly varying bio-potentiais filttaing, or the very large signal swing demanded for action potential detection. These research activities are driven by the health-related motivations described i n the following two subsections.

1.1.1 Understanding tlie Human Nervous System

Counting f r o m the treatment of headache aud gout for th<^ Roman Emperor Claudius by using torpedo üsli i n A D ' K i [1(}|, i t has become ahnost two iniilennia since electricity has been used i n uKKlicine for the first time. The early treatment o f neinal dtsorders by nicians of electricity started w i t h o u t sufficiënt understanding of electricity aud the hmnan nervous system. One step forward was made after the discovery o f tlu; Leyden Jar by Van Musschenbrocck in 1746. This was evident f r o m the observation t h a t electric shocks cause muscle contractions by Franklin i n 1774 (later confirmed again by Galvairi i n 1780) and the breaktliough of electrotherapy by Cavallo in 1777 who used electricity to treat v a r i o i L S diseases i.e., epilepsy, paralysis, deafiicss and blindness [11). A f t e r havmg shed some light on this new way of medical treatment, ek:ctrical and (ilectronic engineering

developed a lot for almost a couple of centuries as can be seen f r o m the existence of the uiveution

of the transistor and wireless technology. Unfbrtimately, however, electrotherapy chd not progress as rapidly as the progress ui electrical and electronic enguieermg. The main obstacle t h a t liiudered its progi-ess was a too limited understanduig o f the workings of the central nervous system.

A f t e r the Second W o r l d War, ad-vaiices u i semiconductor teclmology, microelectronics and micro-electro-uicclianical systems ( M E M S ) allowed the use of electrical recording to study nervous systems at b o t h the iiitra-ceUiilar [12] and extra-cellular [i;![ levels by using iiiicroelectrodes [14]. Significant

2 CHAPTEU 1. INTRODUCTION

progress i n inidersianding tlie nervous system has been made f r o m these eleetronic uiterfaces and the knowledge obtained has been applied in several medical prosthetic devices such as retinal i m -jilauts 115], cochkar implants (GIs) [16], deep bram stunulators (DBS) J17] and functional electrical stimulators (FES) ]18].

Nowadays, i t has b(x:oine clear b o t h u i medicine and engineering that we have learned enough abont the luiinan nervous system to know that there is still much more to learn. I n order to l i e r f o n n trf'atments elteetively and minimize side effects, medical devices that allow suiinltanc:ous iienral stimulation and recording me reiinired. N e i n a l responses are expected to be obsei-ved and studied wliile the body is being stimulated, and system parameters can then be adjusted to give appropriate stimuh ]19]. l b enable this nicchamsm, that is unfortimately not yet available i n any current technology, smm't mrplantable neural microsystems that involve iiiicroelectrodes and u l t r a low-power uitegratcd cirf:uits and systems need to be develojjed ]12|.

I n addition, the technology development n i e n t i o n c K l above is rcquircid in modern lii!althcarc t o

alleviate the cost o f hiture medical t r e a t u K ü i t s as w i l l b(^ describixl u i the next subsection.

1.1.2 Paiadigm Shiff in Bio-Medicine

Advancements i n medical technology is one reason why the world's aging poinilation is expanding rapidly. I t has been predicted that the number of elderly people over 65 will reach 1 hiUioii globally in 20,'lü [20]. Mahitainuig or improving iiuality of life for a longer lifespan is indeed very costly. W i t h o u t carefiil prevention and management, healthcare expenses agauist age-related chronic diseases w i l l become a financial binden for the global society. As indicated u i the 2005 W H O Global Report, $558, $237 and $303 billion f i o m national uicomcs (over the period of 2005-2015) of Ghina, India and the R,ussian Federation, respectively, w i l l be spent on the treatmiait of heart diseases, stroke and diabetes ]21].

As a consequence, the idea of using uiformation and coimnmiication technology to mobiUze bio-medicine to addr(\ss this problem has been developed. Traditional bio-medicine focus(!S on diagnosis and treatments that are centrahzed at a hospital. A n individual-centered healthcare system that focuses on the prevention of illness by early prediction of diseases ami maintaining health on a daily basis could reiluce healthcare costs u i the ftitm'e [22]. To enable this type o f healthcare, body-area networks ( B A N ) (also called a body-sensor networks (BSN)) that require efiieient, low-cost wearabk) mid implantable medical technologies and devices need to be iniplcmented ]21].

The key to success of this new paradigm is to keep the operation and iniplementatiou costs of the aforementioned systems much lower than those of traditional mediciue. These wearable and implantable devices need to be built fiom the cheapest technology and coiisunie extremely low amomits o f power. This demands for research activities i n the same area as mentioned i n Section 1.1.1 as well as smart sensor systems and technology, (üiergy harvesting and u l t r a low-power signal processing.

Driven by the motivations mentioned above, this thesis deals w i t h the design o f signal processuig

analog circuits ui c o m p l e m e n t a r y mctal-oxide-semicondnctor (CMOS) uitegrated circuit (IG)

tech-nology that serve biomedical ek:ctronic systems. Applications o f Hie design techniques presented u i tlus thesis can be seen f r o m : 1) signal filtering in an analog C I processor, 2) signal filtering i n an EGG detector o r oth(!r neural recorders and 3) signal i n u l t i p l i c a t k M i u i an energy-based action potential detci:tor.

1.2. ANALOG SIGNAL PROCESSING IN W^EALiABLE AND IMPLANTABLE DEVICES 3

Sensor/electrode

A m p ~ F i l t e r F i l t e r F e a t u r e A D C Tx

J

Figure; 1.1: Typical neiu'al recording architecture.

1.2 Analog Signal Processing in Wearable and Implantable

Devices

A p a r t from well-known v i t a l signs (temperatme, heart rate, respiratoi-y rate, blood pressme), more complex biomedical (bio-i)otential) signals, i.e., eleetroeardiogranrs (ECGs), electrocorticograms

(ECoGs), electroneurograms (ENGs), and electromyograms (EMGs), can be monitored i L s i u g a

typical E x G r(H:ording .system as shown i n Fig. 1.1 [23]. A l l of the biomedical signals mentioned manifest themselves w i t h i n the frequency range of approxnnately D C to 10 kHz. The amplitude of sigirals obtained f r o m the recording electrode can vary i n the range of a few / i V to niV depending on the recordmg site and type of electrode nsed. These signals w i l l be fed to an amplifier tyjiically w i t h a voltage gain of aromid 40 dB or more [23| before relaying the greater signal amplitudes to the next stage.

A f t e r signal amplification, the signal processing sections, i.e., filter and feature extractor are respon-sible for discrimination between the requu'cd signal and interfermg signals aud extractmg relevant featrrres of the signal, respectively. The extracted feature w i l l be converted into a digital fornrat by an analog-to-digital converter ( A D C ) before the transmLs.sion by the Ii,F transniitt(!r ( T x ) . Thi^rc are also cases (tbimd i n wearable and portable devices) t h a t after filtering the signal wiU be fed to the A D C directly. I n multi-chaimel sch(!ines, extracting only relevant features can help relax the resolutkm thereby low<!rmg power consumption of the A D C . Featme extraction therefore leads to a reduced data rate and lower average traiisnii.ssion power [24[.

This thesis describes design techniques to reahze analog signal processors using standard C M O S integrat(!d circiut technology i u extremely eomi)act and low-power fashions. I t tlnrs investigates the possibiUly to:

• A t the device level: employ a single M O S device to perlbrm signal proces.sing ftmctions u i both the continuous and discrete-tune domains.

• A t the c i r c u i t level: apply class-AB teclmiques to enhance the dynamic range of subthresh-old CMOS circuits fiirther.

1.3 Nanopower C M O S I C Design Challenges

In C M O S technologies, irMOS and pMOS devices are used i n combination w i t h other passive devices (i.e., resistors, capacitors and inductors) to build the re(|uired signal processing fimctions. I n this nanopower design context, MOS devices in a circuit wUl be [)perated i n the snbtlu-esliold or weak inversion region at very low bias currents (in the range of a few uAs down to a few tens of p A s ) . This unavoidable constraint on the design leads to the following problems:

4 CHAPTER 1. INTRODUCTION

1. The voltagc-to-cuneiit characteristic of tlie transistors is governed by au (!x])oiiential huiction which is Irighly noiJuiear |2r)|.

2. As a eoiise(iuc;nce of the (!xponeutial behavior and very low ciurent densities, the effect of transistor uusniatch becomes mon; severe t h a n i n strong inversion [2(i].

3. As the circuit and signal b a u d w i d t l L S can be very low, I / . / ' (Hiclter) noise becomes dominant. To supiness the 1/f iioisi;, transistors are thus retiuired to occupy large chip area, and/or a sain]5led-data teelniiquc, such as the auto-zeroing inc<;liaiiisin, needs to be applied [27].

Designing any analog hinction under the influence of the atbrementicmed issues is indeed challenging. Furtli(!rinore, to serve tlie requirements of miniaturized wearable and iin])laiitable medical devices, the degrees of freedom i n the design are even mon; limited. This th(;sis thus jiresents a design framework that involves the following methods:

1. Keeping the cucuit complexity low by utUiziug a n i i n i n i m i i number of transistors, thereby nuinmizing the chip area, source of noise/uiismatch and pow(;r cousinnption.

2. A p p l y i n g unity gaui-negative feedback loops wherever possible to reduce sensitivity t o internal disturbances (transistor mismatch i n this case), as well as to enhance circuit linearity. 3. h i the case that additional circuit elements are required, applying compact low-voltage circuit

architectures t h a t allow class-AB operation to enable large signal swhigs, thereby eiihmicing the circuit's dynamic range and keep static power consumption low.

Following the above design framework, tliis thesis contributes to: 1) analog sanipled-data, switclicd-cinreiit (SI) memory cells, 2) contmiions-time G „ r C filters and 3) four-quadrant analog multiphers. For the two former circuit classes, we achieved more t h a n an order of magnitude improvement in figme of merits (FoMs) m the designs ]7], [Gj. For the latter circuit class, the first fiiUy clas,s-AB, foiu-quadraut multiplier i n subthreshold CMOS is obtauied ]1].

1.4 Materials and Methods

I n this thesis, some well-known techniciues, viz., "switch surrent (SI)", "transeondnctancf^capacitance (G',„ - C ' ) " and '"ftanslmear ( T L ) " are investigated and developed fiirtlier i n order to serve biomerl-ical signal processuig i n a nW-power r(;giiiie.

The Sl techmqui; is t r a d i t i o n a l l y c o n s i d e r ( ; d to be compact and mismatch i i L s e n s i t i v e . For this reason, i t is developed to overcome the general challenges of nanopower analog design as mentioned in the previous section. Fmidauiciital operation and performance liiiutations of a SI circuit memory circuit are uivcstigated. Bas(;d on these finduigs, we jirojiose the design of a S I memory cell that offers performanci; eidiancement and power consiimption reduction. We estunate the design efficacy by i L s u i g a figure of merit (FoM) t f i a t involves relevant circuit characteristics and comparing i t to other designs reported previously.

The C'„, - C technique Ls widely used f o r filteruig biomedical signals. This techmeiue is examined f o e i L s i n g on the iiossibility t o create a nanopower continuous-tmre filter w i t h large time (tonstaiits in a reasonably small chip area. The concept of trmisistorized G,„ — C filters (using a transistor as a G',„ ceU) is attractive i u terms o f circuit compactness and power consumption. This thesis

1.5. THESIS ORGANIZATION

(l(^v(!k)ps tliis idea f m t l i ( ; r to aclii<;vc a design methodology that leads to the; eliip iinplenieiitatioii of the best-FoM, power-efheieiit, traiisistoriz(Kl G,„ ~ G lowpass and bandpass hlters for the andio h'eqiKiiiey range and b(;low.

The traiisliiiear prineiple is coiLsklered a jiowerftil design tool for low-power einreiit-niode signal processing. I t e.xploits th<; nonlinear large-signal cliaraeteristie of a traiisist<n- to perform varioiLS signal processing hnictioiis ftom different ckised-looj) base-eiiiittfir j n n c t i o i i tenninals arraiigi'.iiients ( T L loop) of B.IT devices (or gate-sonrce, gate-bidk or bnlk-sonrce terminal arrangements of MOS-FETs). Therefore, large signal swuigs can be expected and, subsequently, a large dynamic range becomes possible. This thesis develops a design technique that allows class-AB operation for a subthreshold ciurent-inod(! analog multiplier. This finding is iisefiü for the design of an action potential detector that distinguishes energy of action potentials fi-om backgroimd noise.

1.5 Thesis Organization

A f t e r tfie uitroduction in C h a p t e r 1,

C h a p t e r 2 presents a review of analog circuit teclmiques wiflely used i n low-power biomedical signal processing a])plicatioirs (SI, G,„-C, and T L ) . Subtlicsliold MOS morlel equations, which are eiui)loyed throughout tins thesis, are also described.

Starting from here, the thesis w i l l b(! divid(Kl uito 3 parts as follows:

P a r t I A n a l o g S a n i p l e d - D a t a C i r c u i t T e c h n i q u e

C h a p t e r 3 cxanunes the SI memory cell f r o m a feedback point of vh'.w. Fundamental features and design consideratioiLS using MOSl-'ETs i n subthi-esliold are discussed.

C h a p t e r 4 presents the desigu and simulation of a class-AB SI uKünory cell operating in the subthreshold region. I t wiU be sliown that employing negative feedback and class-AB operation employing MOSFETs i n subtliresliokl can help to obtain a dynamic range of 77 dB at 28 i i W jiower consumption.

P a r t I I C o m p a c t C o n t i n u o u s - T i m e F i l t e r s

C h a p t e r 5 describes the theory, design and implemeutation of 'single branch filters'. A bandpass filter design methodology based on this filter striK:tur(^ is used to obtain tfie best F o M to date. Measurement results for the filter cluj) m-e also reported.

C h a p t e r 6 presents a lowjiass filt(!r ( L P F ) design baserl on a circuit cell caUixl a 'follower integrator ( F I ) ' which is a special class of single branch filters that contains a local negative feedback loop and allows for a cascade connection in a low-voltage environment. The L P F design w i l l be discussed along w i t h its ajiiihcation i n EGG recording and measmement results.

c CHAPTER 1. INTRODUCTION

P a r t I I I V e r y L o w - F r e q u e n c y F i l t e r i n g a n d L a r g e - S w i n g M u l t i p l i c a t i o n

C h a p t e r 7 jircsents a raodulai' transconductance reduction teclnuqne dedicated to fidly-integrated

C,n-C biomedical titters w i t h cutotf frequencies in the range of 1-1(10 Hz. The chij) measur<!nient

results of the G,n~C lowpass tilter w i l l also be discussed.

C h a p t e r 8 shows a non-linear cancellation techmeiue for realizing a class-AB fom'-quadrant cm-rent multiplier. This tecimique utilizes subthreshold class-AB transconductors and a geometric mean current splitter so t h a t a four-quadrant ninltiplier w i t h (tliconitically) u i ü u n i t e d signal swing is obtained.

C h a p t e r 9 summarizes the thesis and discusses the iiossibiUties for h i t m e work.

A p p e n d i x A presents a peak instant detector ( P I D ) <lesigned for an u l t r a low-power analog cochlear implant speech processor.

A p p e n d i x B provides a detailed calculation for harnionic distortioirs of the class-A and class-AB current-mode sauiple-and-hold circuits.

Chapter 2

Review of Relevant Techniques

and MOSFET Model

2.1 Introduction

This ciiapter provides a review of eircuit teclmiques that can be usehil for the <lesign of analog ICs to be used in biomedical apphcations. The mentioued teclmiques comprise switclied-cnrrent (SI), traiLscouduetance-capacitor (G,„ - C) and traiislinear ( T L ) . The; fimdamental concepts and recent progresses of these tecimique are discussed. As the weak uiversion C M O S <Ievices are basic eleiuc;nts apiilied throughout this thesis, the descriptions of subthreshold MOS ope^ration and the model iLsed are also provided.

2.2 Switched-Current Technique

SI is an analog sanipled-data tcchnicpie recognized Ior its iiotential of being compact and insensitive to mismatch (28|. Thus i t is expeeted to overcome the iiaiio]K)wer design challenges mentioned ui the thesis uitrochietion. Tins section presents the circuit descriptioiLS of two generations of SI memory cedls. Effects o l practical MOS switches and techniques to reduce the switcliuig error are also discussed.

2.2.1 and 2"'*-Generation S I Memory Cells

Fig. 2.1 shows two generations of Sl circuits. The l^'-generation SI memory cell [29] comprises switch Sl controlled by a suigle i)hase clock signal and transistors Mi and A'l2, biased by constant current sources In (see F i g . 2.1(a)). Since h'h is diode-connected, i n p u t ciurent /i„ is converted into a voltage which w i l l be meiuorized by the gate-sour<;e parasitic capacitance Cgs2 after t u r n i n g off switch .S'l. Neglecting the channel length modulation and assuming Si is an ideal switch, ƒ;„ w i l l be converted into /oui for the first lialf iieriod of clock signal and then, for the next half period, /„„t w i l l fiold tlie final value of 7i„ at the end of the previoirs half period. We thus obtain a current-mode

8 CHAPTER 2. REVIEW OF RELEVANT TECIINIQUES AND MOSFET MODEL

Figure; 2.1: S w i t c l u K l - c m T e n t i n c u i o r y c e l l s : (a) P ' - g e n e r a t i o n and (b) 2"'*-generation.

hall' delay or track-and-hold operation. I t should be noticed that there is no current being switched but the gate voltage of Mi is.

The true switehed-cmrent mechanism occurs i n the 2"''-generation SI memoiy ceU shown i n Fig. 2.1(b) [29]. Switches Si and S2 are controlled by the same clock wlrile S3 is controlled by a difierent clock signal which is noii-ov(!rlapped w i t h the clock signal for .S'l and S2 (see Fig. 2.1). D u r i n g the clock phase that S'l arrd S2 are i.urned on, /i„ is supplied to the diode-eomiected transistor creating a particular gate-source voltage. I n the iKixt clock jjiase. Si and >?2 are t m i i e d off, the gate and drain terminals of Mi aic. discoimected and the gate-soiu'ce voltage is memorized by c^s. Sunultaneously, ,93 Ls turned on supijlying 7„„t to the next stage. This mechanism is sliglitly difierent ftom the 1"'-generation cell; tliis circuit performs current sample-and-hold operation and indeed the i n p u t and o u t p u t eiurents of this circuit are being switched.

Kegardiiig cucuit compactness, mismatch error and power consumption, the 2'"*-generatioii memory cell is superior t o the P'-geueration OIK; since only one transistor is used to perform both sampling and holding operations, and three switches which do not consume any static power. Tlierelbrx;, the 2""'-generatioii SI memory is chosen to be developed ftirther in this thesis.

2.2.2 Switching Error Cancellation in a S I Memory Cells

The major problem that degrades the accuracy and limits the high frequency performances of the SI memory ceU is the switelimg error due; t o the non-ideal characteristics eif a M O S switch viz., eJiargc injection and cloe;k-feedthrough elfects ]30]. To muiimize the; e;ffe;cts of these switeliing errors, several ti;cliiiiqncs have been jiroposeel.

E r r o r V o l t a g e C a n c e l l a t i o n : Fig. 2.2(a) shows an error cancellation technique preiposed for the P'-geueratioii iue;inory cell ]31]. A n extra switch and a voltage foUower/level slnft,e;r are inserted Ul addition to the; e:oiiveiitioiial P'-geueration memory cell. W i t h this eircuit arrange;meut, the; e:liarge ineluceel by switclie;s Si will be; e:e)nverted into e;rror voltages ajipesaruig at the seiurce and

gate te;riniiials eif M2. Assuming capacitaue:e;s c;, anel Cgs2 ai<; identical, the voltage error ae;re)ss

Cgs2 is tliiLS minimized. Note that tins teclniieiue can also be; applie;d to the 2"''-gi;iieratioii memory

cell. Howe;ve;r, as the; switching error is signal depe;iiele;iit, the error caneiellation canne)t be; ae:liieved e:e)iiipletely.

2.2. SWITCHED-CURRENT TECHNIQUE 9

Figure 2.2: Switc.liiug mvor reductiou teclmiques: (a) voltage error caneellatiou, (b) two-step sani-pliug aud (c) zero-voltage switeliiiig.

1 0 CHAPTER 2. REVIEW OF RELEVANT TECHNIQUES AND MOSFET MODEL

E r r o r C u r r e n t C a n c e l l a t i o n : Anotiier te<:lini(|ne aiiplied to a 2"''-generation SI inemory, called two-step sampling (S^I) is shown i n F i g . 2.2(b) [32]. Unhke the teehmque mentioned above t h a t reduces the voltage error at the memory capacitor, this tecimique minimizes the output current error by introducing two more saiiii)luig steps and one more memory element. The samjihiig period starts alter t u r n i n g on switches Si and ,S':„. IVaiisistor Mj, is acting as a current source supplying a DC current to diode coimeeteil transistor M„. Then, input currcnit I,,, Hows into the d r a m teriirinal of M,,. A f t e r settling, Si„ is turned off and Su starts t u r n i n g on while 5'i remains on. A t this moment. A/,, is UKmiorLsing 7i„ i)lus switching error eiurent (/„) induced by Sia- D u r i n g this period of time, Mj, w i l l track /„ u n t i l Sy, and Si are turned off. Right after switch S2 is turn(;d on, A/p w i l l store and supply ƒ„ and the error current generated by Su, (li,) to the output. Note t h a t In is relatively smaU and less signal depend(!iit coiniiared to [32]. As 5'i,i remains off . A/,, w i l l also

snpply current Ii„+Ia to the output. B y this mechanism, I„ w i l l be cancelled out and only /,,

remains.

Z e r o - V o l t a g e S w i t c h i n g : The previous two teeluriques can only reduce the switching error t o some extent. For high iirecision sample-and-hold operation, the SI memory cell w i t h zero-voltage switcliiug depicted i n Fig. 2.2(c) is required ]33]. As the injected charge and clock-feedtlirongli charge can be made constant by f i x i n g the voltages across the drain and somce terminals of the MOS samphng switch, voltage amphher /!„ is inserted for enhancing the loop gain aroimd the sampling node. I n tins case, C/; is used as a memory capacitor instead of parasitic capacitance

r.g„ of a suigle transistor. During t i n ; sampling phase, the voltage across sampling switch Si, w i l l

be fixed at a certam reference voltage ( v i r t u a l groimd) and the signal error voltage wiU be relayed to the gate terminal of A'/i instead. To the best of our knowledgi;, oidy tins teehmque is able to sujipress the switching error by making i t signal-iiidejicndcnt anrl allows for almost f;oiiii)lete error cancellation in dilfereutial circuit operation. For tins reason, this tecimique is chosen to be developixl hirther for nanopower signal processing IC design. More detail of this work is presented Ul Part I of this thesis.

G',„ — 6' filters ]34] have been applied i n various moderate-linearity apphcatioiLS. Further resemcli, focusing on the circuit structiue and design mothodology for the C,„ - C filters, can be iiseftil for nanopower biomedical signal filtering. T l i i s section provides the basic priiicii>le of G,„ - C filters and a survey of the recent advance m G,„ — C topologies.

2.3.1 Basic Concept and Design Considerations

Fig. 2.3(a) shows a Cr'„, — C' integrator simply fiirmed by transcoiiductor G , „ and capacitor C. h i p u t voltage Vin is converti;d into current I„ut accorduig to I„„i = 1 4 , i G , „ . Then, /„„t w i l l be integrated by G resulting i u output voltagi; K,„t. A n integrator is the niahi buiding block for synthesizing higher-order filters |34[. Fig. 2.3(b) shows how the uitegrator can bc extended to realized a P'-order filter. The feedback traiLscoiiductor G , „ 2 is inserted to the output node thereby crisiting a lossy integrator (or 1^'-order lowpass filter ( L P F ) ) w i t h a transfer ftmction of

2.3 G

C Filters

2.3. GM - G FILTERS ₁₁

Figiu-e 2.3: G,„ - G filters, (a) liit(;grator, (b) P'-or(l(;r L P F and (c) compact r e o r d e r L P F .

It can be fomid f r o m (2.1) that the jjassband gain of this filter is defined by the l a t i o of G,„i antl G,„2. Also, the entoft' frequency is G,„2/G. I n this case, UK; gain aud cutoff frequency eau be set iud(!pendently.

I n practice, either M O S T or B . I T can be used to design a G,„ ciremt. Non-linearity of these tyjies of transistors w i l l affi;ct the huearity of the filter. Tims, any 6',,, circuit is an active element t h a t is, not only non-linear, but also noisy. Moreover, i t can be seen from (2.1) that mismatch between G,i,i and G , „ 2 degrades the precision o f t h e passband gain. For these reasons, inspecting the filter topology closely can help selecting tlie best suitable topology for a speeifie application. Let's fticus on circuit i n Figs. 2.:i(a) and 2.3(b) again. Assuming the transcondiietance characteristics of all of the G'„i circuits are identical and weakly uonfinear, the distortion produced at the outputs of the filters will depend on the voltage appearuig across the i n p u t teriuuials of the G„, circuits. For b o t h filter cu-cuits, we can see that the m p u t voltage is appUed directly to fhe u i i m t terminals of tli(! transconductors, G,„ and G , „ i , and thus the uoiüinearities of the G,„ and G„,i are fiiUy responsible to th<! distortion obtained.

Fig. 2.3(c) presents a first order L P F developed fr'oni the L P F i n Fig. 2.3(b) for G,„ = G,„, = G',„2. I n this case the passband gain is always u n i t y (and cannot be adjusted), h i term o l huearity, wc can

consider that V„„t is connected to the inverting input of G,„ thereby creating a unity-gain negative

feedback. For fre(|uencics well b<;low th(! cutoff fi-equency, Kjut wUi follow closely This r e s i ü t s in a very smaU voltage appearing at the dUftaential uipiit of the G,„ circuit. As a consequence, less distortion wiU be produced h i eomparison with the L P F i n Fig. 2.3(b). I n ternrs of power consumption and noise, i t is clear that the L P F ui Fig. 2.3(c) coiisimi(;s less power and produces less noise than the L P F i n Fig. 2.3(b) for the same cutoff frequency.

2.3.2 Power-EfHcient G„, - C filters

Based on tin; circuit inspeetiou mentioned above, the id<!a of disigning a comiiact L P F has been introduced h i [35]. B y considering a single transistor as a feedback transcouductor, a differential P'-order L P F can be reahzed usmg only two source follower circuits as shown iu Fig. 2.4(a). The dift'crential strnctm-e is used here to maximize the filter's Unear range.

A r i s i n g fi-om F i g . 2.4(a), the biquad section shown i n Fig. 2.4(b) has been developed. This circuit has been successhiUy employed to unplenient a 4"'-order L P F witU a 1Ü M H z cutoff frequency [35].

12 CHAPTER. 2. RE\HEW OF RELEVANT TECHNIQUES AND MOSFET MODEL

( a ) Vss

(b)

Figure 2.4: Ti-ausi,storizecl G,„ - 6' filter, (a) 1="-order L P F eireuit. (b) Lowpa.ss biquad section.

Recently, a 1ÜÜ Hz L P F for biopotential re<;ording that consumes only IT) n W quiescent power has been reported |3(i|. Unfortunately, inspecthig tlris circuit ftuther reveals t l i a t i t requues a D C supply (VoD-Pss) of more t h a n two gate-source voltagis. Moreover, cascade connection to aciiieve a lngh(!r-order design hlter needs an even larger D C supply. Otherwise, an irMOS version of th(i biiinad section is needed. The problem of usuig coniplementary devices i n a standard CMOS process is that the bulk effect gives rise to perforinance degradation.

Favored by the circuit compactness, this type of C,„ - C cucuit has been developed hirther i n order to overcome the liimtatious nientioned above and to aUow for aiiplication to the design of a bandpass filter. Part I I of this thesis presents the details of this activity.

2.4 Ti-anslinear Circuits

The T L iiriiicipic is an efflck;nt tool for synthesizing current-mode signal processing circuits [37]. Mainly, T L circuits are designed using large-signal behaviors of M O S F E T [38[ and B,1T (bipolar j u n c t i o n transistor) [37[. Therefiire, the T L cuciuts a t t r i b u t e large signal swing. This section uivestigates the T L principle applied to B.IT circuits as i t can be applied directly t o snbtlueshold CMOS circuits.

2.4.1 T L Principle

T L prmciple was first introduced based on the exponential relation between voltage and curnHit f o i m d i n B.lTs and diodes [37]. According to the fact that the transconductance of a B J T varies hiiearly w i t h its collector current, circuits that contain loops of base-emitter (BE) junetious aUow current-mode signal processuig huictious to be implemented. A T L loop is characterized by an even number of jiincti(ms. The number of clockwise-oriented ( C W ) devices equals the number of devices witli-coimter clockmse ( C C W ) orientation. The T L principle for B J T states that "the product of the cmrent densities in a clockwise direction equals the product of current densities in a counter-clockwise direction" ]37]. This can be w r i t t e n as.

2.4. TU/INSLINEAR CIRCUITS ₁₃

Figure 2 . 5 : 4-lraiisistor traiislinear loop.

where / ( ; aud A are the coUeetor current and emitter ar(;a of the B J T , respectively.

Considering the circuit in Fig. 2 . 5 , i t can be S(;eii that there an; four tiausistors connected via

their B E junctions starting f r o m Vn through Q i , Q2, Q3 and Q4, and back to Vn again. This arrangenient fonns the T L loop h i whieh the ekickwise e l e u H n i t s are Qi and Q3. Q2 and Q4 are the

eoiuiter-clockwise elements. From the T L loop, in f o r i i L S of voltage we can find that

VnFA 4 VBE3 = VnE2 + V B E 4 . ( 2 . 3 )

Suppose t h a t all the traiLsistors liav(; the same eiiiitt(;r area, applying the T L principle, the following relationship can be found:

Ici • hn = lc2 • ICA- ( 2 . 4 )

2.4.2 Exponential and sinh Tiansconductors

Fig. 2.()(a) shows a two-transistor T L loop w i t h a voltage some (V\a = Vi - V2), a so-called "traiisUii-ear network" ( T N ) . Suimnation of the voltage aroiuid the loop yields

VM = VnFA - VnE2- ( 2 . 5 )

This relationship leads to a (xiuation that Ls useftil for analysing the large signal behavior of circuits that involve this T L network;

The exponential traiLseonductor <:ireuit shown i n F i g 2.0(b) is a good example of such a T N . A p p l y i n g ( 2 . 0 ) and neglecting the base currents of all transistors, the voltage-to-curn!iit relationship of the circuit i n F i g . 2.G(b) can b(! foimd as

/out = IB exp ( 2 . 7 )

F i g 2.C(c) shows a class-AB nonlinear transcouductor basixl on the exiioiiential transcouductor shown Ul F i g 2 . 0 ( b ) . This traiLsconductor provides a (theoretically) m ü i m i t e d output current that

14 CHAPTER 2. REVIEW OF RELEVANT TECHNIQUES AND MOSFET MODEL

Figme 2.6: Tiansliiiear networks: (a) 2-transistor T L network w i t h voltage soirrce, (b) exponential transeonch:etor and (e) sinh transeondnetor.

benefits the design of cmrent-nrode sample-and-hold and analog midtiplier circuits (more details can be found in Parts I and 111 of tlus tlie.sis). The voltage-to-curr(;nt relationshij) of this transcouductor is

'out — — ha — h = 21,s sinh (2.8)

2.4.3 Current-Mode Analog Multiplier

Another application of T L circints is an analog midtiplier. Based on the 4-traiisistor T L loop shown in Fig. 2.5, a curieiit-niode foiu'-qnadrant analog multiplier can be realized as shown i n Fig. 2.7. A p j i l y i n g the T L principle to the loop contaiuing Q i to Q4 and a.ssniiiing the base currents of all transistors are negligible, w(; have

{h + hi) {12 + 13) = I c J f i -

rn

Re-arrangrug (2.9) gives

2.5. EKV MOS MODEL EOR LOW-CURRENT ANALOG DESIGN ₁₅

Vcc

Figure 2.7: Cla.ss-A, cmicut-mocle, 4-qiiadraiit ajialog iiiultiplier

Crm.sidcriiig tlie output t e r u ü i i a l , we eau see that

'out = IB + '1 + «2 - /c4- (2.11)

Substituting (2.1Ü) uito (2.11) lesidts i u

•'•i«2

' „ u t = j ^ . (2.12)

I t eau be seeu that a four-quadrant niiiltiphiu- is aeliieved. However, tliis ninltiplier is operated in class-A that au i n p u t signal greater than IB eauuot be apphed. h i Part I I I of this thesis, a class-AB foiu-quadrant multiplier that can handle i n i i i i t signals larger than the bias current wUl be presented.

2.5 E K V M O S Model for Low-Current Analog Design

A compact E K V MOS transistor model [25] developed for low-current analog circuit design is de-scribed i n this section. Focusing on subthreshold operation, only relevant parameters are smmna-rized for practical hand calculations. As the physical structures of i i MO S and p M O S are iiitruisically symmetrical, the bulk (or body) terimnal voltage is used as the reference potential (instead of the conventional source terminal voltagt;) for the potential of each t(;rininal depicted i n the symbols sliown h i Fig. 2.8. Moreover, only the iiM OS device model wiU be described, in order t o avoid repeating redtmdant descriptions of the dual pMOS. Phnvever, the model description for the p M O S device can be obtained by applying an oiijiosite sign i n the tlueshold voltage and applying the symmetik: condition that

fo ( V G B , VDB, VSB) for uMOS = -Ir, ( - K G B , - I - D B , - K s B ) f o r p M O S , ( 2 . 1 3 )

where is tlu; drain ctirrent of each (k;vice, VGB, VSB mid VDB are the gate-bulk, source-bulk and draiii-tiiilk voltages, rcsiieclivcly.

16 CHAPTEI! 2. RE\HEW OF RELEVANT TECHNIQUES AND MOSFET MODEL

Figure 2.8: M O S F E T 4-teruiirial syuiliols: (a) i i M OS and (b) p M O S .

2.5.1 Large-Signal Equations

As i u d i t a t e d i u (2.13), the draui curreut is a fimetiou ef all terminal voltages. For mi irMOS device, the E K V model propo.ses a general equation for the drain cnrrent valid for all operating regions as

ID

-

Under the subthreshold condition that VGB < VTHU, tbe drain current behavior can be divided into different operating regions as follows.

W e a k I n v e r s i o n C o n d u c t i o n : This region is defined supposuig that VSB (and VDB) > (VGB -KTHn)/"7i- Then, (2.14) can be reduced to

ID = Isn exp V G B - VT

T„VT o.xp

- V S B VT

- (!Xp - V D D (2.15)

I t ean be s(x;ii f r o m (2.f5) that ID of this region is controUed, not oidy by the gate voltagi;, but also the voltage across t l u ; drain aud source terminals. I n other words, tin; i i M O S is acting as a voltage-<;oiitrolled uonluiear conductor.

W e a k I n v e r s i o n R e v e r s e S a t u r a t i o n : This region is found when (VSB - V D B ) > VT and (2.14) can be simplified as ID = -f.S',. oxp VGD - V T H , " „ V T exp - V D B V T (2.16)

I n tills case, ID wiU flow i n an opposite direction compared w i t h the previous case and i t wiU reach 0 when VDB is approximately larger than 4 V T .

2.5. EKV MOS MODEL FOB. LOW-CUURENT ANALOG DESIGN ₁₇

W e a k I n v e r s i o n F o r w a r d S a t u r a t i o n : T l i i s ri^gioii is found when {VUB - V^B) > VT (U jiraetice, VDS > 'IVT is sutfieieut). Then, (2.14) ean be simplified to

ID =- hn exp / V G B

V n„VT

e x j ) - V s i

VT (2.17)

For pMOS devices iLsed ui this thesis, the souree and bulk terimnals are connected together thereby avoiding the bulk efi'ect in standard CMOS teehnology. B y doing so, (2.17) can be simplified hirther and using the .syimnelrie <:oiiditioii as (kHcribed i n (2.13), we have

f n = I •S';, e x p V S G - | V T H P I / I . „ V T = ƒ .s-,, exp n„VT e x j ) VSG G j i i e x i ) n,.VT (2.18)

where /on = ^ . S p c x p ' ) = Jso{W/L) is the zero-biased current of the p M O S T obtained by

settuig Ves = 0 while Iso is defined here as the zero-biased current for a u m t transistor obtained fi-om conditions: VQS = 0 and W = L. Vmp and n,, are the tliresliold voltage and slope factor of the pMOS device, respectively. Note t h a t smce this operating region is often irsed, the more appropriate term "weak inversion saturation" is used i n tlris thesis to denote this region.

2.5.2 Small-Signal Model

Fig. 2.9 shows the static (low-fiixiuency) small-sigiial model of the 4-terrauial transistor. Tianscon-ductances 3,„„ (gate trancoriductanei;), (drain trauseonductance) and ry,,,, (sourei; transconduc-tance) contribute to the drain current variation when siiiaU variatioiLS of the respective voltages, V G B , I^DB arid Vsu are apphed. For the weak uiversion saturation i i M O S , i t can be found that

Hn,,, d h , ID OVGB « „ V T ' (2.19) . . , „ . ^ | ^ ^ « ( A / . ) , (2.20) and d i p OVsi

hi

Note t h a t the cliamiel length modulation ( C L M ) that leads to the drain condnetion i n the weak inversion saturation region is neglected. I f i t is included, g,,,,, w i l l become as shown hetween brackets h i (2.20), where A is the C L M parameter [25].

18 CIIAPTER 2. REWEW OF RELEVANT TECHNIQUES AND MOSFET MODEL B _ + 9 D

+ is

Figm-e 2.9: Static (low-frequoüicy) small-.signal ecniival(;nt circuit,

2.6 Conclusions

Tiuee u.seful analog design techniques have bc<;n described vin., SI, 6 ' , „ - C and T L . The discirssions o f the ijerforniance l i n i i t a t i o i L S and advantages of the circuits based on these t e c h n i q u e s have heen given. Also a siniplification of the compact E K V M O S model has been presented iu order provide a few relevant nomenclatiues t l i a t help the hiterested reader to foUow the consecutive chapters conveniently. The information shown in tbis chapter is employed as huidamental material Ior the nanopower design teclmiques ])resentc<l i n the ivst o f this thesis.

P a r t I

Analog Sampled-Data Circuit

Technique

Chapter 3

Switched-Current Technique in

Subthreshold CMOS

3.1 Introduction

Processing electrical signals in the voltage domain using CMOS circuits is encountering the problem of l i m i t e d voltage headroom. This residts h o m CMOS process seahng that re<luces the supply voltage and thereby forces the maxunuui signal voltage swing to go down |39J. To recover the signal-to-uoise ratio (SNB,) and the dynamic range (DR.), current-mode signal processmg has become attractive since the nonlinear behavior of the devices, i.e., the; square and exponential laws for strong and weak inversion behaviors, respectively, provide a compressive voltage swing. A wide range of eirrrent signal swings can thus be obtained fi-om a low supply voltage [28].

h i the area of biomedical electronics that focuses on the ckisign of portable, wearable and implantable devices, minimizuig power and area consumption are major r(!(iuirenieiits. This is to keep the device sizes fit fi)r such applicatioiLS and to prolong the lifetime of the batt<;ry used. To operate circuits at verly low ciurent consuiuptiou (in the range of u A ) and a supply voltage below 1 V , the C M O S devices w i l l be forced into their wealt inversion region, winch creates a design (hfficulty i n terms of noise and mismatch [40,41]. Large clup area is reciuired for capacitors and trausistors us<;d in a circuit to m i n ü n ü z e noise and uusniatch. Therefore, a suitable circuit tecimique that can satisfy the i-cquirements and overcome the problem of noise and luismatch is needed.

This chapter exaiiunes the feasibility to perform signal processing ftmctions w i t i i i n a small sihcon area to achieve SNR and D R lugher than 70 dB wliile consmuing very l i t t l e electrical pow<!r. As it was introduced w i t h the distinct feature of small ari^a and mismatch uisensitive sampled data operation, the analog current-mode technique caUed 'switched current' (SI) is re-examined i n rletail Ibeusing on its ftmdmneutal euciut operation. R.elc-vant elfects of circuit and device non-kleahties are also discussed.

3.2 Feedback Analysis of a 2"'^-Generation SI Memory Cell

This section presents a feedback analysis, review of perforinance enhanc(!inent trxjmiqnes mid sta-bility analysis of a 2"''-g(;iiei-ation SI memory cell.

CIIjiPTER 3. SWITCHED-CURRENT TECHNIQUE IN SUBTHRESHOLD CMOS

3.2.1 Reexamination of a 'i'^'-Generation S I Memory Cell

Fig. 3.1(a) sliows a 2"'' goiiorat.ioii SI iii(!inoiy cell [28]. I t comprises only one transistor biased by constant current IB and .switches Si — S^ controlled by two nomoverlapping clock signals. Consid(;ring sniall-signal operation and iiichiding channel length modulation, the circuit in F i g . 3.1(a) can be modeled as shown i n Fig. 3.1(b), where Ro and 6',„ represent the output resistance (output resistance of IB in parallel w i t h that of the traiLsistor) and transconductance lactor of the transistor, resiicctively.

( a ) ( b ) Figure 3.1: Second-generation SI memory cell, (a) circuit schematic, (b) smaU-signal model.

D u r i n g the sanipliug phase (6'i and S2 are closed ami .S3 is o])ened), the gate and drain terimnals of the transistor are connected creating a feedback looj) as shown in the block diagiam i n Fig. 3.2. As one can see, the error current resulting ftom / i „ — / / , (where Ii^ and I j represent the iniint and feedback currents, resiicctively) will flow into i n p u t impedance Z, = R„{1 -|- s C f ; / ï „ ) ^ \ thereby creating voltage Vn which is the input voltage of transcouductor G „ , . Voltage V// wUl bc; converted into cmrent I j by 6',„.

VH

Figure 3.2; Feedback block diagram of the second-generation Sl memory cell From tli(! bkick diagram, the looji gain ( L G ) of the system ean be found as

L G =

a,„z, = ^

where G;; etiuals the parasitic gate-source capacitance; Cg, of the t r a i L s i s t o r . I n this case, LG equals the intrinsic gain of a siiigk; transistor which is becoming small(;r i n deep snbmicron technology [42[. The; i i i i i u t i i n ] ) e d a i K : e o f the circuit can b e also found to be

- - 1 4 LG - G,„

(1

I t can be seen fi-om (3.1) and (3.2) that H„ directly contributes to L G but affects Zi^ insignificantly. On the other hand, R„ plays a role when tli<; fi;edback loop is broken during the hold jiliase ( S i and S2 are opened and .^s is closed). I t defines the outi>ut rcsistaiic(; o f t h e memory cell since the gat(; voltage of the transistor is h(;ld coiLstaut by the charge stored on memory capacitor Cgg.

a.2. FEEDBACK ANALYSIS OF A 2^"-GENERATION SI MEMORY CELL 23

3.2.2 Reconsideration of tlie Performance Enhancement Techniques

As we can see fiom tfi<! previous sul)seetion Üiat tfii; operation o f a 2"''-gl jnemory cell Ls a unity-gaui negative feedback system, tlie system's L G can be nsed to define tlie precision of the SI ciremt. For tills r < ; a s o i i , the L G defined by (,3.1) sliould IK; (^nliaueed fiirthiu- to imiirove t h e currtnit-mode sample and hold (CSH) operation.

There are two difierent ap])roaclies to enhance the L G : 1) increasing R^ by cascoding transistors [43| and 2) increasing G,,, by cascading G,„ stages |3,6,33,44 46|. A t first glance, tfi(S(! two solutions seem to provide a satisfactory iiiiprovcmeut as long as the L G is enhanced sufficiently. This Ls true oidy f o r the case of a continuons-time signal for which the feedback loop is always maintamed. A l t h o u g h cascodes are used i n many switdied capacitor circuits, e.g., a folded-cascode opamp, for the sample and hold operation i n wliich the finxlback-loop is being .switched and the swichiug mechanism is performed by IVIOS switches, the latter solution is preferable. Tins is because i t gives the possibility to supjiress the error fiom charge injeetiou and clock-feedthroiigh effects. As we

have seen f r o m (2.2), t:ascodiiig [Iocs not fielp regidating the voltage swing at the sampling node.

The voltage at the switching node Vu varies according to l\n/G„, inducuig a signal-dependent charg(; injection error winch leads to output signal distortion [47]. This signal-dependent error is a residt of the charge uijection and clock-feedthrongh via the gate-soince and gate-drain parasitic capacitances of a practical M O S device that forms switch S2 which Ls jilaced at the eircuit node w i t h signal-dependent voltage f l u c t u a t i o n ]30]. Having a larger Zi^ due to lower G,„, leads to a gi'eater VH swing and, subs(!<in(;iitly, a more signakdependeut error is obtained. On the other hand, f o r a larger G,„, a smaller voltage swing is what we obtain f r o m (2.2) and this helps the charge injection error to be<:oine less signal-dependent such that i t can be possibly c a n c e l l e d out by operating the CSH c i r c u i t i n a dilfijreiitial I'asluon. However, to have higher G,„, more power c o i L s u m p t i o n need to be sacrificed.

The G,„ euhmicenient tecliiu(iu(; can be realized as shown h i Fig. 3.3. I n F i g . 3.3(a), a voltage amplifier A„ is i i L s e r t e d in fiont o l the G „ , . This results i n a higher effective transconductance (hnt = A„G„,, which can be made very large. B y douig so, the ( i r r o r cmrent is forc(xl to be very sniaU by the larger L G resulting i n a very small variation o f Vji. Instead, the large voltage swing (V„u rge — A^Vii) is now rela,y(;d to the o u t p u t o f amplifier A„ which L> not where the switch is placed. Therefore the charge uijef:tion error can be considered sigual-uidepeuflent. To

realize voltage amphfier A„, another G,„ stage is u s c i d and uidortunal,(4y at k;ast one additional

time-constant is introduced by the para,sitic resistances and capacitances of all the active elements, wluch may lead to instability. Pole s p l i t t u i g can be applied to stabUize the system by changing the location of the holding capacitor Gn (winch is now used as a M i l l e r capacitor i n the sampling phase) and the polarities of amiilifiers /!„ and G„, as .shown iu F i g . 3.3(b) J33,45]. For proper fi equeney compensation, the bandwidth of the CSH w ü l be Imuterl. Tins is a finidamental trade oft' of a low-distortion CSH circuit. A l t h o u g h the charge injection error o f the single-ended circuit h i Fig. 3.3(b) can IK; made almost constant by the feedback tecimique mentioned above, the distortion still remains as long as the G,„ used Ls nonlinear.

To get rid of the charge injection error thereby minimizuig distortion of the output signal, a fidly dift'erential structure, as shown u i F i g . 3.4, is deshable. h i the case that the pair of switches

S2 is identical and the pair of liolduig caiiacitors C// are perfectly matched, the same amounts

of constant charge injection error voltages wiU appi^ar at the input tenninals of the G,„ w i t h the same amiilitude and phase. These error voltages are therefore seen as a common-mode signal and suppressed by the connnon-mode rejection capability of the G , „ . As a result, a lugh linearity CSH eircuit is obtained 13,44,47,48]. I t is w o r t h uotuig that even in the situation that b o t h G,„ circints are uonluiear, the complete error canc(4latioii meutionefl above can be achieved as long as capacitors Cu and switches S2 are identical aud the former are linear, and the sampling period is sufliciently

CHAPTER 3. SWTTCHED-CURRENT TECHNIQUE IN SUBTHRESHOLD CMOS

(b)

Figure 3 . C S H circuit w i t h LG eiüiancement w i t h (a) grouuded liolchug capacitor aud (b) Miller holding capacitor.

3.2. FEEDBACK ANALYSIS OF A 2''^^-GENEBATION Sl MEMORY CELL 25

long for complete settling of V,,. U i i l b r t m i a f e l y , for tlm cas(; that botli capacitors C„ are weakly nonlinear and/or switches .S'^ an; not matched p(;rfectly, the cliaige iiije<:tioii error voltages can only be caneeUed out pm-tially. Subsetiuently, output distortion w i l l be generated f r o m the residual input offset of G',,,2. Effeets o f t h i s imperfection w i l l be discussed analytically i n Sec. ;i.:i.4.

3.2.3 Stability and Tiansicnt Behavior

I n practice, the voltage amphficn- w i t h u i the feedback loop of Fig. 3.4 can be formed by a transcou-ductor w i t h high resistive loads, and the D C voltage levels at the mternal nodes iieetl to be; stabilized by common-mode feedback ( C M F B ) circuits. Including pm-asitic capacitances and resistances, a more practical CSH circuit can be represented by the macro-model shown in Fig. 3.5. A.ssuinuig aU the circuit elements are linear, o m i t t i n g thi; C M F B circuits and breaking the looji at the input of G',,,2, the; cucuit can be redrawn as i n Fig. 3.6 to find t k ; circuit's L G . It can be seen t h a t the circuit is now i n the f o r m of a generic two stage amplifier and tfie L G can be found to be [49]

V,' ^ 4 G „ . i G , „ 2 / ? i / r ; 2 ( l - f | f f f )

" i ^ " s'^RiRa (G1G2 + GiiGi + GnCi) + sG„aRJhG„ + 1 (3.3)

Its open-loop u n i t y gain frequency, pok;s and R H P zero ean be approximated to be

w„ = G „ , 2 / G „ , (3.4)

t^p2 = - G , „ i / ( C ' i - t G s ) , (3.5)

and

w ^ i = G , „ i / G „ , (3.6)

respectively.

Capacitors C„ arc; now serving two piirioosc;s: I ) the; holding capacitors and, 2) iiole-splitting compensation capacitors. I n this c:ase, the; latter pmpose d(;fines the value o l G„ to mauitain s t a b ü i t y . To achieve a phase margin (</>M) of 6Ü ", we set ajp2 > 2.2w„ aud G „ < C'l 4- G2. To estimate; lieiw fast a cloe;k signal can be; ap])he;d t o this CSH circuit, the sel44ing time, /.., of the; closed-loop response of the; system i n Fig. 3.5 ne;cds to be; fiamd. W i t h i n the; range of an acceptable normalized output setthng e;rror (e), ft om (,3.3) we e;an find that [50|

^ ^ 27rG„

G,„2\/4tan?!.A, ( I - t a n 0 „ ) ' ^''''^^

where the setthng error is ai)j)re)xiinati;d as

e = e x p ( - 7 r \ / t a u ? i M / ( 4 - t a n ^ w ) . (3.8)

Thus, we find the m a x i m u m samphng fiequeney o f tins sample and hole! as ./;._„,„x < 0.5^7^ Note that tlris analysis is based on the assinnption that the oii-resistances o f aU MOS switejies and parasitic resistaiice;s miel capacitances o f the C M F B chcuits are small enough to create very small time; constants compare;d to C V / / G , „ 2 , and i t is vallei f o r (jy^, gre;ater than 45 ° . Note; that, u i this case, G,„2 Is a large-signal t r a i L s c o n d n e t a n c e which is not eiemstant b u t elependeut on the i n p u t signal amiilitude as shown in (3.19) or (3.20).

CIIArTEll 3. SmTCHED-CURRENT TECHNIQUE IN SUBTHRESHOLD CMOS

DESIGN CONSlDEnATION: GLASS-A AND CLASS-AD 2i

0 . 5 / B I V V O . S / B ,

( a ) ( b )

F i g i i i i ! ,'!.7: Subtlire.shold traiisc.oiuluctors. (a) Class-A. (b) Class-AB.

3.3 Design Consideration: Class-A and C l a s s - A B

For low-voltag(; design, defined by V D D < 2Kti, [51], there are two choices of s n l j - t l n t s h o l d cu-cuit c^ells to replace G,,,^ in the previous section to form a CSH circuit: class-A m i d class-AB traiiscon-duc;tors [6[, as shown i n Figures. 3.7(a) and .3.7(b), respectively. A.ssmuing all the transistors are working i n weak inversion saturation ( V ^ s < Vth and VDS > 4 V T ) |25[, the large-signal characteris-tics o f t h e elas.s-A and class-AB transconduetors can be expressed by

a n i l /„.i = i - ^ ^ ^ t a i i h f * ^ ± ^ 2 2 V "inrVr ^ t a i i h f ^ 2 V 2 ' " p V r /,„, = ^ ^ ^ ^ ^ = 21,2 shdi f - 21,2 sinh ( ^ 2 V " / ' V T / V " / ' V T (3.9) (3.10)

respectively, where np is tli<; subthreshold slope factor of the pMOSTs and VV = kT/q is the thermal voltage.

To cteign the CSH to be power ellicieiit and to liandk; an input signal as large as possible, the large-signal chara<-,teristics of (3.9) and (3.10) should be nciither neglected nor even approximated. In this section, we provide coin[)arative disciLssions on several design aspects between class-A and class-AB CSH f:ircuits.

3.3.1 Current Consumption

Considering current consumption, we divide the circuit operation into two cases: I ) static, which is flefined as the situation i u which there is uo incoming signal, and 2) dynamic, wliich is the situation in which the cm-rent consumption varies w i t h the uiput signal. For the class-A circuit (Fig. 3.7(a)), t i l l ! current consumption can be found for both situations to be

28 CHAPTER 3. SWITCHED-CURRENT TECHNIQUE IN SUBTHRESHOLD CMOS

By contrast, the class-AB circuit (Fig. .'!.7(b)) allows the curreut to go higher than its quiescent cnrrent level for the dyuaniic situation. T h i s <;ntails a more complex circuit and hence leads to more dynamic ciu'rent consumption ( / d y n a m i c A B ) as shown helow [ti]

f . l y , i a i , i i c A B = 27B2 + 2702 exp (— - \ - 2/^2 exp — ^

T h e static power eonsiunption of this class-AB c h c m t ean be f o u n d f r o m (3.12) by settiug VJa to zero. T h i s results i u

/ s t a t i c A B = ('hn- (3.13)

In order t o come to a reasonable eomparison betw(;en tli(!se classes of chcuit operation, we use the condiiion ihal. jirovides a static condition w i t h the same oj,, and (pM- This comlition can be satisfied by cqnatuig the small-signal transconductance gains of both circnits, i.e., _(y„,/i =

g„u\B-From (3.9) and (3.10) and by considering small-signal operation, we can approximate that

and

y„iAB = T1-- (3.15) npVr

F'or g,„A = HmAB, we then have Ipi = S / B 2 , arid tins leads to

/ s t a t i r A B =^ 0 . 7 5 / s t a t i c A • (3.16)

From now on, we w i l l iLse tins condition to analyze the circuit performance.

3.3.2 Signal Exclusion and Drivability

A f t e r setting Ipi = ^IB2, let's consider (3.9) and (3.10) again. I n the case t h a t the circuits i n Figs. 3.7(a) and 3.7(b) are working as transconduetors and that the input terniuials are driven by the same dift'erential uiput voltage, Vi,i, tlic o u t p u t currents, lad, for b o t h cases are shown i n F i g . 3.8 ( i i j i — SIB2 = S i i A ) . I t can be seen, as expected, that for a siiiaU Vui b o t h circuits behave hnearly giving the same trancoiiductance. For Via > 25 ni"V, the output curreut o l the cla.ss-A circuit starts saturatuig but, lor the class-AB circuit, i t keeps increasuig exponentially. This implies t h a t , for the CSH circiut using class-A circuitry, we can not apply an in|)iit current larger than its bias current. However, using class-AB cu-cniti-y the input current magiutiide can be higher than i n the case o f t h e ela.ss-A circuit.

3.3. DESIGN CONSIDERATION: CLASS-A AND CLASS-AD 20 10 T3 -10 -20 -0.1 -0.05 0 0.05 0.1 Vid.V

Figure 3.8: I - V trau.sfer characteristics o l tlie subthiushold transconduetors.

Tins ar-gninent becomes clearer when we operate the transeondiictors as non-hnear transimpedance amplihers based ou the inverse functions o l (3.9) aud (3.10). Ih;nce, we apply input current and observe the behavior of o u t p u t voltage Vod for th(! entire range of the varied ha- Here, we re-define variables / i d - > / , v and K d H - V y to be used i n the inverse fimction o l (3.9) aud (3.10). Now, the o u t p u t currents and the input voltages of the transconduetors become i n i n i t and o u t p u t variables of the traiLsimpedance ani|)lifiers, respectively, as shown below.

Vy = 2».„Vrtaiih-> f ^ ) (3.17)

and

VY = n,VT^m\C'[Jf-^ , (3.18)

f o r the case of class-A and class-AB, respectively.

These trairsfiir characteristics are plotted and shown in F i g . 3.9. This situation can happeen ideally when negative feedback is appfied and the L G is large enough to make the voltage at the u i p u t nodes constant. Then input current lx can be apphed (see F i g . 3.5). As Ix comes close to 1 BI (8 u A ) , the voltage is driven to the snjiply voltage f o r a class-A ciicnit. This is an undeshed feature; fiir low voltage circuits in general since this largo voltage excursion w i l l push some chcuit e l e u K m t s (transistors i n this case) out o l their proper operating region and eventually degrades the entire c:ircuit iierformance. For elas,s-AB, the eircuit behaves in an opposite way such that, although the

cmrent goes h i g h , the voltage can be kept low. This results f r o m the compressive nature of class-AB

operation i i M h c a t e d by (3.18).

Another ü n p o r t a n t design parameter t h a t should be jiairl atteul ion to is t h e largij-signal traiiscou-ductance Gm- T h i s parameter influences t h e dynamic ciremt's L G . Taking t h e first derivatives w i t h respect to Vd o l (3.9), (3.10) a n d substituting (3.17) and (3.18) into tlie results, we can find t h a t

and

Gu.AB - -^%^cosli f s i i d r ' f K T ^ l ) . (.'i-SO)

T 1

C l a s s - A B / / C l a s s A

-CHAPTER 3. SmTCHED-CURRENT TECHNIQUE IN SUDTHRESIIOLD CMOS

for class-A and class-AB circuits, rcsjicctively.

To give uiore iusiglit, (3.19) and (3.2Ü) arc sliown g T a p l i i c a l l y i u Fig. 3.10. As one can see, G,nA decreases wli<;n |/ia| > 1 u A goes high wliile G,„AB is eidianccd. From these curves, we can predict t h a t the accuracy (charge injection error canceUatiou) and bandwitlth (see E q . 3.4) of the clas.s-A CSH circuit w i l l be degraded when a large is apjihed since tin; L G becomes smaller. For tlu; class-AB CSH eircuit, the accuracy and bandwidth will be enhanced to some extent. I f Tui keeps increasing the ciremt will requhe a longer setthng time and even oscillation can occiu (more detads w i l l be given i n the next chapter). This Is a serious problem so t h a t the m a x u n u m magnitude of

needs to be identified. This w i l l be explained i n the next chapter as weU.

3.3.3 Noise

Since b o t h the clas.s-A and A B CSH circuit share the same G,„i stage, tmly the noise contribution fi'om G',,,2 w i l l be considered here. The flicker noise is neglected Ior simplicity since i t is assimred t h a t i t w i f l be uuUified by an aiito-zeroing meelianism o f t h e CSH ciremt [52]. Only the ciuTent shot noise, that is associated w i t h the drain and source barriers t h a t control the carrier concentration h i the charmel of the transistors, is considered here [25]. Since the spectral rleirsity of this type of noise is white, i t camiot be uuUified by the; auto-zerouig niechanism. The output cmrent shot noise of G , „ 2 will be smnpled and stored on G ; , . T i n ; stored noise w i l l be converted into current noise agam at the output d i n u i g the hold phase. This sampled noise will be added to the noise generated by Gn,2 dnring the hold phase. Due to aliashig, this type of noise becomes dominant [52].