Crystallographic Silicon-Etching for Ultra-High Aspect-Ratio FinFET

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Vladimir Jovanović1_{, Tomislav Suligoj}1_{, Lis K. Nanver}2 1_{University of Zagreb, Zagreb, Croatia}

2_{Delft University of Technology, Delft, The Netherlands}

vladimir.jovanovic@fer.hr The challenge of moving towards ultimate CMOS scaling-limit depends on the ability to contain short-channel effects (SCE). The double- or triple-gate FinFET is considered the best candidate to suceed planar bulk devices for the 22 nm node and beyond in various applications, such as digital logic [1], SRAM [2], DRAM [1] and Flash memory [3]. FinFETs offer better gate control of the channel which reduces SCE. A small width of the etched fin is necessary for good SCE control, and at the same time high quality of the etched surfaces is needed to reduce surface scattering. Additionally, with the channel positioned vertically to the wafer surface, tall silicon fins can significantly increase the driving current of the FinFET.

Anisotropic properties of silicon etching using tethra-methyl-ammonium-hydroxide (TMAH) have already been utilized on (110) silicon wafers to form nearly perfectly vertical fin structures with (111) orientation of active sidewalls [4]. The (111) crystal orientation reduces electron mobility, but improves hole mobility [5], resulting in more balanced n- and p-type devices. Moreover, after TMAH etch the surface is crystallographically smooth [6, 7] which reduces surface scattering and ultra-thin thermal oxides show as good or better quality on (111) surface compared to standard (100) orientation [8].

This paper presents fin processing using TMAH etching on (110) bulk silicon wafers to produce vertical fins with ultra-high aspect-ratio (1.15 µm / 30 nm). The use of bulk silicon wafers offers significant cost reduction compared to the SOI wafers used in previous work on TMAH-etched fins [4]. Additionally, arbitrarily tall silicon fins can be processed on bulk wafers. Silicon-nitride spacers are used as the hard-mask for the etching in 25% TMAH heated to 85°C. Conformal deposition of silicon dioxide followed by chemical-mechanical polishing (CMP) and oxide etch-back is used to isolate the fins [9]. The gate stack of thermally grown silicon dioxide and n+ doped polysilicon gate is formed next, followed by wet etching of polysilicon, also in TMAH. Source and drain regions are implanted at 60° tilt angle, isolating oxide is deposited, implanted dopants are thermally annealed and contacts and metal lines are formed.

Analysis of structure cross-sections using SEM confirm record high, more than 600 nm tall active parts of silicon fins. Both, n- and p-type long-channel devices (Lg=410 nm) are successfully demonstrated and exhibit

low leakage and excellent subthreshold performance. The developed silicon fin-etching and isolation scheme allows processing of FinFETs with extremely high current driveability per single fin and very efficient use of the silicon surface area for the required driving current. The increasing attention directed towards the use of (110) silicon wafers for bulk CMOS for maximizing the hole mobility, places the described process as a very promising option for combined bulk CMOS and FinFET ICs.

Keywords: FinFET, TMAH etching, (110) silicon wafers References

[1] Kim et al., IEDM Tech. Dig., p.35, 2007 [2] Inaba et al., IEDM Tech. Dig., p.487, 2007 [3] Sung et al., VLSI Symp. Tech. Dig., p.86, 2006 [4] Liu et al., IEEE EDL, p.484, 2003

[5] Takagi et al., IEEE TED, p.2363, 1994

[6] Hölke et al., Micromech. Microeng., p.51, 1999 [7] Tabata et al., Sens. and Act. A, p.51, 1992 [8] Sasaki Momose et al., IEEE TED, p.1597, 2002 [9] Suligoj et al., ECSSL., p.G125, 2005

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Fig. 1. SEM image of silicon fins etched in TMAH solution (25%, 85ºC). Pad regions are used for contact placement (left). The fins are mechanically stable, even for long sizes (b).

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Fig. 2. SEM image of oxide-isolated silicon fins with n+

-polysilicon gates. A single-fin transistor (a). Long gates over long fins demonstrate good process controllability (b).

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Fig. 3. SEM image of silicon fin after oxide CMP and etch-back (a). SEM image of FinFET cross-section (b). Active device part is approximately 630 nm.

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Fig. 4. Transfer characteristics of p-channel (a) and n-channel (b) FinFETs. Nearly ideal subthreshold slope and low-leakage are achieved.

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Fig. 5. Output characteristics of p-channel (a) and n-channel (b) FinFETs. Measured pFET drive capability almost matches nFET device.