LM3S5D91

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Stellaris ^® LM3S5D91 Microcontroller

D ATA S H E E T

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Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris

http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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List of Figures

Figure 1-1. Stellaris LM3S5D91 Microcontroller High-Level Block Diagram ... 46

Figure 2-1. CPU Block Diagram ... 69

Figure 2-2. TPIU Block Diagram ... 70

Figure 2-3. Cortex-M3 Register Set ... 72

Figure 2-4. Bit-Band Mapping ... 93

Figure 2-5. Data Storage ... 94

Figure 2-6. Vector Table ... 100

Figure 2-7. Exception Stack Frame ... 102

Figure 3-1. SRD Use Example ... 116

Figure 4-1. JTAG Module Block Diagram ... 177

Figure 4-2. Test Access Port State Machine ... 180

Figure 4-3. IDCODE Register Format ... 186

Figure 4-4. BYPASS Register Format ... 186

Figure 4-5. Boundary Scan Register Format ... 187

Figure 5-1. Basic RST Configuration ... 191

Figure 5-2. External Circuitry to Extend Power-On Reset ... 191

Figure 5-3. Reset Circuit Controlled by Switch ... 192

Figure 5-4. Power Architecture ... 195

Figure 5-5. Main Clock Tree ... 197

Figure 6-1. Internal Memory Block Diagram ... 293

Figure 7-1. μDMA Block Diagram ... 340

Figure 7-2. Example of Ping-Pong μDMA Transaction ... 347

Figure 7-3. Memory Scatter-Gather, Setup and Configuration ... 349

Figure 7-4. Memory Scatter-Gather, μDMA Copy Sequence ... 350

Figure 7-5. Peripheral Scatter-Gather, Setup and Configuration ... 352

Figure 7-6. Peripheral Scatter-Gather, μDMA Copy Sequence ... 353

Figure 8-1. Digital I/O Pads ... 406

Figure 8-2. Analog/Digital I/O Pads ... 407

Figure 8-3. GPIODATA Write Example ... 408

Figure 8-4. GPIODATA Read Example ... 408

Figure 9-1. EPI Block Diagram ... 459

Figure 9-2. SDRAM Non-Blocking Read Cycle ... 467

Figure 9-3. SDRAM Normal Read Cycle ... 467

Figure 9-4. SDRAM Write Cycle ... 468

Figure 9-5. Example Schematic for Muxed Host-Bus 16 Mode ... 474

Figure 9-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 ... 476

Figure 9-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 ... 477

Figure 9-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0, RDHIGH = 0 ... 477

Figure 9-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual CSn ... 478

Figure 9-10. Continuous Read Mode Accesses ... 478

Figure 9-11. Write Followed by Read to External FIFO ... 479

Figure 9-12. Two-Entry FIFO ... 479

Figure 9-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ... 483

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Figure 9-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,

WRCYC=1 ... 483

Figure 9-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ... 484

Figure 9-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ... 484

Figure 9-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ... 486

Figure 9-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ... 487

Figure 9-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ... 487

Figure 10-1. GPTM Module Block Diagram ... 533

Figure 10-2. Timer Daisy Chain ... 539

Figure 10-3. Input Edge-Count Mode Example ... 541

Figure 10-4. 16-Bit Input Edge-Time Mode Example ... 542

Figure 10-5. 16-Bit PWM Mode Example ... 543

Figure 11-1. WDT Module Block Diagram ... 580

Figure 12-1. Implementation of Two ADC Blocks ... 605

Figure 12-2. ADC Module Block Diagram ... 606

Figure 12-3. ADC Sample Phases ... 610

Figure 12-4. Doubling the ADC Sample Rate ... 611

Figure 12-5. Skewed Sampling ... 611

Figure 12-6. Sample Averaging Example ... 612

Figure 12-7. ADC Input Equivalency Diagram ... 613

Figure 12-8. Internal Voltage Conversion Result ... 614

Figure 12-9. External Voltage Conversion Result with 3.0-V Setting ... 615

Figure 12-10. External Voltage Conversion Result with 1.0-V Setting ... 615

Figure 12-11. Differential Sampling Range, V_{IN_ODD}= 1.5 V ... 617

Figure 12-14. Internal Temperature Sensor Characteristic ... 619

Figure 12-15. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ... 621

Figure 12-16. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ... 622

Figure 12-17. High-Band Operation (CIC=0x3 and/or CTC=0x3) ... 623

Figure 13-1. UART Module Block Diagram ... 686

Figure 13-2. UART Character Frame ... 689

Figure 13-3. IrDA Data Modulation ... 691

Figure 13-4. LIN Message ... 693

Figure 13-5. LIN Synchronization Field ... 694

Figure 14-1. SSI Module Block Diagram ... 750

Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ... 754

Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ... 754

Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ... 755

Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ... 755

Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ... 756

Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ... 757

Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ... 757

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Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ... 758

Figure 14-10. MICROWIRE Frame Format (Single Frame) ... 759

Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ... 760

Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ... 760

Figure 15-1. I²C Block Diagram ... 792

Figure 15-2. I²C Bus Configuration ... 793

Figure 15-3. START and STOP Conditions ... 794

Figure 15-4. Complete Data Transfer with a 7-Bit Address ... 794

Figure 15-5. R/S Bit in First Byte ... 795

Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ... 795

Figure 15-7. Master Single TRANSMIT ... 799

Figure 15-8. Master Single RECEIVE ... 800

Figure 15-9. Master TRANSMIT with Repeated START ... 801

Figure 15-10. Master RECEIVE with Repeated START ... 802

Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated START ... 803

Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated START ... 804

Figure 15-13. Slave Command Sequence ... 805

Figure 16-1. I²S Block Diagram ... 830

Figure 16-2. I²S Data Transfer ... 833

Figure 16-3. Left-Justified Data Transfer ... 833

Figure 16-4. Right-Justified Data Transfer ... 833

Figure 17-1. CAN Controller Block Diagram ... 867

Figure 17-2. CAN Data/Remote Frame ... 869

Figure 17-3. Message Objects in a FIFO Buffer ... 877

Figure 17-4. CAN Bit Time ... 881

Figure 18-1. USB Module Block Diagram ... 918

Figure 19-1. Analog Comparator Module Block Diagram ... 1057

Figure 19-2. Structure of Comparator Unit ... 1059

Figure 19-3. Comparator Internal Reference Structure ... 1059

Figure 20-1. PWM Module Diagram ... 1072

Figure 20-2. PWM Generator Block Diagram ... 1072

Figure 20-3. PWM Count-Down Mode ... 1077

Figure 20-4. PWM Count-Up/Down Mode ... 1077

Figure 20-5. PWM Generation Example In Count-Up/Down Mode ... 1078

Figure 20-6. PWM Dead-Band Generator ... 1078

Figure 21-1. QEI Block Diagram ... 1149

Figure 21-2. Quadrature Encoder and Velocity Predivider Operation ... 1152

Figure 22-1. 100-Pin LQFP Package Pin Diagram ... 1171

Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ... 1172

Figure 25-1. Load Conditions ... 1255

Figure 25-2. JTAG Test Clock Input Timing ... 1256

Figure 25-3. JTAG Test Access Port (TAP) Timing ... 1256

Figure 25-4. Power-On Reset Timing ... 1257

Figure 25-5. Brown-Out Reset Timing ... 1257

Figure 25-6. Power-On Reset and Voltage Parameters ... 1258

Figure 25-7. External Reset Timing (RST) ... 1258

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Figure 25-8. Software Reset Timing ... 1258

Figure 25-9. Watchdog Reset Timing ... 1259

Figure 25-10. MOSC Failure Reset Timing ... 1259

Figure 25-11. SDRAM Initialization and Load Mode Register Timing ... 1264

Figure 25-12. SDRAM Read Timing ... 1264

Figure 25-13. SDRAM Write Timing ... 1265

Figure 25-14. Host-Bus 8/16 Mode Read Timing ... 1266

Figure 25-15. Host-Bus 8/16 Mode Write Timing ... 1266

Figure 25-16. Host-Bus 8/16 Mode Muxed Read Timing ... 1267

Figure 25-17. Host-Bus 8/16 Mode Muxed Write Timing ... 1267

Figure 25-18. General-Purpose Mode Read and Write Timing ... 1268

Figure 25-19. General-Purpose Mode iRDY Timing ... 1268

Figure 25-20. ADC Input Equivalency Diagram ... 1270

Figure 25-21. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ... 1271

Figure 25-22. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ... 1271

Figure 25-23. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ... 1272

Figure 25-24. I²C Timing ... 1273

Figure 25-25. I²S Master Mode Transmit Timing ... 1273

Figure 25-26. I²S Master Mode Receive Timing ... 1274

Figure 25-27. I²S Slave Mode Transmit Timing ... 1274

Figure 25-28. I²S Slave Mode Receive Timing ... 1274

Figure C-1. Stellaris LM3S5D91 100-Pin LQFP Package Dimensions ... 1331

Figure C-2. 100-Pin LQFP Tray Dimensions ... 1333

Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ... 1334

Figure C-4. Stellaris LM3S5D91 108-Ball BGA Package Dimensions ... 1335

Figure C-5. 108-Ball BGA Tray Dimensions ... 1337

Figure C-6. 108-Ball BGA Tape and Reel Dimensions ... 1338

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List of Tables

Table 1. Revision History ... 39

Table 2. Documentation Conventions ... 43

Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ... 72

Table 2-2. Processor Register Map ... 73

Table 2-3. PSR Register Combinations ... 78

Table 2-4. Memory Map ... 86

Table 2-5. Memory Access Behavior ... 89

Table 2-6. SRAM Memory Bit-Banding Regions ... 91

Table 2-7. Peripheral Memory Bit-Banding Regions ... 91

Table 2-8. Exception Types ... 97

Table 2-9. Interrupts ... 98

Table 2-10. Exception Return Behavior ... 103

Table 2-11. Faults ... 103

Table 2-12. Fault Status and Fault Address Registers ... 105

Table 2-13. Cortex-M3 Instruction Summary ... 107

Table 3-1. Core Peripheral Register Regions ... 110

Table 3-2. Memory Attributes Summary ... 113

Table 3-3. TEX, S, C, and B Bit Field Encoding ... 116

Table 3-4. Cache Policy for Memory Attribute Encoding ... 117

Table 3-5. AP Bit Field Encoding ... 117

Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ... 117

Table 3-7. Peripherals Register Map ... 118

Table 3-8. Interrupt Priority Levels ... 145

Table 3-9. Example SIZE Field Values ... 173

Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ... 177

Table 4-2. JTAG_SWD_SWO Signals (108BGA) ... 178

Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion ... 179

Table 4-4. JTAG Instruction Register Commands ... 184

Table 5-1. System Control & Clocks Signals (100LQFP) ... 188

Table 5-2. System Control & Clocks Signals (108BGA) ... 188

Table 5-3. Reset Sources ... 189

Table 5-4. Clock Source Options ... 196

Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ... 198

Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ... 198

Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 ... 199

Table 5-8. System Control Register Map ... 203

Table 5-9. RCC2 Fields that Override RCC Fields ... 225

Table 6-1. Flash Memory Protection Policy Combinations ... 297

Table 6-2. User-Programmable Flash Memory Resident Registers ... 301

Table 6-3. Flash Register Map ... 301

Table 7-1. μDMA Channel Assignments ... 341

Table 7-2. Request Type Support ... 343

Table 7-3. Control Structure Memory Map ... 344

Table 7-4. Channel Control Structure ... 344

Table 7-5. μDMA Read Example: 8-Bit Peripheral ... 354

Table 7-6. μDMA Interrupt Assignments ... 355

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Table 7-7. Channel Control Structure Offsets for Channel 30 ... 356

Table 7-8. Channel Control Word Configuration for Memory Transfer Example ... 356

Table 7-9. Channel Control Structure Offsets for Channel 7 ... 357

Table 7-10. Channel Control Word Configuration for Peripheral Transmit Example ... 358

Table 7-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ... 359

Table 7-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ... 360

Table 7-13. μDMA Register Map ... 362

Table 8-1. GPIO Pins With Non-Zero Reset Values ... 401

Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ... 401

Table 8-3. GPIO Pins and Alternate Functions (108BGA) ... 403

Table 8-4. GPIO Pad Configuration Examples ... 410

Table 8-5. GPIO Interrupt Configuration Example ... 411

Table 8-7. GPIO Register Map ... 412

Table 9-1. External Peripheral Interface Signals (100LQFP) ... 459

Table 9-2. External Peripheral Interface Signals (108BGA) ... 460

Table 9-3. EPI SDRAM Signal Connections ... 465

Table 9-4. Capabilities of Host Bus 8 and Host Bus 16 Modes ... 469

Table 9-5. EPI Host-Bus 8 Signal Connections ... 470

Table 9-6. EPI Host-Bus 16 Signal Connections ... 472

Table 9-7. EPI General Purpose Signal Connections ... 481

Table 9-8. External Peripheral Interface (EPI) Register Map ... 487

Table 10-1. Available CCP Pins ... 533

Table 10-2. General-Purpose Timers Signals (100LQFP) ... 534

Table 10-3. General-Purpose Timers Signals (108BGA) ... 535

Table 10-4. General-Purpose Timer Capabilities ... 536

Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes ... 537

Table 10-6. 16-Bit Timer With Prescaler Configurations ... 538

Table 10-7. Counter Values When the Timer is Enabled in RTC Mode ... 539

Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ... 540

Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ... 541

Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ... 542

Table 10-11. Timers Register Map ... 547

Table 11-1. Watchdog Timers Register Map ... 582

Table 12-1. ADC Signals (100LQFP) ... 606

Table 12-2. ADC Signals (108BGA) ... 607

Table 12-3. Samples and FIFO Depth of Sequencers ... 608

Table 12-4. Differential Sampling Pairs ... 616

Table 12-5. ADC Register Map ... 624

Table 13-1. UART Signals (100LQFP) ... 687

Table 13-2. UART Signals (108BGA) ... 687

Table 13-3. Flow Control Mode ... 693

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Table 13-4. UART Register Map ... 698

Table 14-1. SSI Signals (100LQFP) ... 751

Table 14-2. SSI Signals (108BGA) ... 751

Table 14-3. SSI Register Map ... 762

Table 15-1. I2C Signals (100LQFP) ... 792

Table 15-2. I2C Signals (108BGA) ... 792

Table 15-3. Examples of I²C Master Timer Period versus Speed Mode ... 796

Table 15-4. Inter-Integrated Circuit (I²C) Interface Register Map ... 806

Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ... 812

Table 16-1. I2S Signals (100LQFP) ... 831

Table 16-2. I2S Signals (108BGA) ... 831

Table 16-3. I²S Transmit FIFO Interface ... 834

Table 16-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ... 835

Table 16-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ... 835

Table 16-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz) ... 836

Table 16-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz) ... 836

Table 16-8. I²S Receive FIFO Interface ... 838

Table 16-9. Audio Formats Configuration ... 840

Table 16-10. Inter-Integrated Circuit Sound (I²S) Interface Register Map ... 841

Table 17-1. Controller Area Network Signals (100LQFP) ... 868

Table 17-2. Controller Area Network Signals (108BGA) ... 868

Table 17-3. Message Object Configurations ... 874

Table 17-4. CAN Protocol Ranges ... 881

Table 17-5. CANBIT Register Values ... 881

Table 17-6. CAN Register Map ... 885

Table 18-1. USB Signals (100LQFP) ... 918

Table 18-2. USB Signals (108BGA) ... 919

Table 18-3. Remainder (MAXLOAD/4) ... 931

Table 18-4. Actual Bytes Read ... 931

Table 18-5. Packet Sizes That Clear RXRDY ... 931

Table 18-6. Universal Serial Bus (USB) Controller Register Map ... 933

Table 19-1. Analog Comparators Signals (100LQFP) ... 1057

Table 19-2. Analog Comparators Signals (108BGA) ... 1058

Table 19-3. Internal Reference Voltage and ACREFCTL Field Values ... 1060

Table 19-4. Analog Comparators Register Map ... 1061

Table 20-1. PWM Signals (100LQFP) ... 1073

Table 20-2. PWM Signals (108BGA) ... 1074

Table 20-3. PWM Register Map ... 1082

Table 21-1. QEI Signals (100LQFP) ... 1149

Table 21-2. QEI Signals (108BGA) ... 1150

Table 21-3. QEI Register Map ... 1154

Table 23-1. GPIO Pins With Default Alternate Functions ... 1173

Table 23-2. Signals by Pin Number ... 1174

Table 23-3. Signals by Signal Name ... 1186

Table 23-4. Signals by Function, Except for GPIO ... 1197

Table 23-5. GPIO Pins and Alternate Functions ... 1206

Table 23-6. Possible Pin Assignments for Alternate Functions ... 1209

Table 23-7. Signals by Pin Number ... 1212

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Table 23-8. Signals by Signal Name ... 1225

Table 23-9. Signals by Function, Except for GPIO ... 1236

Table 23-10. GPIO Pins and Alternate Functions ... 1245

Table 23-11. Possible Pin Assignments for Alternate Functions ... 1248

Table 23-12. Connections for Unused Signals (100-Pin LQFP) ... 1251

Table 23-13. Connections for Unused Signals (108-Ball BGA) ... 1251

Table 24-1. Temperature Characteristics ... 1253

Table 24-2. Thermal Characteristics ... 1253

Table 24-3. ESD Absolute Maximum Ratings ... 1253

Table 25-1. Maximum Ratings ... 1254

Table 25-2. Recommended DC Operating Conditions ... 1254

Table 25-3. JTAG Characteristics ... 1255

Table 25-4. Power Characteristics ... 1257

Table 25-5. Reset Characteristics ... 1258

Table 25-6. LDO Regulator Characteristics ... 1259

Table 25-7. Phase Locked Loop (PLL) Characteristics ... 1259

Table 25-8. Actual PLL Frequency ... 1260

Table 25-9. PIOSC Clock Characteristics ... 1260

Table 25-10. 30-kHz Clock Characteristics ... 1260

Table 25-11. Main Oscillator Clock Characteristics ... 1261

Table 25-12. Supported MOSC Crystal Frequencies ... 1261

Table 25-13. System Clock Characteristics with ADC Operation ... 1262

Table 25-14. System Clock Characteristics with USB Operation ... 1262

Table 25-15. Sleep Modes AC Characteristics ... 1262

Table 25-16. Flash Memory Characteristics ... 1262

Table 25-17. GPIO Module Characteristics ... 1263

Table 25-18. EPI SDRAM Characteristics ... 1263

Table 25-19. EPI SDRAM Interface Characteristics ... 1263

Table 25-20. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ... 1265

Table 25-21. EPI General-Purpose Interface Characteristics ... 1267

Table 25-22. ADC Characteristics ... 1269

Table 25-23. ADC Module External Reference Characteristics ... 1270

Table 25-24. ADC Module Internal Reference Characteristics ... 1270

Table 25-25. SSI Characteristics ... 1270

Table 25-26. I²C Characteristics ... 1272

Table 25-27. I²S Master Clock (Receive and Transmit) ... 1273

Table 25-28. I²S Slave Clock (Receive and Transmit) ... 1273

Table 25-29. I²S Master Mode ... 1273

Table 25-30. I²S Slave Mode ... 1274

Table 25-31. USB Controller Characteristics ... 1275

Table 25-32. Analog Comparator Characteristics ... 1275

Table 25-33. Analog Comparator Voltage Reference Characteristics ... 1275

Table 25-34. Nominal Power Consumption ... 1275

Table 25-35. Detailed Current Specifications ... 1276

Table B-1. Part Ordering Information ... 1329

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List of Registers

The Cortex-M3 Processor ... 67

Register 1: Cortex General-Purpose Register 0 (R0) ... 74

Register 14: Stack Pointer (SP) ... 75

Register 15: Link Register (LR) ... 76

Register 16: Program Counter (PC) ... 77

Register 17: Program Status Register (PSR) ... 78

Register 18: Priority Mask Register (PRIMASK) ... 82

Register 19: Fault Mask Register (FAULTMASK) ... 83

Register 20: Base Priority Mask Register (BASEPRI) ... 84

Register 21: Control Register (CONTROL) ... 85

Cortex-M3 Peripherals ... 110

Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ... 121

Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 ... 123

Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ... 124

Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 ... 125

Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ... 126

Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 ... 127

Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ... 128

Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ... 129

Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ... 130

Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ... 131

Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 ... 132

Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ... 133

Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ... 134

Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ... 135

Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C ... 135

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Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00 ... 137

Register 29: Auxiliary Control (ACTLR), offset 0x008 ... 138

Register 30: CPU ID Base (CPUID), offset 0xD00 ... 140

Register 31: Interrupt Control and State (INTCTRL), offset 0xD04 ... 141

Register 32: Vector Table Offset (VTABLE), offset 0xD08 ... 144

Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C ... 145

Register 34: System Control (SYSCTRL), offset 0xD10 ... 147

Register 35: Configuration and Control (CFGCTRL), offset 0xD14 ... 149

Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18 ... 151

Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C ... 152

Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20 ... 153

Register 39: System Handler Control and State (SYSHNDCTRL), offset 0xD24 ... 154

Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28 ... 158

Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C ... 164

Register 42: Memory Management Fault Address (MMADDR), offset 0xD34 ... 165

Register 43: Bus Fault Address (FAULTADDR), offset 0xD38 ... 166

Register 44: MPU Type (MPUTYPE), offset 0xD90 ... 167

Register 45: MPU Control (MPUCTRL), offset 0xD94 ... 168

Register 46: MPU Region Number (MPUNUMBER), offset 0xD98 ... 170

Register 47: MPU Region Base Address (MPUBASE), offset 0xD9C ... 171

Register 48: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ... 171

Register 49: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ... 171

Register 50: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ... 171

Register 51: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ... 173

Register 52: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 ... 173

Register 53: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 ... 173

Register 54: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 ... 173

System Control ... 188

Register 1: Device Identification 0 (DID0), offset 0x000 ... 206

Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ... 208

Register 3: Raw Interrupt Status (RIS), offset 0x050 ... 209

Register 4: Interrupt Mask Control (IMC), offset 0x054 ... 211

Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 ... 213

Register 6: Reset Cause (RESC), offset 0x05C ... 215

Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ... 217

Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ... 222

Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ... 223

Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ... 225

Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ... 228

Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ... 229

Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ... 231

Register 14: I²S MCLK Configuration (I2SMCLKCFG), offset 0x170 ... 232

Register 15: Device Identification 1 (DID1), offset 0x004 ... 234

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Register 16: Device Capabilities 0 (DC0), offset 0x008 ... 236

Register 20: Device Capabilities 4 (DC4), offset 0x01C ... 245

Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C ... 254

Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ... 257

Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ... 259

Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ... 260

Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ... 263

Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ... 266

Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ... 276

Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ... 284

Register 36: Software Reset Control 0 (SRCR0), offset 0x040 ... 286

Internal Memory ... 293

Register 1: Flash Memory Address (FMA), offset 0x000 ... 304

Register 2: Flash Memory Data (FMD), offset 0x004 ... 305

Register 3: Flash Memory Control (FMC), offset 0x008 ... 306

Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ... 309

Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ... 310

Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ... 311

Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ... 312

Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ... 313

Register 9: Flash Control (FCTL), offset 0x0F8 ... 314

Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C ... 315

Register 11: ROM Control (RMCTL), offset 0x0F0 ... 316

Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ... 317

Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ... 318

Register 14: Boot Configuration (BOOTCFG), offset 0x1D0 ... 319

Register 15: User Register 0 (USER_REG0), offset 0x1E0 ... 321

Register 18: User Register 3 (USER_REG3), offset 0x1EC ... 324

Register 19: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ... 325

Register 21: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ... 327

(22)

Register 25: Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ... 331 Register 26: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ... 332 Register 27: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ... 333 Register 28: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ... 334 Register 29: Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ... 335 Register 30: Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ... 336 Register 31: Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ... 337 Register 32: Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ... 338 Micro Direct Memory Access (μDMA) ... 339 Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ... 364 Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ... 365 Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 ... 366 Register 4: DMA Status (DMASTAT), offset 0x000 ... 371 Register 5: DMA Configuration (DMACFG), offset 0x004 ... 373 Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 ... 374 Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C ... 375 Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ... 376 Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ... 377 Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 ... 378 Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ... 379 Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 ... 380 Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ... 381 Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ... 382 Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ... 383 Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 ... 384 Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ... 385 Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ... 386 Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C ... 387 Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ... 388 Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ... 389 Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 ... 390 Register 23: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ... 391 Register 24: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ... 392 Register 25: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ... 393 Register 26: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ... 394 Register 27: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ... 395 Register 28: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ... 396 Register 29: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ... 397 Register 30: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ... 398 Register 31: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ... 399 General-Purpose Input/Outputs (GPIOs) ... 400 Register 1: GPIO Data (GPIODATA), offset 0x000 ... 415 Register 2: GPIO Direction (GPIODIR), offset 0x400 ... 416 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 ... 417 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ... 418 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ... 419 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ... 420 Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ... 421

(23)

Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ... 422 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ... 424 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ... 425 Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ... 427 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ... 428 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ... 429 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ... 430 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ... 431 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ... 433 Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ... 435 Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ... 436 Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ... 438 Register 20: GPIO Commit (GPIOCR), offset 0x524 ... 439 Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ... 441 Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ... 443 Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ... 445 Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ... 446 Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ... 447 Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ... 448 Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ... 449 Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ... 450 Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ... 451 Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ... 452 Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 ... 453 Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 ... 454 Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 ... 455 Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ... 456 External Peripheral Interface (EPI) ... 457 Register 1: EPI Configuration (EPICFG), offset 0x000 ... 489 Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 ... 490 Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 ... 492 Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ... 494 Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ... 497 Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ... 501 Register 7: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 ... 506 Register 8: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ... 509 Register 9: EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ... 512 Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C ... 513 Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020 ... 515 Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030 ... 515 Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024 ... 516 Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034 ... 516 Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ... 517 Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ... 517 Register 17: EPI Status (EPISTAT), offset 0x060 ... 519 Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ... 521 Register 19: EPI Read FIFO (EPIREADFIFO), offset 0x070 ... 522 Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 ... 522

(24)

Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 ... 522 Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ... 522 Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 ... 522 Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 ... 522 Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 ... 522 Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ... 522 Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ... 523 Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ... 525 Register 29: EPI Interrupt Mask (EPIIM), offset 0x210 ... 526 Register 30: EPI Raw Interrupt Status (EPIRIS), offset 0x214 ... 527 Register 31: EPI Masked Interrupt Status (EPIMIS), offset 0x218 ... 529 Register 32: EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C ... 530 General-Purpose Timers ... 532 Register 1: GPTM Configuration (GPTMCFG), offset 0x000 ... 549 Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ... 550 Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ... 552 Register 4: GPTM Control (GPTMCTL), offset 0x00C ... 554 Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 ... 557 Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ... 559 Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ... 562 Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 ... 565 Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ... 567 Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ... 568 Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ... 569 Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ... 570 Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ... 571 Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ... 572 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ... 573 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ... 574 Register 17: GPTM Timer A (GPTMTAR), offset 0x048 ... 575 Register 18: GPTM Timer B (GPTMTBR), offset 0x04C ... 576 Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 ... 577 Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 ... 578 Watchdog Timers ... 579 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ... 583 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ... 584 Register 3: Watchdog Control (WDTCTL), offset 0x008 ... 585 Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ... 587 Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ... 588 Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ... 589 Register 7: Watchdog Test (WDTTEST), offset 0x418 ... 590 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ... 591 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ... 592 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ... 593 Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ... 594 Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ... 595 Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ... 596 Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ... 597

(25)

Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ... 598 Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ... 599 Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ... 600 Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ... 601 Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ... 602 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ... 603 Analog-to-Digital Converter (ADC) ... 604 Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ... 627 Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ... 628 Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ... 630 Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C ... 632 Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ... 635 Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ... 637 Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ... 642 Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ... 643 Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ... 645 Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ... 647 Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ... 649 Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ... 650 Register 13: ADC Control (ADCCTL), offset 0x038 ... 652 Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ... 653 Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ... 655 Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ... 658 Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ... 658 Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ... 658 Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ... 658 Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ... 659 Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ... 659 Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ... 659 Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ... 659 Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ... 661 Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 ... 663 Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ... 665 Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ... 665 Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ... 666 Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ... 666 Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ... 668 Register 31: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ... 668 Register 32: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 ... 669 Register 33: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 ... 669 Register 34: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ... 671 Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ... 672 Register 36: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ... 673 Register 37: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 ... 674 Register 38: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ... 675 Register 39: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ... 680 Register 40: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ... 680 Register 41: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ... 680

(26)

Register 42: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ... 680 Register 43: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ... 680 Register 44: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ... 680 Register 45: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ... 680 Register 46: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ... 680 Register 47: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ... 683 Register 48: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ... 683 Register 49: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ... 683 Register 50: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ... 683 Register 51: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ... 683 Register 52: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ... 683 Register 53: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ... 683 Register 54: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ... 683 Universal Asynchronous Receivers/Transmitters (UARTs) ... 685 Register 1: UART Data (UARTDR), offset 0x000 ... 700 Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ... 702 Register 3: UART Flag (UARTFR), offset 0x018 ... 705 Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ... 708 Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ... 709 Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ... 710 Register 7: UART Line Control (UARTLCRH), offset 0x02C ... 711 Register 8: UART Control (UARTCTL), offset 0x030 ... 713 Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ... 717 Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ... 719 Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ... 723 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ... 727 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ... 731 Register 14: UART DMA Control (UARTDMACTL), offset 0x048 ... 733 Register 15: UART LIN Control (UARTLCTL), offset 0x090 ... 734 Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ... 735 Register 17: UART LIN Timer (UARTLTIM), offset 0x098 ... 736 Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ... 737 Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ... 738 Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ... 739 Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ... 740 Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ... 741 Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ... 742 Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ... 743 Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ... 744 Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ... 745 Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ... 746 Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ... 747 Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ... 748 Synchronous Serial Interface (SSI) ... 749 Register 1: SSI Control 0 (SSICR0), offset 0x000 ... 764 Register 2: SSI Control 1 (SSICR1), offset 0x004 ... 766 Register 3: SSI Data (SSIDR), offset 0x008 ... 768 Register 4: SSI Status (SSISR), offset 0x00C ... 769

(27)

Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 ... 771 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ... 772 Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 ... 773 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ... 775 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ... 777 Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ... 778 Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ... 779 Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ... 780 Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ... 781 Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ... 782 Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ... 783 Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ... 784 Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ... 785 Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ... 786 Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ... 787 Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ... 788 Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ... 789 Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ... 790 Inter-Integrated Circuit (I²C) Interface ... 791 Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ... 808 Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ... 809 Register 3: I²C Master Data (I2CMDR), offset 0x008 ... 814 Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ... 815 Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ... 816 Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ... 817 Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ... 818 Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ... 819 Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ... 820 Register 10: I²C Slave Own Address (I2CSOAR), offset 0x800 ... 821 Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x804 ... 822 Register 12: I²C Slave Data (I2CSDR), offset 0x808 ... 824 Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ... 825 Register 14: I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ... 826 Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ... 827 Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ... 828 Inter-Integrated Circuit Sound (I²S) Interface ... 829 Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000 ... 842 Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ... 843 Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008 ... 844 Register 4: I²S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ... 846 Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ... 847 Register 6: I²S Transmit FIFO Level (I2STXLEV), offset 0x018 ... 848 Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800 ... 849 Register 8: I²S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ... 850 Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808 ... 851 Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ... 854

(28)

Register 11: I²S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ... 855 Register 12: I²S Receive FIFO Level (I2SRXLEV), offset 0x818 ... 856 Register 13: I²S Module Configuration (I2SCFG), offset 0xC00 ... 857 Register 14: I²S Interrupt Mask (I2SIM), offset 0xC10 ... 859 Register 15: I²S Raw Interrupt Status (I2SRIS), offset 0xC14 ... 861 Register 16: I²S Masked Interrupt Status (I2SMIS), offset 0xC18 ... 863 Register 17: I²S Interrupt Clear (I2SIC), offset 0xC1C ... 865 Controller Area Network (CAN) Module ... 866 Register 1: CAN Control (CANCTL), offset 0x000 ... 888 Register 2: CAN Status (CANSTS), offset 0x004 ... 890 Register 3: CAN Error Counter (CANERR), offset 0x008 ... 893 Register 4: CAN Bit Timing (CANBIT), offset 0x00C ... 894 Register 5: CAN Interrupt (CANINT), offset 0x010 ... 895 Register 6: CAN Test (CANTST), offset 0x014 ... 896 Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ... 898 Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ... 899 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ... 899 Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ... 900 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ... 900 Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ... 903 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ... 903 Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ... 904 Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ... 904 Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ... 906 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ... 906 Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ... 907 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ... 907 Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ... 909 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ... 909 Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ... 912 Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ... 912 Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ... 912 Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ... 912 Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ... 912 Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ... 912 Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ... 912 Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ... 912 Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ... 913 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ... 913 Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ... 914 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ... 914 Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ... 915 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ... 915 Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ... 916 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ... 916 Universal Serial Bus (USB) Controller ... 917 Register 1: USB Device Functional Address (USBFADDR), offset 0x000 ... 945 Register 2: USB Power (USBPOWER), offset 0x001 ... 946