I486-2

inter

i486™ MICROPROCESSOR

• Binary Compatible with Large Software Base

-MS-DOS*, OS/2**, Windows -UNIX*** System V/386 -iRMX®, iRMKTM Kernels

• High Integration Enables On-Chip - 8 Kbyte Code and Data Cache - Floating Point Unit

- Paged, Virtual Memory Management

• Easy To Use - Built-In Self Test

- Hardware Debugging Support -Intel Software Support

- Extensive Third Party Software Support

• High Performance Design

- Frequent Instructions Execute in One Clock

- 25 MHz and 33 MHz Clock Frequencies

-106 MbytelSec Burst Bus - CHMOS IV Process Technology

• Complete 32-Bit Architecture - Address and Data Busses -Registers

• Multiprocessor Support - Multiprocessor Instructions - Cache Consistency Protocols - Support for Second Level Cache

The i486™ CPU offers the highest performance for DOS, OS/2, Windows and UNIX System V /386 applica- tions. It is 100% binary compatible with the 386TM CPU. One million transistors integrate cache memory, floating point hardware and memory management on-chip while retaining binary compatibility with previous members of the 86 architectural family. Frequently used instructions execute in one cycle resulting in RISC performance levels. An 8 Kbyte unified code and data cache combined with a 106 Mbyte/Sec burst bus at 33.3 MHz ensure high system throughput even with inexpensive DRAMs.

New features enhance multiprocessing systems. New instructions speed manipulation of memory based sem- aphores. On-chip hardware ensures cache consistency and provides hooks for multilevel caches.

The built in self test extensively tests on-chip logic, cache memory and the on-chip paging translation cache.

Debug features include breakpoint traps on code execution and data accesses.

i486™ Microprocessor Pipelined 32-Bit Microarchitecture

6491tlt ItT f B

~)

^{n erun ron, er "'}

32-blt Data Bus

II oj 32

32-blt Data Bus

J l j l

1i II ¹ⁱ h

Linear Address Bus ³²

J). ³²

Segmentation Paging peo, PWT

Barrel Shifter Base/ U," U," 2 Cache Unit

Index

~

Oescrlptor

R.91~.r File Registers 20 Bk ayte

32 Ph)'$lcol cache

LImIt and Translation Address

ALU Attribute Lookoslde

PLA Buffer

F

Dis lacement Bus ^128R Pref.tcher

mlcro-Instructron 32

...

^Code 32 Byte Code

Stream Queue

==:

^floating Control cnd

,,,,,,,\10'

r

Point Protection Test 2. 2 x 16 Bytes

~ F P RegIster ^U,. Control ^Unit

~

Instruction ^Decode

File RO" Poth

iRMX, iRMK, 386, 387, 486, i486 are trademarks of Intel Corporation .

• MS-DOS® is a registered trademark of Microsoft Corporation.

"OS/2TM is a trademark of Microsoft Corporation.

*"UNIXTM is a trademark of AT&T.

Bus Interface

~

Address Drivers

Writ. Buffers

~ ---

^{.4 x 80}

Data Bus

:r

Tran,cel ... ers Bus Control Request Sequencer

- - - --

Burst Bus Control

---

Bus Size Control

- - - --

Coche Control

- - --- - - --

Parity Generation and Control

A,2-A,31 BEO#-

-

00-[)31

~. ~6~ ^#L

~I BRDY# BLAST#

-

BS16# BS8#

7.r

AHOtO.

~

^{DPO- P}

240440-1

Intel Corporation assumes no responsibility for the use of any CirCUitry other than Circuitry embodied In an Intel product. No other circuit patent licenses are Implied. Information contained herein supersedes previously published speCifications on these devices from Intel. April 1989

CONTENTS ^PAGE

1.0 TABLE OF CONTENTS. . . .. 2

Pinout... 9

Brief Pin Descriptions .. . . 13

2.0 ARCHITECTURAL OVERVIEW... ... ... ... 18

2.1 Register Set . . .

18

2.1.1 Base Architecture Registers. . . .. 19

2.1.1.1 General Purpose Registers. . . 19

2.1.1.2 Instruction Pointer. . . 19

2.1.1.3 Flags Register ... . . . 19

2.1.1.4 Segment Registers. . . .. 22

2.1.1.5 Segment Descriptor Cache Registers. . . .. 22

2.1.2 System Level Registers . . . ..

23

2.1 .2.1 Control Registers ... . . . ..

23

Control Register

O. . . .. 23

Control Register 2. . . .. 25

Control Register 3 . . . .. 26

2.1.2.2 System Address Registers ... 26

GDTR and IDTR ... 26

LDTR and TR . . . .. 26

2.1.3 Floating Point Registers. . . .. 26

2.1.3.1 Data Registers. . . .. 27

2.1.3.2 Tag Word ... 27

2.1.3.3 Status Word ... 27

2.1.3.4 Instruction and Data Pointers. . . .. 31

2.1.3.5 FPU Control Word ... 33

2.1.4 Debug and Test Registers. . . .. . . .. . . .. . . .. 34

2.1.4.1 Debug Registers. . . .. 34

2.1.4.2 Test Registers. . . .. .. . .. . . ... . . .. . .. . . .. 34

2.1.5 Register Accessibility ... 34

2.1.6 Compatibility... . . . .. 35

2.2 Instruction Set. . . .. 36

2.3 Memory Organization ... 36

2.3.1 Address Spaces ... 36

2.3.2 Segment Register Usage. . . .. 37

2.4 I/O Space. . . .. 37

2.5 Addressing Modes. . . .. 38

2.5.1 Addressing Modes Overview. . . .. 38

2.5.2 Register and Immediate Modes ... 38

2.5.3 32-Bit Memory Addressing Modes. . . .. 38

2.5.4 Differences between 16- and 32-Bit Addresses . . . 40

CONTENTS (Continued) PAGE

2.6

Data Formats ...

40

2.6.1

Data Types.. .. . .. .. .. . . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. . . .. .. . .. . . . .. . .. . . . .. .. ..

40

2.6.1.1

Unsigned Data Types.. .. .. . .. . . .. .. .. .. . .. .. . .. .. . .. .. . . .. . .. . . . .. .. ..

40

2.6.1.2

Signed Data Types. . . ..

41

2.6.1.3

Floating Point Data Types ...

41

2.6.1.4

BCD Data Types ...

41

2.6.1.5

String Data Types ...

41

2.6.1.6

ASCII Data Types ...

41

2.6.1.7

Pointer Data Types.. .. . .. .. .. . .. .. .. . .. . .. .. .. .. . .. . .. .. . .. . . .. . .. .... 43

2.6.2

Little Endian vs. Big Endian Data Formats. . . ..

44

2.7

Interrupts...

44

2.7.1

Interrupts and Exceptions ...

44

2.7.2

Interrupt Processing ... , .... ... ... ... .. . .. .. ... . .... ... ... ... .. ...

44

2.7.3

Maskable Interrupt. ... . ... ... .. .. . .. .... ... . .. .. .. .. .. ... ... ... .. . .. . .. 45

2.7.4

Non-Maskable Interrupt... 46

2.7.5

Software Interrupts... .. .. .... ... .. .. ... ... ... .. . ... ... .. 46

2.7.6

Interrupt and Exception Priorities... . .. ... .. .... .. ... ... ... .. .. 46

2.7.7

Instruction Restart ... 47

2.7.8

Double Fault... ... ... ... ... ... . ... ... .. .. 47

2.7.9

Floating Point Interrupt Vectors... . .. ... .. .... ... ... ... .. 47

3.0 REAL MODE ARCHITECTURE. . . ..

48

3.1

Real Mode Introduction .... . . .. 48

3.2

Memory Addressing. . . .. 49

3.3

Reserved Locations. . . .. 49

3.4

Interrupts... 49

3.5

Shutdown and Halt. . . .. 49

4.0 PROTECTED MODE ARCHITECTURE ...

50

4.1

Introduction... 50

4.2

Addressing Mechanism ... . . . .. 50

4.3

Segmentation... . . . .. 51

4.3.1

Segmentation Introduction... ... ... 51

4.3.2

Terminology... . .. . . . .. . . . .. . . .. . . .. .. . . .... . . .. . .. 51

4.3.3

Descriptor Tables... ... 52

4.3.3.1

Descriptor Table Introduction... ... 52

4.3.3.2

Global Descriptor Table. . . .. 52

4.3.3.3

Local Descriptor Table. . . .. 52

4.3.3.4

Interrupt Descriptor Table. . . .. 53

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i486™ MICROPROCESSOR

CONTENTS

(Continued)

PAGE

4.3.4 Descriptors... 53

4.3.4.1 Descriptor Attribute Bits. . . .. 53

4.3.4.2 486 CPU Code, Data Descriptors (S = 1) . . . .. 53

4.3.4.3 System Descriptor Formats ... . . . .. 56

4.3.4.4 LDT Descriptors (S = 0, TYPE = 2). . . 56

4.3.4.5 TSS Descriptors (S = 0, TYPE = 1 ,3,9,B) . . . .. . . .. . . .. 56

4.3.4.6 Gate Descriptors (S=O, TYPE=4-7,C,F)... 56

4.3.4.7 Differences between 486 CPU and 80286 Descriptors. . . .. 57

4.3.4.8 Selector Fields ... 58

4.3.4.9 Segment Descriptor Cache ... 58

4.3.4.10 Segment Descriptor Register Settings. . . .. 59

4.4 Protection... . . .. 62

4.4.1 Protection Concepts. . . .. 62

4.4.2 Rules of Privilege. . . .. 63

4.4.3 Privilege Levels ... 63

4.4.3.1 Task Privilege. . . .. 63

4.4.3.2 Selector Privilege (RPL) ... 63

4.4.3.3 I/O Privilege Level and I/O Permission Bitmap... 63

4.4.3.4 Privilege Validation. . . .. 64

4.4.3.5 Descriptor Access. . . .. 64

4.4.4 Privilege Level Transfers ... 64

4.4.5 Call Gates. . . .. 67

4.4.6 Task Switching. . . .. . . .. . . .. 67

4.4.7 Initialization and Transition to Protected Mode... .... .. .. ... 68

4.4.8 Tools for Building Protected Systems... ... ... ... 69

4.5 Paging .. . . .. . . .. 69

4.5.1 Paging Concepts. . . .. 69

4.5.2 Paging Organization. . . .. 70

4.5.2.1 Page Mechanism. . . .. 70

4.5.2.2 Page Descriptor Base Register ... 70

4.5.2.3 Page Directory ... 70

4.5.2.4 Page Tables... 71

4.5.2.5 Page Directory/Table Entries... ... ... ... 71

4.5.3 Page Level Protection (R/W, U/S Bits). . . .. 71

4.5.4 Page Cacheability (PWT, PCD Bits) ... . . . .. 72

4.5.5 Translation Lookaside Buffer ... . . . .. 72

4.5.6 Paging Operation. . . .. 73

4.5.7 Operating System Responsibilities... 74

CONTENTS (Continued) PAGE

4.6 Virtual 8086 Environment. . . .. 74

4.6.1 Executing 8086 Programs... 74

4.6.2 Virtual 8086 Addressing Mechanism. . . 74

4.6.3 Paging in Virtual Mode. . . .. 74

4.6.4 Protection and Virtual 8086 Mode to I/O Permission Bitmap. . . .. 75

4.6.5 Interrupt Handling. . . .. 76

4.6.6 Entering and leaving Virtual 8086 Mode ... . . 77

4.6.6.1 Task Switches to/from Virtual 8086 Mode. . . .. 77

4.6.6.2 Transitions through Trap and Interrupt Gates, and IRET ... . . . .. 77

5.0 ON-CHIP CACHE. . . .. 79

5.1 Cache Organization . . . .. 79

5.2 Cache Control ... . . . 80

5.3 Cache Line Fills. . . .. 80

5.4 Cache Line Invalidations. . . ..

81

5.5 Cache Replacement. . .

81

5.6 Page Cacheability . . . .. 82

5.7 Cache Flushing . . . .. 83

5.8 Caching Translation lookaside Buffer Entries... 83

6.0 HARDWARE INTERFACE. .. . .. . . .. . . . .. .. . . ... . . .. . . .. . . .. . . . .. .. . . .. .. 84

6.1 Introduction... 84

6.2 Signal Descriptions ... 85

6.2.1 Clock (ClK) . . . .. 85

6.2.2 Address Bus (A31-A2, BEO#-BE3#) ... 85

6.2.3 Data Lines (D31-DO) ... 86

6.2.4 Parity... 86

Data Parity Input/Outputs (DPO-DP3) . . ... . . .. . . .. . .. .. . . .. .. 86

Parity Status Output (PCHK#)... .. ... 86

6.2.5 Bus Cycle Definition. . . .. 86

M/IO#, D/C#, W/R# Outputs ... 86

Bus lock Output (lOCK #) . . . .. 86

Pseudo-lock Output (PLOCK #) . . . .. 87

6.2.6 Bus Control. . . .. 87

Address Status Output(ADS#) ... 87

Non-Burst Ready Input (RDY#) ... 87

6.2.7 Burst Control... 87

Burst Ready Input (BRDY#)... 87

Burst last Output (BLAST#) ... 87

6.2.8 Interrupt Signals ... 88

Reset Input (RESET) . . . ..

88

Maskable Interrupt Request Input (INTR) . . . .. 88

Non-Maskable Interrupt Request Input (NMI) ... 88

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i486™ MICROPROCESSOR

CONTENTS (Continued) PAGE

6.2.9 Bus Arbitration Signals. . . .. 88

Bus Request Output (BREQ) . . . .. 88

Bus Hold Request Input (HOLD) ... 88

Bus Hold Acknowledge Output (HLDA)... 89

Backoff Input (BOFF#) ... 89

6.2.10 Cache Invalidation. . . .. 89

Address Hold Request Input (AHOLD) ... 89

External Address Valid Input (EADS#) ... ... 89

6.2.11 Cache Control. . . .. 89

Cache Enable Input (KEN#)... 89

Cache Flush Input (FLUSH#)...

90

6.2.12 Page Cacheability Outputs (PWT, PC D) ... . . . ..

90

6.2.13 Numeric Error Reporting. . . ..

90

Floating Point Error Output (FERR #) ...

90

Ignore Numeric Error Input (IGNNE #) . . . ..

90

6.2.14 Bus Size Control (BS 16 #, BS8 #) . . . ..

90

6.2.15 Address Bit 20 Mask (A20M #) . . . ..

90

6.3 Write Buffers. . . .. 91

6.3.1 Write Buffers and I/O Cycles.. . . .. . . .. 91

6.3.2 Write Buffers Implications on Locked Bus Cycles. . . .. 91

6.4 Interrupt and Non-Maskable Interrupt Interface. . . .. . . ..

92

6.4.1 Interrupt Logic. . .

92

6.4.2 NMI Logic...

92

6.5 Reset and Initialization ...

92

6.5.1 Pin State During Reset ... 93

7.0 BUS OPERATION... 94

7.1 Data Transfer Mechanism. . . ..

94

7.1.1 Memory and I/O Spaces. . . .. . . .. .. . . ..

94

7.1.2 Memory and I/O Space Organization.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 95

7.1.3 Dynamic Data Bus Sizing. . . .. .. . . .. . . .. . . .. . . . .. 96

7.1.4 Interfacing with 8-, 16- and 32-bit Memories ... 97

7.1.5 Dynamic Bus Sizing During Cache Line Fills ... 99

7.1.6 Operand Alignment ...

99

7.2 Bus Functional Description.. .. ... ... ... ... . ... .... ... ..

100

7.2.1 Non-Cacheable Non-Burst Single Cycle...

100

7.2.1.1 NoWaitStates ...

100

7.2.1.2 Inserting Wait States... .... .. ... . .... ... ...

101

7.2.2 Multiple and Burst Cycle Bus Transfers ... , ... .. . ... 101

7.2.2.1 Burst Cycles.. .. .. . .. .. .. .. .. .. .. . .. .. .. .. .. .. . .. .. . .. .. .. . .. .. .. .. ..

101

7.2.2.2 Terminating Multiple and Burst Cycle Transfers... . .. .. ... ... ..

103

7.2.2.3 Non-Cacheable Non-Burst Multiple Cycle Transfers. . .. ... ... ..

103

7.2.2.4 Non-Cacheable Burst Cycles... .... ... ... ....

103

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i486™ MICROPROCESSOR

CONTENTS (Continued) PAGE

7.2.3 Cacheable Cycles... ... ... 105

7.2.3.1 Byte Enables During a Cache Line Fill . . . 105

7.2.3.2 Non-Burst Cacheable Cycles. . . 105

7.2.3.3 Burst Cacheable Cycles... ... 106

7.2.3.4 Effect of Changing KEN# During a Cache Line Fill... 107

7.2.4 Burst Mode Details... ... 108

7.2.4.1 Adding Wait State to Burst Cycles. . . 108

7.2.4.2 Burst and Cache Line Fill Order... 109

7.2.4.3 Interrupted Burst Cycles ... 110

7.2.5 8- and 16-Bit Cycles ... . . . 112

7.2.6 Locked Cycles... 114

7.2.7 Pseudo-Locked Cycles... 115

7.2.8 Invalidate Cycles... ... .... ... 116

7.2.8.1 Rate of Invalidate Cycles... ... ... ... 118

7.2.8.2 Running Invalidate Cycles Concurrently With Line Fills. . . 118

7.2.9 Bus Hold.. . . .. . . .. . . .. . . .. . . .. . . 119

7.2.10 Interrupt Acknowledge... 120

7.2.11 Special Bus Cycles. . . .. 121

7.2.12 Bus Cycle Restart... 121

7.2.13 Bus States . . . .. 123

7.2.14 Floating Point Error Handling ... 124

8.0 TESTABILITy... 125

8.1 Built-In SelfTest(BIST) ... 125

8.2 On-Chip Cache Testing... 126

8.2.1 Cache Organization. . . 126

8.2.2 Cache Testing Registers: TR3, TR4, TR5... 127

Cache Data Test Register: TR3 ... 128

Cache Status Test Register: TR4... ... ... ... ... 128

Cache Control Test Register: TR5.. .. ... ... ... ... ... 128

8.2.3 Cache Testability Write... 128

8.2.4 Cache Testability Read... 130

8.2.5 Flush Cache. . . 130

8.3 Translation Lookaside Buffer (TLB) Testing.... ... ... ... 130

8.3.1 Translation Lookaside Buffer Organization. . . 130

8.3.2 TLB Test Registers: TR6 and TR7 ... ... ... ... 131

Command Test Register: TR6... 132

Data Test Register: TR7 ... 132

8.3.3 TLB Write Test... .. ... ... ... ... ... 133

8.3.4 TLB Lookup Test... 133

8.4 Tristate OutputTest Mode... 133

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i486™ MICROPROCESSOR

CONTENTS (Continued) PAGE

9.0 DEBUGGING SUPPORT... 134

9.1 Breakpoint Instructions ...

134

9.2 Single Step Instructions.... ... .... ... ... ... ..

134

9.3 Debug Registers. . .

134

9.3.1 Linear Address Breakpoint Registers. . . ..

134

9.3.2 Debug Control Register. . . ..

134

9.3.3 Debug Status Register. . . ..

137

9.3.4 Use of Resume Flag (RF) in Flag Register. . .

137

10.0 INSTRUCTION SET SUMMARy... 137

10.1 486™ Microprocessor Instruction Encoding and Clock Count Summary ...

138

10.2 Instruction Encoding ...

156

10.2.1 Overview ...

156

10.2.2 32-Bit Extensions of the Instruction Set. . .

157

10.2.3 Encoding of Integer Instruction Fields. . .

158

10.2.3.1 Encoding of Operand Length (w) Field ...

158

10.2.3.2 Encoding of the General Register (reg) Field ...

158

10.2.3.3 Encoding of the Segment Register (sreg) Field...

159

10.2.3.4 Encoding of Address Mode. . . ..

159

10.2.3.5 Encoding of Operation Direction (d) Field ...

163

10.2.3.6 Encoding of Sign-Extend (s) Field...

163

10.2.3.7 Encoding of Conditional Test (tUn) Field. . .

163

10.2.3.8 Encoding of Control or Debug or Test Register (eee) Field. . . ..

163

10.2.4 Encoding of Floating Point Instruction Fields. . .

164

11.0 DIFFERENCES WITH THE 386™ MiCROPROCESSOR... 164

12.0 ELECTRICAL DATA... 165

12.1 Power and Grounding ...

165

12.2 Maximum Ratings . . . ..

165

12.3 D.C. Specifications...

166

12.4 A.C. Specifications. . . ..

166

12.5 Designing for ICD-486 . . .

170

13.0 MECHANICAL DATA... 173

13.1 Package Thermal Specifications. . . ..

174

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i486™ MICROPROCESSOR

S ^1.27 ₀ ^1.26 ₀ ^1.23 ₀ ^NC ₀ ^1.14 ₀ ^VSS ₀ ^1.12 ₀ ^VSS ₀ ^VSS ₀ ^VSS ₀ ^VSS ₀ ^VSS ₀ ^1.10 ₀ ^VSS ₀ ^1.6 ₀ ^1.4 ₀ ^AOS# ₀ R ^1.28 ₀ ^1.25 ₀ ^VCC ₀ ^VSS ₀ ^1.18 ₀ ^VCC ₀ ^1.15 ₀ ^VCC ₀ ^VCC ₀ ^VCC ₀ ^VCC ₀ ^All ₀ ^1.8 ₀ ^vee ₀ ^1.3 ₀ ^BLASTH ₀ ^NC ₀ Q ^{1.31 VSS 1.17 1.19 1.21 1.24 1.22 1.20 1.16 1.13 1.9 1.5 1.7 1.2} BREQ PlOCK# PCHK#

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

p ^{00 1.29 1.30 HlOA VCC VSS}

0 0 0 0 0 0

N

^{02 01 OPO} lOCK# M/lO# w IR#

0 0 0 0 0 0

M ^vss ₀ ^VCC _{0 0} ^{04 o/c#} ₀ ^vee ₀ ^vss ₀

L ^VSS _{0 0} ⁰⁶ ₀ ^{07 PWT} ₀ ^VCC ₀ ^VSS ₀

K

^{vss VCC 014} 4861M Microprocessor BEO# vee VSS

0 0 0 PIN SlOE VIEW 0 0 0

J ^VCC _{0 0} ^{05 016} ₀ ^BE2# ₀ ^BE1# ₀ ^PCO ₀

H

^VSS ₀ ⁰³ ₀ ^OP2 ₀ ^BROY# ₀ ^VCC ₀ ^VSS ₀

G ^VSS ₀ ^VCC ₀ ⁰¹² _{0 0} ^{NC VCC} ₀ ^VSS ₀

F ^{OPl 08 015} KEN# ROY# BE3#

0 0 0 0 0 0

E

^VSS ₀ ^VCC ₀ ⁰¹⁰ ₀ ^HOlO ₀ ^vee ₀ ^VSS ₀

D

^{D9 013 017} AlOM# BS8# BOff#

0 0 0 0 0 0

C ^{011 018 ClK VCC VCC 027 026 028 030 NC NC NC NC} fERR# flUSH# RESET BS16#

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

B ⁰¹⁹ ₀ ⁰²¹ ₀ ^VSS ₀ ^VSS ₀ ^VSS ₀ ⁰²⁵ ₀ ^vcc ₀ ⁰³¹ ₀ ^vee _{0 0} ^{NC vcc} _{0 0} ^NC ₀ ^{NC NC} ₀ ^NMI ₀ ^NC ₀ ^[AOS# ₀ A ^{020 022 NC 023 OP3 024 VSS 029 VSS NC VSS NC NC NC} IGNNE# INTR AHOlO

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2 3 4 5 6 7

8 9

10 11 12 13 14 15 16 17

240440-2 Figure 1.1

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i486™ MICROPROCESSOR

Pin Cross Reference by Pin Name Pin Location

Name

Pin Location Name

Pin Location Name

Pin Location Name

A2 014 B516# C17 HLOA P15

Vss

^B4

A3 R15 CLK C3 HOLO E15

Vss

^B5

A4 516 00 P1 IGNNE# A15

Vss

^E1

A5 012 01 N2 INTR A16

Vss

^E17

A6 515 02 N1 KEN# F15

Vss

^G1

A7 013 03 H2 LOCK# N15

Vss

^G17

A8 R13 04 M3 M/IO# N16

Vss

^H1

A9 011 05 J2 NMI B15

Vss

^H17

A10 513 06 L2 PCO J17

Vss

^K1

A11 R12 07 L3 PCHK# 017

Vss

^K17

A12 57 08 F2 PWT L15

Vss

^L1

A13 010 09 01 PLOCK# 016

Vss

^M1

A14 55 010 E3 ROY# F16

Vss

^M17

A15 R7 011 C1 RE5ET C16

Vss

^P17

A16 09 012 G3

Vee

^B7

Vss

⁰²

A17 03 013 02

Vee

^B9

Vss

^R4

A18 R5 014 K3

Vee

^B11

Vss

⁵⁶

A19 04 015 F3

Vee

^C4

Vss

⁵⁸

A20 08 016 J3

Vee

^C5

Vss

⁵⁹

A21 05 017 03

Vee

^E2

Vss

⁵¹⁰

A22 07 018 C2

Vee

^E16

Vss

⁵¹¹

A23 53 019 B1

Vee

^G2

Vss

⁵¹²

A24 06 020 A1

Vee

^G16

Vss

⁵¹⁴

A25 R2 021 B2

Vee

^{H16 W/R# N17}

A26 52 022 A2

Vee

^J1

A27 51 023 A4

Vee

^{K2 NC A3}

A28 R1 024 A6

Vee

^{K16 NC A10}

A29 P2 025 B6

Vee

^{L16 NC A12}

A30 P3 026 C7

Vee

^{M2 NC A13}

A31 01 027 C6

Vee

^{M16 NC A14}

A20M# 015 028 C8

Vee

^{P16 NC B10}

A05# 517 029 A8

Vee

^{R3 NC B12}

AHOLO A17 030 C9

Vee

^{R6 NC B13}

BEO# K15 031 B8

Vee

^{R8 NC B14}

BE1# J16 O/C# M15

Vee

^{R9 NC B16}

BE2# J15 OPO N3

Vee

^{R10 NC C10}

BE3# F17 OP1 F1

Vee

^{R11 NC C11}

BLA5T# R16 OP2 H3

Vee

^{R14 NC C12}

BOFF# 017 OP3 A5

Vss

^{A7 NC C13}

BROY# H15 EA05# B17

Vss

^{A9 NC G15}

BREO 015 FERR# C14

Vss

^{A11 NC R17}

B58# 016 FLU5H# C15

Vss

^{B3 NC 54}

NOTE:

Pins Identified as

Ne

should remain completely unconnected.

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i486™ MICROPROCESSOR

Pin Cross Reference By location location Pin

Name location Pin

Name location Pin

Name location Pin Name

A1 020 C9 030 J15 BEU 010 A13

A2 022 C10 NC J16 BE1# 011 A9

A3 NC C11 NC J17 PCO 012 A5

A4 023 C12 NC K1

Vss

^{013 A7}

A5 OP3 C13 NC K2

Vee

^{014 A2}

A6 024 C14 FERR# K3 014 015 BREO

A7

Vss

C15 FLU5H# K15 BEO# 016 PLOCK#

A8 029 C16 RE5ET K16

Vee

^{017 PCHK#}

A9

Vss

^{C17 B516# K17}

Vss

^{R1 A28}

A10 NC 01 09 L1

Vss

R2 A25

A11

Vss

^{02 013 L2 06 R3}

Vee

A12 NC 03 017 L3 07 R4

Vss

A13 NC 015 A20M# L15 PWT R5 A18

A14 NC 016 B58# L16

Vee

^R6

Vee

A15 IGNNE# 017 BOFF# L17

Vss

^{R7 A15}

A16 INTR E1

Vss

^M1

Vss

^R8

Vee

A17 AHOlO E2

Vee

^M2

Vee

^R9

Vee

B1 019 E3 010 M3 04 R10

Vee

B2 021 E15 HOLO M15 O/C# R11

Vee

B3

Vss

E16

Vee

M16

Vee

^{R12 A11}

B4

Vss

^E17

Vss

^M17

Vss

^{R13 A8}

B5

Vss

^{F1 OP1 N1 02 R14}

Vee

B6 025 F2 08 N2 01 R15 A3

B7

Vee

^{F3 015 N3 OPO R16 BLA5T#}

B8 031 F15 KEN# N15 LOCK# R17 NC

B9

Vee

^{F16 ROY# N16 M/IO# 51} A27

B10 NC F17 BE3# N17 W/R# 52 A26

B11

Vee

^G1

Vss

^{P1 00 53 A23}

B12 NC G2

Vee

^{P2 A29 54 NC}

B13 NC G3 012 P3 A30 55 A14

B14 NC G15 NC P15 HLOA 56

Vss

B15 NMI G16

Vee

^P16

Vee

^{57 A12}

B16 NC G17

Vss

^P17

Vss

⁵⁸

Vss

B17 EA05# H1

Vss

^{01 A31 59}

Vss

C1 011 H2 03 02

Vss

⁵¹⁰

Vss

C2 018 H3 OP2 03 A17 511

Vss

C3 ClK H15 BROY# 04 A19 512

Vss

C4

Vee

^H16

Vee

05 A21 513 A10

C5

Vee

^H17

Vss

06 A24 514

Vss

C6 027 J1

Vee

^{Q7 A22 515} A6

C7 026 J2 05 08 A20 516 A4

C8 028 J3 016 09 A16 517 AD5#

NOTE:

All pins identified as Ne should remain completely unconnected.

12

intJ

i486™ MICROPROCESSOR

QUICK PIN REFERENCE

What follows is a brief pin description. For detailed signal descriptions refer to Section 6.

Symbol Type Name and Function

ClK I Clock provides the fundamental timing and the internal operating frequency for the 486 microprocessor. All external timing parameters are specified with respect to the rising edge ofClK.

ADDRESS BUS

A31-A4 I/O A31-A2 are the address lines of the microprocessor. A31-A2 together with the byte A2-A3 0 enables, BEO#-BE3#, define the physical area of memory or input/output space

accessed. Address lines A31-A4 are used to drive addresses into the microprocessor to perform cache line invalidations. Input signals must meet setup and hold times t22 and t23. A31-A2 are active HIGH and are not driven during bus or address hold.

BE3# 0 The byte enable signals indicate active bytes during read and write cycles. Ouring the BE2# 0 first cycle of a cache fill, the external system should assume that all byte enables are BE1# 0 active. BE3# applies to 024-031, BE2# applies to 016-023, BE1 # applies to 08- BEO# 0 015 and BEO# applies to 00-07. BEO#-BE3# are active lOW and are not driven

during bus hold.

DATA BUS

031-00 I/O These are the data lines for the 486 microprocessor. Lines 00-07 define the least significant byte of the data bus while lines 024-031 define the most significant byte of the data bus. These signals must meet setup and hold times t22 and t23 for proper operation on reads. These pins are active HIGH and are driven during the second and subsequent clocks of write cycles.

DATA PARITY

OPO-OP3 I/O There is one data parity pin for each byte of the data bus. Oata parity is generated on all write data cycles with the same timing as the data driven by the 486 microprocessor.

Even parity information must be driven back into the microprocessor on the data parity pins with the same timing as read information to insure that the correct parity check status is indicated by the 486 microprocessor. The signals read on these pins do not affect program execution.

Input signals must meet setup and hold times t22 and t23. OPO-OP3 should be

connected to Vee through a pullup resistor in systems which do not use parity. OPO-OP3 are active HIGH and are driven during the second and subsequent clocks of write cycles.

PCHK# 0 Parity Status is driven on the PCH K # pin the clock after ready for read operations. The parity status is for data sampled at the end of the previous clock. A parity error is indicated by PCHK# being lOW. Parity status is only checked for enabled bytes as indicated by the byte enable and bus size signals. PCHK # is valid only in the clock immediately after read data is returned to the microprocessor. At all other times PCHK # is inactive (HIGH). PCHK# is never floated.

BUS CYCLE DEFINITION

MIIO# 0 The memory/input-output, data/control and write/read lines are the primary bus O/C# 0 definition signals. These signals are driven valid as the AOS# signal is asserted.

W/R# 0 MIIO# D/C# W/R# Bus Cycle Initiated

0 0 0 Interrupt Acknowledge

0 0 1 Halt/Special Cycle

0 1 0 I/O Read

0 1 1 I/O Write

1 0 0 Code Read

1 0 1 Reserved

1 1 0 Memory Read

1 1 1 Memory Write

The bus definition signals are not driven during bus hold and follow the timing of the address bus. Refer to Section 7.2.11 for a description of the special bus cycles.

inter

i486™ MICROPROCESSOR

QUICK PIN REFERENCE

(Continued)

Symbol Type Name and Function

BUS CYCLE DEFINITION (Continued)

LOCK#

a

The bus lock pin indicates that the current bus cycle is locked. The 486 microprocessor will not allow a bus hold when LOCK # is asserted (but address holds are allowed).

LOCK # goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when ready is returned. LOCK # is active LOW and is not driven during bus hold. Locked read cycles will not be transformed into cache fill cycles if KEN is returned active.

PLOCK#

a

The pseudo-lock pin indicates that the current bus transaction requires more than one bus cycle to complete. Examples of such operations are floating point long reads and writes (64 bits), segment table descriptor reads (64 bits), in addition to cache line fills (128 bits). The 486 microprocessor will drive PLOCK # active until the addresses for the last bus cycle of the transaction have been driven regardless of whether RDY # or BRDY # have been returned.

Normally PLOCK # and BLAST # are inverse of each other. However during the first bus cycle of a 64-bit floating point write, both PLOCK # and BLAST # will be asserted.

PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock ready is returned. PLOCK# is active LOW and is not driven during bus hold.

BUS CONTROL

ADS#

a

The address status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock as the addresses are driven. ADS# is active LOW and is not driven during bus hold.

RDY# I The non-burst ready input indicates that the current bus cycle is complete. RDY # indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted data from the 486 microprocessor in response to a write. RDY # is ignored when the bus is idle and at the end of the first clock of the bus cycle.

RDY # is active during address hold. Data can be returned to the processor while AHOLD is active.

RDY# is active LOW, and is not provided with an internal pullup resistor. RDY# must satisfy setup and hold times t16 and t17 for proper chip operation.

BURST CONTROL

BRDY# I The burst ready input performs the same function during a burst cycle that RDY # performs during a non-burst cycle. BRDY # indicates that the external system has presented valid data in response to a read or that the external system has accepted data in response to a write. BRDY # is ignored when the bus is idle and at the end of the first clock in a bus cycle.

BRDY # is sampled in the second and subsequent clocks of a burst cycle. The data presented on the data bus will be strobed into the microprocessor when BRDY # is sampled active. If RDY # is returned simultaneously with BRDY #, BRDY # is ignored and the burst cycle is prematurely aborted.

BRDY # is active LOW and is provided with a small pullup resistor. BRDY # must satisfy the setup and hold times t16 and t17.

BLAST #

a

The burst last signal indicates that the next time BRDY # is returned the burst bus cycle is complete. BLAST # is active for both burst and non-burst bus cycles. BLAST # is active LOW and is not driven during bus hold.

QUICK PIN REFERENCE

(Continued)

Symbol Type Name and Function

INTERRUPTS

RESET I The reset input forces the 486 microprocessor to begin execution at a known state. The microprocessor cannot begin execution of instructions until at least 1 ms after Vee and CLK have reached their proper DC and AC specifications. The RESET pin should remain active during this time to insure proper microprocessor operation. RESET is active HIGH.

RESET is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock.

INTR I The maskable interrupt indicates that an external interrupt has been generated. If the internal interrupt flag is set in EFLAGS, active interrupt processing will be initiated. The 486 microprocessor will generate two locked interrupt acknowledge bus cycles in response to the INTR pin going active. INTR must remain active until the interrupt acknowledges have been performed to assure that the interrupt is recognized.

INTR is active HIGH and is not provided with an internal pulldown resistor. INTR is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock.

NMI I The non-maskable interrupt request signal indicates that an external non-maskable interrupt has been generated. NMI is rising edge sensitive. NMI must be held LOW for at least four CLK periods before this rising edge. NMI is not provided with an internal pulldown resistor. NMI is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock.

BUS ARBITRATION

BREa

a

The internal cycle pending signal indicates that the 486 microprocessor has internally generated a bus request. BREa is generated whether or not the 486 microprocessor is driving the bus. BREa is active HIGH and is never floated.

HOLD I The bus hold request allows another bus master complete control of the 486

microprocessor bus. In response to HOLD going active the 486 microprocessor will float most of its output and input/output pins. HLDA will be asserted after completing the current bus cycle, burst cycle or sequence of locked cycles. The 486 microprocessor will remain in this state until HOLD is deasserted. HOLD is active high and is not provided with an internal pulldown resistor. HOLD must satisfy setup and hold times t18 and t19 for proper operation.

HLDA

a

Hold acknowledge goes active in response to a hold request presented on the HOLD pin.

HLDA indicates that the 486 microprocessor has given the bus to another local bus master. HLDA is driven active in the same clock that the 486 microprocessor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active HIGH and remains driven during bus hold.

BOFF# I The backoffinput forces the 486 microprocessor to float its bus in the next clock. The microprocessor will float all pins normally floated during bus hold but HLDA will not be asserted in response to BOFF # . BOFF # has higher priority than ROY # or BRDY #; if both are returned in the same clock, BOFF # takes effect. The microprocessor remains in bus hold until BOFF # is negated. If a bus cycle was in progress when BOFF # was asserted the cycle will be restarted. BOFF # is active LOW and must meet setup and hold times t18 and t19 for proper operation.

CACHE INVALIDATION

AHOLD I The address hold request allows another bus master access to the 486 microprocessor's address bus for a cache invalidation cycle. The 486 microprocessor will stop driving its address bus in the clock following AHOLD going active. Only the address bus will be floated during address hold, the remainder of the bus will remain active. AHOLD is active HIGH and is provided with a small internal pulldown resistor. For proper operation AHOLD must meet setup and hold times t18 and t19.

inter

i486™ MICROPROCESSOR

QUICK PIN REFERENCE

(Continued)

Symbol Type Name and Function

CACHE INVALIDATION (Continued)

EADS I This signal indicates that a valid external address has been driven onto the 486 microprocessor address pins. This address will be used to perform an internal cache invalidation cycle. EADS# is active LOW and is provided with an internal pullup resistor.

EADS# must satisfy setup and hold times t12 and t13 for proper operation.

CACHE CONTROL

KEN# I The cache enable pin is used to determine whether the current cycle is cacheable. When the 486 microprocessor generates a cycle that can be cached and KEN # is active, the cycle will become a cache line fill cycle. Returning KEN # active one clock before ready during the last read in the cache line fill will cause the line to be placed in the on-chip cache. KEN # is active LOW and is provided with a small internal pullup resistor. KEN # must satisfy setup and hold times t14 and t15 for proper operation.

FLUSH# I The cache ffush input forces the 486 microprocessor to flush its entire internal cache.

FLUSH # is active low and need only be asserted for one clock. FLUSH # is asynchronous but setup and hold times t20 and t21 must be met for recognition in any specific clock.

PAGE CACHEABILITY

PWT

a

The page write-through and page cache disable pins reflect the state of the page PCD 0 attribute bits, PWT and PCD, in the page table entry or page directory entry. If paging is

disabled or for cycles that are not paged, PWT and PCD reflect the state of the PWT and PCD bits in control register 3. PWT and PCD have the same timing as the cycle definition pins (M/IO#, D/C# and W/R#). PWT and PCD are active HIGH and are not driven during bus hold. PCD is masked by the cache enable bit (CE) in Control Register

o.

NUMERIC ERROR REPORTING

FERR# 0 The ffoating point error pin is driven active when a floating point error occurs. FERR # is similar to the ERROR # pin on the 387TM math coprocessor. FERR # is included for compatibility with systems using DOS type floating point error reporting. FERR # is active LOW, and is not floated during bus hold.

IGNNE# I When the ignore numeric error pin is asserted the 486 microprocessor will ignore a numeric error and continue executing non-control floating point instructions. When IGNNE # is deasserted the 486 microprocessor will freeze on a non-control floating point instruction, if a previous floating point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is set. IGNNE# is active LOW and is provided with a small internal pullup resistor. IGNNE# is asynchronous but setup and hold times t20 and t21 must be met to insure recognition on any specific clock.

BUS SIZE CONTROL

8S16# I The bus size 16 and bus size 8 pins (bus sizing pins) cause the 486 microprocessor to run 8S8# I multiple bus cycles to complete a request from devices that cannot provide or accept 32

bits of data in a single cycle. The bus sizing pins are sampled every clock. The state of these pins in the clock before ready is used by the 486 microprocessor to determine the bus size. These signals are active LOW and are provided with internal pullup resistors.

These inputs must satisfy setup and hold times t14 and t15 for proper operation.

ADDRESS MASK

A20M# I When the address bit 20 mask pin is asserted, the 486 microprocessor masks physical address bit 20 (A20) before performing a lookup to the internal cache or driving a memory cycle on the bus. A20M # emUlates the address wraparound at one Mbyte which occurs on the 8086. A20M # is active LOW and should be asserted only when the processor is in real mode. This pin is asynchronous but should meet setup and hold times t20 and t21 for recognition in any specific clock.

inter

^i486™ MICROPROCESSOR

Table 1.1. Output Pins Table 1.2. Input Pins

Name Active When

Level Floated Name Active Synchronousl

Level Asynchronous

BREQ HIGH CLK

HLOA HIGH RESET HIGH Asynchronous

BEO#-BE3# LOW Bus Hold HaLO HIGH Synchronous

PWT, PCO HIGH Bus Hold AHOLO HIGH Synchronous

W/R#, O/C#, M/IO# HIGH Bus Hold EAOS# LOW Synchronous

LOCK# LOW Bus Hold BOFF# LOW Synchronous

PLOCK# LOW Bus Hold FLUSH # LOW Asynchronous

AOS# LOW Bus Hold A20M# LOW Asynchronous

BLAST# LOW Bus Hold BS16#, BS8# LOW Synchronous

PCHK# LOW KEN# LOW Synchronous

FERR# LOW ROY# LOW Synchronous

A2-A3 HIGH Bus, Address Hold BROY# LOW Synchronous

INTR HIGH Asynchronous

NMI HIGH Asynchronous

IGNNE# LOW Asynchronous

Table 1.3. Input/Output Pins

Name Active When

Level Floated

00-031 HIGH Bus Hold

OPO-OP3 HIGH Bus Hold

A4-A31 HIGH Bus, Address Hold

inter

i486TM MICROPROCESSOR

2.0 ARCHITECTURAL OVERVIEW

The 486 microprocessor is a 32-bit architecture with on-chip memory management, floating point and cache memory units.

The 486 microprocessor contains all the features of the 386™ microprocessor with enhancements to in- crease performance. The instruction set includes the complete 386 microprocessor instruction set along with extensions to serve new applications. The on- chip memory management unit (MMU) is completely compatible with the 386 microprocessor MMU. The 486 microprocessor brings the 387TM math coproc- essor on-chip. All software written for the 386 micro- processor, 387 math coprocessor and previous members of the 86/87 architectural family will run on the 486 microprocessor without any modifications.

Several enhancements have been added to the 486 microprocessor to increase performance. On-chip cache memory allows frequently used data and code to be stored on-chip reducing accesses to the external bus. RISC design techniques have been used to reduce instruction cycle times. A burst bus feature enables fast cache fills. All of these features combined, lead to performance greater than twice that of a 386 microprocessor.

The memory management unit (MMU) consists of a segmentation unit and a paging unit. Segmentation allows management of the logical address space by providing easy data and code relocatibility and effi- cient sharing of global resources. The paging mech- anism operates beneath segmentation and is trans- parent to the segmentation process. Paging is op- tional and can be disabled by system software. Each segment can be divided into one or more 4 Kbyte segments. To implement a virtual memory system, the 486 microprocessor supports full restartability for all page and segment faults.

Memory is organized into one or more variable length segments, each up to four gigabytes (232 bytes) in size. A segment can have attributes associ- ated with it which include its location, size, type (Le., stack, code or data), and protection characteristics.

Each task on a 486 microprocessor can have a max- imum of 16,381 segments each up to four gigabytes in size. Thus each task has a maximum of 64 tera- bytes (trillion bytes) of virtual memory.

The segmentation unit provides four-levels of pro- tection for isolating and protecting applications and the operating system from each other. The hardware enforced protection allows the design of systems with a high degree of integrity.

The 486 microprocessor has two modes of opera- tion: Real Address Mode (Real Mode) and Protected

Mode Virtual Address Mode (Protected Mode). In Real Mode the 486 microprocessor operates as a very fast 8086. Real Mode is required primarily to setup the processor for Protected Mode operation.

Protected Mode provides access to the sophisticat- ed memory management paging and privilege capa- bilities of the processor.

Within Protected Mode, software can perform a task switch to enter into tasks designated as Virtual 8086 Mode tasks. Each virtual 8086 task behaves with 8086 semantics, allowing 8086 software (an applica- tion program or an entire operating system) to exe- cute.

The on-chip floating point unit operates in parallel with the arithmetic and logic unit and provides arith- metic instructions for a variety of numeric data types.

It executes numerous built-in transcendental func- tions (e.g., tangent, sine, cosine, and log functions).

The floating point unit fully conforms to the ANSI/

IEEE standard 754-1985 for floating point arithmetic.

The on-chip cache is 8 Kbytes in size. It is 4-way set associative and follows a write-through policy. The on-chip cache includes features to provide flexibility in external memory system design. Individual pages can be designated as cacheable or non-cacheable by software or hardware. The cache can also be en- abled and disabled by software or hardware.

Finally the 486 microprocessor has features to facili- tate high performance hardware designs. The 1 X clock eases high frequency board level designs. The burst bus feature enables fast cache fills. These fea- tures are described beginning in Section 6.

2.1 Register Set

The 486 microprocessor register set includes all the registers contained in the 386 microprocessor and the 387 math coprocessor. The register set can be split into the following categories:

Base Architecture Registers General Purpose Registers Instruction Pointer Flags Register Segment Registers Systems Level Registers

Control Registers System Address Registers

inter

i486™ MICROPROCESSOR Floating Point Registers

Data Registers Tag Word Status Word

Instruction and Data Pointers Control Word

Debug and Test Registers

The base architecture and floating point registers are accessible by the applications program. The sys- tem level registers are only accessible at privilege level 0 and are used by the systems level program.

The debug and test registers are also only accessi- ble at privilege level

o.

2.1.1 BASE ARCHITECTURE REGISTERS Figure 2.1 shows the 486 microprocessor base ar- chitecture registers. The contents of these registers are task-specific and are automatically loaded with a new context upon a task switch operation.

General Purpose Registers

31 24₁23 16 15 el7 ⁰

AH AX AL EAX

BH BX BL EBX

CH CX CL ECX

DH DX DL EDX

SI ESI

DI EDI

BP EBP

SP ESP

Segment Registers

15 0

CS Code Segment SS Stack Segment

~)

ES Data Segments FS

GS

Instruction Pointer

31 16 15 0

I I

^IP

I

^EIP

Flags Register

I I

^FLAGS

I

^EFLAGS

Figure 2.1_ Base Architecture Registers

The base architecture includes six directly accessi- ble descriptors, each specifying a segment up to 4 Gbytes in size. The descriptors are indicated by the selector values placed in the 486 microprocessor segment registers. Various selector values can be loaded as a program executes.

The selectors are also task-specific, so the segment registers are automatically loaded with new context upon a task switch operation.

2.1.1.1 General Purpose Registers

The eight 32-bit general purpose registers are shown in Figure 2.1. These registers hold data or address quantities. The general purpose registers can support data operands of 1, 8, 16 and 32 bits, and bit fields of 1 to 32 bits. Address operands of 16 and 32 bits are supported. The 32-bit registers are named EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP.

The least significant 16 bits of the general purpose registers can be accessed separately by using the 16-bit names of the registers AX, BX, CX, DX, SI, DI, BP and SP. The upper 16 bits of the register are not changed when the lower 16 bits are accessed sepa- rately.

Finally 8-bit operations can individually access the lowest byte (bits 0-7) and the higher byte (bits 8- 15) of the general purpose registers AX, BX, CX and DX. The lowest bytes are named AL, BL, CL and DL respectively. The higher bytes are named AH, BH, CH and DH respectively. The individual byte acces- sibility offers additional flexibility for data operations but is not used for effective address calculation.

2.1.1.2 Instruction Pointer

The instruction pointer, shown in Figure 2.1, is a 32- bit register named EIP. EIP holds the offset of the next instruction to be executed. The offset is always relative to the base of the code segment (CS). The lower 16 bits (bits 0-15) of the EIP contain the 16-bit instruction pointer named IP, which is used for 16-bit addressing.

2.1.1.3 Flags Register

The flags register is a 32-bit register named EFLAGS. The defined bits and bit fields within EFLAGS control certain operations and indicate status of the 486 microprocessor. The lower 16 bits (bit 0-15) of EFLAGS contain the 16-bit register named FLAGS, which is most useful when executing 8086 and 80286 code. EFLAGS is shown in Figure 2.2.

inter

^i486™ MICROPROCESSOR

FLAGS 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 0 9 8 7 6 5 4 3 2 1 0

EFLAGS RESERVED fOR INTEL

ALIGNMENT CHECK---' VIRTUAL M O D E - - - ' RESUME F L A G - - - ' NESTED TASK F L A G - - - J I/O PRIVILEGE L E V E L - - - ' O V E R F L O W - - - -...

DIRECTION F L A G - - - . . . . J INTERRUPT E N A B L E - - - -...

240440-6 NOTE:

o

indicates Intel Reserved: do not define; see Section 2.1.6.

Figure 2.2. Flags Register EFLAGS bits 1,3,5, 15 and 19-31 are "undefined".

When these bits are stored during interrupt process- ing or with a PUSHF instruction (push flags onto stack), a one is stored in bit 1 and zeros in bits 3, 5, 15 and 19-31.

The EFLAGS register in the 485 microprocessor contains a new bit not available in the 386 micro- processor. The new bit, AC, is defined in the upper 16 bits of the register and it enables faults on ac- cesses to misaligned data.

AC (Alignment Check, bit 18)

The AC bit enables the generation of faults if a memory reference is to a misaligned address.

Alignment faults are enabled when AC is set to 1. A mis-aligned address is a word access

to an odd address, a dword access to an ad- dress that is not on a dword boundary, or an 8-byte reference to an address that is not on a 54-bit word boundary. See Section 7.1.6 for more information on operand alignment.

Alignment faults are only generated by pro- grams running at privilege level 3. The AC bit setting is ignored at privilege levels 0, 1 and 2.

Note that references to the descriptor tables (for selector loads), or the task state segment (TSS), are implicitly level 0 references even if the instructions causing the references are executed at level 3. Alignment faults are re- ported through interrupt 17, with an error code of

o.

Table 2.1 gives the alignment required for the 485 microprocessor data types.

Table 2.1. Data Type Alignment Requirements

Memory Access Alignment (Byte Boundary)

Word 2

Dword 4

Single Precision Real 4

Double Precision Real 8

Extended Precision Real 8

Selector 2

48-Bit Segmented Pointer 4

32-Bit Flat Pointer 4

32-Bit Segmented Pointer 2

48-Bit "Pseudo-Descriptor" 4

FSTENV IFLDENV Save Area 4/2 (On Operand Size) FSAVE/FRSTOR Save Area 4/2 (On Operand Size)

Bit String 4

20

IMPLEMENTATION NOTE:

Several instructions on the 486 microprocessor generate misaligned references, even if their mem- ory address is aligned. For example, on the 486 mi- croprocessor the LGDT /LiDT (load global/interrupt descriptor table) and SGDT /SIDT (store global/in- terrupt descriptor table) instructions read/write two bytes, and then read/write four bytes from a "pseu- do-descriptor" at the given address. The 486 mi- croprocessor will generate misaligned references unless the address is on a dword boundary. The FSAVE and FRSTOR instructions (floating point save and restore state) will generate misaligned references for

%

of the register save/restore cy- cles. The 486 microprocessor will not cause any AC faults if the effective address given in the in- struction has the proper alignment.

VM (Virtual 8086 Mode, bit 17)

The VM bit provides Virtual 8086 Mode within Protected Mode. If set while the 486 Micro- processor is in Protected Mode, the 486 Mi- croprocessor will switch to Virtual 8086 opera- tion, handling segment loads as the 8086 does, but generating exception 13 faults on privileged opcodes. The VM bit can be set only in Protected Mode, by the IRET instruc- tion (if current privilege level ⁼ 0) and by task switches at any privilege level. The VM bit is unaffected by POPF. PUSHF always pushes a

o

in this bit, even if executing in virtual 8086 Mode. The EFLAGS image pushed during in- terrupt processing or saved during task switches will contain a 1 in this bit if the inter- rupted code was executing as a Virtual 8086 Task.

RF (Resume Flag, bit 16)

The RF flag is used in conjunction with the debug register breakpoints. It is checked at instruction boundaries before breakpoint pro- cessing. When RF is set, it causes any debug fault to be ignored on the next instruction. RF is then automatically reset at the successful completion of every instruction (no faults are signalled) except the IRET instruction, the POPF instruction, (and JMP, CALL, and INT instructions causing a task switch). These in- structions set RF to the value specified by the memory image. For example, at the end of the breakpoint service routine, the IRET instruc- tion can pop an EFLAG image having the RF bit set and resume the program's execution at the breakpoint address without generating an- other breakpoint fault on the same location.

NT (Nested Task, bit 14)

This flag applies to Protected Mode. NT is set to indicate that the execution of this task is nested within another task. If set, it indicates

that the current nested task's Task State Seg- ment (TSS) has a valid back link to the previ- ous task's TSS. This bit is set or reset by con- trol transfers to other tasks. The value of NT in EFLAGS is tested by the IRET instruction to determine whether to do an inter-task return or an intra-task return. A POPF or an IRET instruction will affect the setting of this bit ac- cording to the image popped, at any privilege level.

10PL (Input/Output Privilege Level, bits 12-13) This two-bit field applies to Protected Mode.

10PL indicates the numerically maximum CPL (current privilege level) value permitted to ex- ecute I/O instructions without generating an exception 13 fault or consulting the I/O Per- mission Bitmap. It also indicates the maximum CPL value allowing alteration of the IF (INTR Enable Flag) bit when new values are popped into the EFLAG register. POPF and IRET in- struction can alter the 10PL field when execut- ed at CPL = O. Task switches can always al- ter the 10PL field, when the new flag image is loaded from the incoming task's TSS.

OF (Overflow Flag, bit 11)

OF is set if the operation resulted in a signed overflow. Signed overflow occurs when the operation resulted in carry/borrow into the sign bit (high-order bit) of the result but did not result in a carry/borrow out of the high-order bit, or vice-versa. For 8-, 16-, 32-bit opera- tions, OF is set according to overflow at bit 7, 15, 31, respectively.

OF (Direction Flag, bit 10)

OF defines whether ESI and/or EDI registers postdecrement or postincrement during the string instructions. Postincrement occurs if OF is reset. Postdecrement occurs if OF is set.

IF (INTR Enable Flag, bit 9)

The IF flag, when set, allows recognition of external interrupts signalled on the INTR pin.

When IF is reset, external interrupts signalled on the INTR are not recognized. 10PL indi- cates the maximum CPL value allowing altera- tion of the IF bit when new values are popped into EFLAGS or FLAGS.

TF (Trap Enable Flag, bit 8)

TF controls the generation of exception 1 trap when single-stepping through code. When TF is set, the 486 Microprocessor generates an exception 1 trap after the next instruction is executed. When TF is reset, exception 1 traps occur only as a function of the breakpoint ad- dresses loaded into debug registers DRO- DR3.