An Assessment of ?-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008 1563

An Assessment of µ-Czochralski, Single-Grain

Silicon Thin-Film Transistor Technology for

Large-Area, Sensor and 3-D Electronic Integration

Nitz Saputra, Student Member, IEEE, Mina Danesh, Member, IEEE, Alessandro Baiano, Ryoichi Ishihara,

John R. Long, Member, IEEE, Nobuo Karaki, Member, IEEE, and Satoshi Inoue, Senior Member, IEEE

Abstract—Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the -Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrys-tallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350 C, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode oper-ational amplifier fabricated in an experimental 1.5 m SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain band-width of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With _T comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices.

Index Terms—Flexible electronic circuits, large area electronics, -Czochralski fabrication, operational amplifier, pin diodes, RF amplifiers, single-grain thin-film transistor (SG-TFT), 3-D integra-tion, voltage reference.

I. INTRODUCTION

F

ABRICATION of electronic devices over a surface area many times larger than a traditional silicon IC on non-conventional (e.g., glass or plastic) substrates is driving products such as flat panel displays, into the commercial mar-ketplace. Low-cost manufacturing of transistors dispersed over large-area substrates has been realized through the development of thin-film transistor (TFT) technologies using amorphous silicon, polysilicon, and more recently, organic materials as a base [1], [2]. However, the field-effect mobility of these thin-film devices is poor when compared to similar-sized

Manuscript received November 21, 2007; revised February 27, 2008. This work was supported by Seiko-Epson Corporation, Fujimi JP, and the Dutch Technology Foundation, STW.

N. Saputra, M. Danesh, A. Baiano, R. Ishihara, and J. R. Long are with the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology, Delft, The Netherlands (e-mail: nitz_s@hotmail.com).

N. Karaki and S. Inoue are with the Frontier Device Research Center, Seiko-Epson Corporation, 391-0213 Nagano, Japan.

Digital Object Identifier 10.1109/JSSC.2008.922404

transistors made in bulk CMOS, which limits the speed or bandwidth of electronic circuits. The -Czochralski process is a novel, low-cost, and potentially higher performance method for thin-film transistor fabrication (see Fig. 1). Transistors are fabricated inside location-controlled silicon (Si) grains that are defined by a grain filter using excimer-laser crystallization of a polysilicon film. The transistors produced in this way have relatively high field-effect mobilities and they exhibit electrical characteristics comparable with conventional silicon-on-insu-lator (SOI) MOSFETs [3]. Excimer-laser crystallization defines the Si grains, which are single-crystal “islands” of silicon, with precise position control of the grain size and quality using pro-cessing steps that do not require temperatures exceeding 350 C [4]. Field-effect electron mobility as high as 600 cm V s [5] has been demonstrated for single-grain (SG) Si-TFTs produced by the -Czochralski process, enabling fabrication of digital, analog, and even RF circuits [6], [7] on large-area substrates. For example, a computer on a flexible (or rollable) substrate could be designed where memory, a processor core, analog/mixed-signal and RF circuits are integrated together with a flat-panel display. Three-dimensional (3-D) integration of circuits is another potential application, as the underlying devices are not affected by heat cycling from the relatively low temperatures encountered in the -Czochralski process.

In this paper, the capabilities of -Czochralski SG-TFTs are benchmarked using representative circuit examples. Key ele-ments of the SG-TFT technology developed by researchers at the DIMES facility of the Delft University of Technology are presented, including: a brief summary of the process, device characterization and modeling, and characterization results for analog and RF benchmarking circuits. The SG-TFTs used in this work demonstrate a unity-gain frequency ( ) of 5-6 GHz for a gate length of 1.5 m, far surpassing other TFT technolo-gies at this level of lithography [8], [9]. A SPICE-compatible, modified BSIM-SOI model that matches measured DC and AC characteristics of the SG-TFT is also described briefly. This model is used to design analog operational amplifier (opamp) and voltage reference ( ) demonstrators in the SG-TFT tech-nology. Operational amplifiers and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuit performance. In addition, SG-TFT RF charac-teristics are described, as well as the performance of RF am-plifier circuits built using on-chip spiral inductors. Good agree-ment between simulation and measureagree-ment results is obtained for these test cases, which validates the SG-TFT technology

and demonstrates its potential for realizing high-performance analog/RF applications on large-area substrates.

II. SINGLE-GRAINSILICONTFT FABRICATION

Precise position control of silicon (Si) grains fabricated using relatively low processing temperatures (i.e., 350 C) is an ad-vantage of the -Czochralski recrystallization method [4]. Re-cent developments have shown that the desired crystal ori-entation for a single crystal grain can also be controlled in pro-cessing [10]. Additionally, device fabrication at temperatures below 100 C has been realized, which enables the use of cost-effective plastic substrate materials [11].

Oxidized Si wafers may be used as the starting material, al-though the maximum processing temperature after amorphous silicon (a-Si) deposition is well below the glass deformation temperature of 350 C. Since it is a low-temperature process, if the Si wafer is replaced with a glass substrate the same result should be obtained [12]. To minimize the dissipation of high-frequency energy in the substrate, a 2 k cm Si wafer is used for RF circuits. First, 1- m-diameter holes are formed by conven-tional I-line photolithography and anisotropic dry etching of a 750-nm-thick thermal SiO layer. An 875-nm-thick SiO layer is then deposited by TEOS PECVD at a substrate temperature of 350 C in order to reduce the hole diameter to approximately 100 nm. This is the maximum temperature seen by the devices during fabrication. A 250-nm-thick a-Si film is then deposited by LPCVD. After a threshold-adjust implant of boron (B) ions for both n- and p-channel transistors (2.5 cm ), a single 56-ns-long pulse of light from a XeCl (308 nm) excimer-laser irradiates the Si surface. Silicon grains of 6 m per side are thereby obtained in predetermined positions via a recrystalliza-tion known as the -Czochralski process.

A scanning electron microscope (SEM) image of loca-tion-controlled grains formed after defect delineation etching is shown in Fig. 2. Although random grain boundaries are absent inside the grains, some of the grains have planar defects which are generated from either the center of the film or from the rim of the grain filter. Electron backscattering diffraction (EBSD) analysis of such grains showed that the planar defects generated from the holes are mainly coincidence site lattice (CSL) boundaries, followed by , which are reported to be electrically less active than random grain boundaries [13], [14]. Subsequently, the Si film is patterned into islands by reactive ion etching. The transistors are designed such that a single grain covers the entire channel area of a TFT. A 30 nm TEOS-PECVD SiO layer is then deposited as a gate insulator at 350 C. Alu-minum (Al) sputtered at room temperature forms the gate elec-trode. The source and drain are implanted with either P or B ions (1 cm ) depending on the device type, which is then activated by the excimer-laser annealing. After SiO passi-vation and contact hole formation, Al interconnect metal is sput-tered and patterned. This process is repeated to define two metal layers for circuit interconnections. The minimum gate length of transistors fabricated in the DIMES facility at TU Delft is 1.5 m, whereas the maximum gate width permitted by the grain size is 5 m. The channel length is limited by the lithographic tools used in fabrication, and 0.5 m gate length TFTs have been

fabricated on an industrial scale by Seiko-Epson in Japan using a similar process flow [15].

III. SG-TFT MODELING

The BSIM-SOI model [16]–[18] was chosen as the basis for modeling the SG-TFT devices. It employs most of essential silicon-on-insulator (SOI) MOSFET physics from BSIM-SOI, but the mobility model was modified in order to model the ef-fect of coincident site lattice (CSL) grain boundaries present in the TFT channel, as shown in Fig. 2. The atoms at the CSL grain boundary are distorted. Although less significant than the random grain boundaries (GB) present in polysilicon [18], these grain boundaries can form charge trapping sites that are capable of creating a potential barrier, impeding the motion of carriers, thereby reducing the effective channel mobility.

It is assumed that the SG-TFT channel consists of a number CSL-GBs that separate CSL silicon grains with an average intra-grain length of and an average CSL-GB length . Given these assumptions, the conduction in a SG-TFT above threshold voltage can be described by a combination of drift in the silicon grain, and thermionic emission across the CSL-GBs, according to Mathiessen’s rule [19]:

(1) where is the effective carrier mobility and is the mo-bility in the crystalline silicon used in the BSIM-SOI model. Parameter is the mobility across the grain boundary and is added to the BSIM-SOI model with a new fitting parameter, . This parameter relates the proportion of the CSL to the crystalline Si boundary and unifies the polysilicon and SOI models. It is equal to zero when there are no CSL-GBs in the channel, thus the mobility model approaches the formu-lation used in BSIM-SOI. Parameter further depends upon the gate voltage as given by the following equation [18]:

(2)

where is the zero-field carrier mobility, which is 670 cm V s for nMOS and 250 cm V s for pMOS devices. Fitting parameters and model the degradation due to the normal electric field. is the transistor threshold voltage,

is a smoothing function that approaches

above threshold, and is the gate oxide thickness. Mobility across the grain boundary ( ) is described by the following thermionic relation [20]:

(3) where is the mobility in the CSL-GB and is the potential barrier height, which depends upon the gate bias voltage [21]. For simplicity, the potential barrier height is described by an empirical equation that utilizes the smoothing function according to the following equation:

SAPUTRA et al.: ASSESSMENT OF µ-CZOCHRALSKI, SINGLE-GRAIN SILICON THIN-FILM TRANSISTOR TECHNOLOGY 1565

Fig. 1. (a) Top and (b) side view of a TFT built on top of a single grain (c) made by a grain filter (d) using the-Czochralski process.

Fig. 2. Electron back scattering diffraction image showing coincidence site lat-tice grain boundaries (GBs)63 (gray) 69 (black) and random GBs (white).

where is the maximum potential barrier height. Fitting parameter describes decreasing grain boundary potential when the gate potential increases.

After modifying the existing BSIMSOI model as described previously, a parameter extraction was carried out to obtain a complete set of DC model parameters with channel scalability.

Measured results were then compared to the DC characteris-tics simulated via the modified BSIM-SOI model to verify the quality of fit. Fig. 3 shows a comparison of transfer ( versus ) and output ( versus ) characteristics to measured data for n- and p-channel SG-TFTs with 5 m channel width and length. Fig. 4 illustrates the agreement between simulated char-acteristics for shorter channel length ( m) and experi-mental results. The good agreement seen in both cases verifies the scalability of the modified BSIM-SOI model.

After DC parameter extraction and verification, parameters required by BSIM-SOI to model small-signal (AC) behavior were determined. Firstly, the simulated capacitance between gate and source/drain of specific SG-TFT devices is adjusted to fit parasitic capacitances measured at a frequency of 1 MHz, yielding results as shown in Fig. 5. Since the body terminal is floating, no capacitance is measured in the accumulation region. Secondly, two-port -parameters of n-channel, multi-finger SG-TFTs with 500 m equivalent channel width and 1.5 m channel length over a frequency range of 50 MHz to 6.05 GHz were measured. Scattering ( )-parameter data is collected as the drain voltage is varied between 3 and 5 V, for gate voltages ranging from 2 to 4 V. Parasitic effects of the transistor test structures were removed by -parameter de-embedding in order to obtain the intrinsic transistor behavior at RF [22]. This data is then used to determine the remaining AC parameters for the BSIM-SOI model. Agreement between simulation and -parameter data after fitting (see Fig. 6) has an absolute RMS error below 1% between measured and simulated data over the entire range of bias voltages and frequency.

This complete set of extracted model parameters was sub-sequently used for simulation and design of circuits. Small

Fig. 3. Measurement and simulation results of SG-TFTs (W = 5 m, L = 5 m): n-channel transfer (a) and output (b) characteristics, and p-channel transfer (c) and output (d) characteristics.

Fig. 4. Measurement and simulation results of short (1.5 m) n-channel SG-TFTs output characteristics forV = 0 to 6 V with a 1 V step.

changes were made to the model parameter set in order to ac-count for changes in device behavior caused by batch-to-batch variations in processing. The simulation capabilities will be extended in the future by adding models for temperature de-pendence and noise sources unique to the SG-TFT.

IV. DEVICECHARACTERISTICS

SG-TFTs fabricated using the -Czochralski method are capable of electrical performance comparable to single-crystal

Fig. 5. Measurement and simulation results of capacitance between gate and source-drain.

transistors [5], as shown in Table I. This enables new applica-tions for digital, analog and mixed-signal circuits and systems (e.g., large-area systems on-chip) which can leverage the po-tential cost/area advantages of the technology. Although the SG-TFT offers excellent electrical performance, parameters of transistors fabricated in different grains can vary by as much as 10% within a single die. This is caused mainly by crystal defects and variation of the crystal orientation on each Si grain or island. Alignment errors during lithography steps, which is one of the main sources of parameter mismatch in other

SAPUTRA et al.: ASSESSMENT OF µ-CZOCHRALSKI, SINGLE-GRAIN SILICON THIN-FILM TRANSISTOR TECHNOLOGY 1567

Fig. 6. Measurement and simulation results of SG-TFTS-parameters with W = 500 m, and L = 1:5 m for V = 2 V, V = 3 V and V = 4, V = 5 V.

TABLE I

SG-TFT PERFORMANCEPARAMETERS

technologies [23], is also a source of parameter variation for SG-TFTs. Mismatch between a pair of transistor can cause an offset voltage in an analog circuit. Such offsets are minimized by controlling the crystal orientation [10] and by placing transistor pairs (or multiple transistors) inside a single grain. Since the grain size at present is limited to 6 6 m , only two transistors at most can be placed inside a single grain for a minimum gate length of 1.5 m, as illustrated in Fig. 7. Fig. 8(a) and (b) show the statistical variation ( ) of the mobility and threshold voltage for both nMOS and pMOS devices between different dice, within a single die, and within a single grain.

The silicon channel region is fully-depleted when the silicon thickness is less than the maximum depletion-region width extending from an inverted surface [24]. Since the silicon layer beneath the gate is 250 nm thick and the maximum deple-tion width is approximately 285 nm, the SG-TFT channel is fully-depleted when the channel is inverted (i.e., in normal op-eration). The fully-depleted TFT offers additional advantages, including reduced hot-electron effects, improved subthreshold slope, threshold-voltage stability, a higher source-drain

break-Fig. 7. Physical layouts for multiple transistors implemented in a single grain.

down voltage, and reduced parasitic bipolar effect [25]. As a result, the SG-TFT should exhibit good reliability and has no threshold shift due to the body effect.

For the construction of analog and RF circuits, passive de-vices such as resistors, capacitors, inductors, diodes and trans-mission lines are required, and these devices have also been

in-Fig. 8. Measured mobility and threshold voltage variations of a SG-TFT (W = 4:5 m and L = 1:5 m) within a single grain, intra die (die size = 10 mm 2 10 mm), and inter die (wafer-size = 100 mm diameter).

tegrated into the SG-TFT process flow and characterized. The polysilicon thin-film resistor, which can be used for biasing and load resistors, has a sheet resistivity of 45 . Linear metal–insulator–metal (MIM), and MOS (gate) capacitors are also available for coupling, decoupling and waveshaping in cir-cuits. Spiral microstrip inductors, required for on-chip resonant circuits at RF, have been realized using two layers of intercon-nect metal. Also, a lateral photosensitive p-i-n (pin) diode was realized by inserting almost intrinsic silicon between heavily doped p and n bulk silicon regions. Fig. 9 shows the measured photocurrent of the pin diode under dark and light conditions. The pin diode can also be used as an RF switch, in a temperature sensor or in voltage reference circuitry.

V. ANALOGBENCHMARKINGCIRCUITS

Although the SG-TFT performance approaches that of single crystal CMOS, several of the characteristics of these TFTs present difficulties to the analog circuit designer. Firstly, the spread of device electrical parameters, such as threshold voltage and carrier mobility, is much larger than for conven-tional CMOS. Secondly, the kink effect [26] in TFTs, which gives excess current due to impact ionization, results in a low output impedance making high voltage gain and power supply rejection ratio (PSRR) difficult to achieve. Finally, the channel mobility is strongly gate-bias dependent, and it is smaller at the low gate-bias levels commonly used in analog amplifiers than at the high gate voltages commonly used in digital circuits [27]. On the other hand, SG-TFT technologies offer advantages over bulk CMOS, such as less parasitic capacitance, immunity to latch-up, and no body effect. Two key analog circuit building blocks, specifically, opamps and voltage references, were built using SG-TFT technology and characterized.

Fig. 9. Measured photocurrent of the pin diode under reverse bias for dark (black) and under illumination with white light (gray).

TABLE II

SG-TFT ANALOGCIRCUITSSPECIFICATIONS

A CMOS opamp is one of the building blocks for many analog circuit applications. For example, it is used as a general purpose gain block in active filters, analog-to-digital (A/D) converters, supply voltage regulators and other analog signal processing and interfacing blocks. Building opamps in the SG-TFT process is the first step to evaluate the technology’s capability, and to identify deficiencies that need to be solved with process modifications or circuit design technique. A voltage reference is required by many A/D and D/A converter designs and for precision biasing of analog circuits. The ref-erence voltage output should be independent of changes in the power supply, temperature and processing variations. The variations seen between devices fabricated in different grains using the -Czochralski process can therefore be characterized in a circuit context through the fabrication and evaluation of voltage reference circuits. The desired target specifications for a small number of key parameters required from both circuit blocks are summarized in Table II.

Two batches of wafer were characterized, and on average the measured performance agrees well with the behavior pre-dicted by the modified BSIM-SOI model. Fig. 10 shows the chip photograph of the opamp and voltage references fabricated for this study. Automated test measurement setups using on-wafer probing were used to characterize 50 circuit samples per batch quickly and accurately.

SAPUTRA et al.: ASSESSMENT OF µ-CZOCHRALSKI, SINGLE-GRAIN SILICON THIN-FILM TRANSISTOR TECHNOLOGY 1569

Fig. 10. Chip micrograph of the (a) opamp and (b) voltage reference test circuits.

In order to benchmark the SG-TFT technology for analog circuit applications, circuits ranging from single gain stages to more complex opamps using gain boosting amplifiers were de-signed and fabricated [28]. The simplest opamp (not reported here) is not designed to achieve the required specifications, but to be tested for functionality as a gain block, offset voltage char-acterization due to mismatch, and for its intrinsic voltage gain. The intrinsic voltage gain (gm/gds) of the SG-TFT is approx-imately 15 dB, which is close to that of a bulk CMOS tran-sistor fabricated in a 65 nm process. It should be noted that opamp topologies requiring a larger number of transistors (e.g., gain-boosted folded cascode versus folded cascode) are consid-ered riskier to implement successfully, given the level of matu-rity of this new technology.

The key specification for the opamp is the gain, therefore most of the opamp designs selected for specification use cas-coding to increase the output impedance of the TFT stages. An additional stage is implemented to further increase the DC gain of the opamp in some of the designs. A two-stage design with cascoding achieved more than 60 dB of DC gain. The drawback of the two stage design is less stability because of phase shift introduced by the second stage. It also consumes more power than a single-stage opamp. Gain boosting increases the gain of the opamp with minimal increase in power consumption, while conserving the stability advantage of a single-stage opamp. Cur-rent consumption was limited to 100 A for the test designs. Simulation showed that this current is enough to attain the spec-ified unity gain bandwidth (UGBW).

The gain and unity gain bandwidth of the selected opamps were measured and the average values and its variance are sum-marized in Table III. Single stage opamps using a cascode (tele-scopic, folded cascode, and current mirror) realize a DC gain of about 40 dB on average. The telescopic opamp shows the widest bandwidth, followed by the current mirror and folded cascode designs. This result is expected, as the telescopic topology has

Fig. 11. Schematic of the two-stage telescopic opamp test circuit.

a lower secondary pole and hence greater bandwidth. The gain boosted topologies (gain-boosted telescopic and gain-boosted folded cascode) achieve approximately 50 dB of gain on av-erage. The gain boosting amplifier implemented adds an addi-tional 10 dB of gain (gain could be further increased by using a more sophisticated boosting amplifier). The two-stage opamps (e.g., two-stage telescopic and two-stage folded cascode) were able to exceed the desired specification, as they have 55 dB of DC gain. Again the telescopic topology shows superior band-width than the folded cascode. The measured and simulated small-signal (AC) response of the two-stage telescopic opamp (shown in Fig. 11) is illustrated in Fig. 12. Although 5 MHz of UGBW is the desired specification for the opamps, simula-tion predicts over 100 MHz unity-gain bandwidth when driving a 1 pF load. The circuit bandwidth is ultimately limited by the maximum of the thin-film transistor.

TABLE III

OPAMPPERFORMANCESUMMARY

Fig. 12. Measured and simulated small-signal response of the opamp of Fig. 10.

As previously mentioned, a large variation of the transistor parameters occurs in SG-TFT technology, similar to deep-sub-micron bulk CMOS technologies (i.e., below 180 nm gate length). Any mismatch or defect in the transistor will produce an offset voltage in the opamp. In order to minimize device mismatch, the opamps were built using multiple single-grain transistors in parallel. This redundancy helps improve the yield, as any defect will only create an offset instead of failure. By uti-lizing multiple gate fingers, the offset tends to an average value. The measured offset of the opamps is around 100 mV-rms. This level of offset is tolerable in some applications (e.g., biasing circuits), but for precision applications such as high resolu-tion sensor interfaces the offset must be further minimized. Dynamic offset cancellation techniques, such as auto-zeroing and chopper stabilization could be implemented to reduce the offset voltage [29], [30]. Moreover, the circuit can be trimmed or calibrated using built-in self-test methods to further enhance the performance [31]. Simulation results showed that the rms value of the offset can be reduced to below 1 mV in a SG-TFT opamp by using chopper stabilization [32].

The original target specifications listed in Table II were attain-able using most (but not all) of the topologies designed and fab-ricated in SG-TFT technology. Given the encouraging first-pass results, a 100 dB of DC gain and 100 MHz unity-gain-band-width opamp for use in functional blocks such as a fast sample-and-hold should be realizable. The modified BSIM-SOI tran-sistor model predicts the gain and the first pole observed in the opamp frequency response accurately, although it will require

some refinement in order to include the anticipated processing variations for SG-TFTs.

Voltage reference circuits require an electronic element that is insensitive to variation over a range of supply voltages, tempera-tures and process corners. The bandgap voltage reference offers excellent immunity to changing temperature and process spread [33]. However, the circuit requires a bipolar junction transistor or a p-n junction diode for implementation. Since junction diode elements have not been well characterized in the SG-TFT tech-nology, MOSFET-only voltage references were designed and characterized in this study.

MOSFET-only voltage references have demonstrated excel-lent immunity to supply voltage variation. Three distinct CMOS voltage reference topologies were implemented in SG-TFT technology [28], [34] and the average measured performance of 50 samples with its variance is summarized in Table IV. A 5 V voltage supply was used in measurement. The low power CMOS voltage [34] consumes little current (34 nA on average), but only achieves 26 dB of PSRR. An nMOS-only voltage reference with a resistive feedback is able to achieve the specification of 40 dB PSRR, while a delta- reference, as in Fig. 13, achieves 50 dB of PSRR, despite a higher current consumption. These circuits make extensive use of cascodes to improve the output impedance and PSRR. A feedback am-plifier is added to further improve the output impedance of the delta- reference.

The voltage references implemented and measured in the SG-TFT technology were able to meet the desired specifica-tions. However, the CMOS based voltage reference exhibited a relatively large measured variation of 20% in its output voltage. Thus, this type of reference would require calibration or trim-ming before use in an analog application (e.g., A/D converter). The current consumption is higher than expected because the thin-film resistor was not accurately modeled for this design cycle. The modified BSIM-SOI model predicts the PSSR and voltage reference values quite accurately.

VI. RF CIRCUITS

Integrating radio-frequency circuits in SG-TFT technology could enable a range of wireless applications not yet present in the market, such as wireless e-paper or wireless smart cards. One potential advantage of this technology, aside from low-cost of fabrication, is complete integration of a system on the same

SAPUTRA et al.: ASSESSMENT OF µ-CZOCHRALSKI, SINGLE-GRAIN SILICON THIN-FILM TRANSISTOR TECHNOLOGY 1571

TABLE IV

VOLTAGEREFERENCEPERFORMANCESUMMARY

Fig. 13. Schematic of the voltage reference test circuit.

substrate (analogous to SoC). For example, an embedded 2-D or even 3-D stacked configurations could be built. 3-D systems are envisioned where one layer of transistors could be used for RF high-frequency circuits, a second layer for analog and biasing circuits, a third layer for digital circuits, and a fourth layer for the display screen as shown in Fig. 14. In this concept, there is no need for extra interconnects (e.g., a PCB carrier, wire-bonds, or flip-chip packaging) that add parasitic elements and alter the performance of the circuits at high frequencies. As the -Czochraslki fabrication method is a low temperature process, antennas and passive elements can be directly fabricated to-gether with the SG-TFT on a flexible substrate material, such as glass or polymer plastics to realize high-performance RF sys-tems and sub-syssys-tems that can also be low cost.

Prototype SG-TFT transistors are assessed at RF in order to benchmark their performance limitations caused by parasitic effects, and to validate device models for RF circuit designs. Transistors of varying width, length, and multiple fingers were built for both nMOS and pMOS types. RF circuits incorporating nMOS and pMOS SG-TFTs and passive devices were measured over the frequency range from 50 MHz to 20 GHz. -parameter measurements made using a vector network analyzer were cor-rected for parasitic effects using separate de-embedding open and short test structures [22].

Fig. 14. 3-D circuit integration concept.

Multiple finger devices achieve sufficient transconductance ( ) and gain at RF with low extrinsic gate resistance, as alu-minum metal is used for the gate. In the physical layout, a square 6 6 m grain was used. Gate width and length ranging from 1.5 m to 5 m were investigated in simulation and experi-mentally, where maximum gate area is limited by the constraint that the TFT transistor channel must fit inside a single grain. In order to reduce the number of grains required for multiple finger TFTs, a 5 m gate width was selected for each finger. A 1 m extension of the gate metal length is required to connect gates of adjacent rows while avoiding the grain boundary. Fig. 15(a) shows a 500 1.5 m TFT device with 20 fingers and 5 rows. Dual-gate nMOS TFTs, where both gates are within the same grain, were also designed for use in cascode amplifier circuits, as seen in Fig. 15(b). Both gates are included in the same grain (i.e., 2 m apart from each other), thereby sharing the same ac-tive region and reducing the effect of the parasitics at the inter-stage node in the cascode. On-chip spiral inductor connected to the source sets a 50 input impedance via local feedback, while forms part of the resonant tank loading the drain.

Fig. 16(a) and (b) show the measured -parameters of the 500 1.5 m nMOS transistor of Fig. 15(a). As shown in the

Fig. 15. (a) 5002 1.5 m SG nMOS-TFT used for RF characterization. (b) Cascode amplifier using a dual-gate SG-TFT.

Smith chart of Fig. 16(a), the input impedance (from ) is ca-pacitive due to the gate-to-source capacitance, . The output impedance (from ) seen at the drain of the transistor is also capacitive (due to the gate-to-drain capacitance, ) but has a significant resistive part due to the 290 output resistance of the transistor. These results are for an unmatched transistor, so the forward gain (for 50 source and load impedances) is relatively small at 2.3 dB. Impedance matching the transistor input and output can substantially raise this voltage gain, as will be seen in the following RF amplifier example. quantifies the isolation of the amplifier in a 50 system, which is better than 20 dB for frequencies below 1 GHz. Fig. 16(c) reveals that the measured current gain-bandwidth is 5.45 GHz at a drain-source and gate-source bias of 3 V ( mA and mS) for the 500 1.5 m nMOS TFT. The corresponding unity-power-gain frequency is 11.45 GHz, as shown in Fig. 15(d). For a drain current of 30 mA where is 5 V, reaches 6.5 GHz and , 15.5 GHz. For 600 1.5 m pMOS devices biased at V and V, the drain current is 50 mA, and the measured and are 4.3 and 4.4 GHz, respectively. With unity gain bandwidths in the 5–6 GHz range, amplifiers can be designed in the sub-1-GHz frequency ranges with expected gains on the order of 10 dB. Oscillators can also be designed well into the gigahertz range.

A cascode amplifier designed for the 433 MHz ISM band is shown in Fig. 17. The cascode dual-gate TFT and source and drain spiral inductors contained in the chip are shown in the micrograph of Fig. 15(b). The cascode topology improves the amplifier gain, stability, and reverse isolation by limiting the Miller effect across the input transistor. The cascode amplifier circuit uses a 35 nH load on-chip inductor ( ) designed for a resonance of 430 MHz. The source inductance ( ) of 3 nH sets a 50 input impedance with minimum noise figure for this amplifier. These inductors are implemented in the second (top Al) metal layer and the circuits are fabricated on a high-resistivity (2 cm) silicon substrate (note that an insulating

Fig. 16. Measured RF performance for the 5002 1.5 m transistor: (a) S andS in Smith chart; (b) S and S ; (c) h and G versus frequency.

SAPUTRA et al.: ASSESSMENT OF µ-CZOCHRALSKI, SINGLE-GRAIN SILICON THIN-FILM TRANSISTOR TECHNOLOGY 1573

Fig. 17. Cascode RF amplifier schematic diagram.

Fig. 18. MeasuredQ-factor for 35 nH and 3 nH inductors.

glass substrate could be used instead of silicon to reduce losses further). The top metal thickness is 1.4 m. A conductor spacing of 4 m and a conductor width of 8 m and 10 m were used for the 35 nH and 3 nH inductors, respectively. Fig. 18 shows the measured quality factor ( ) of both inductors, which ranges from 2 to 5 between 200 MHz and 1 GHz. At these frequencies, the is mainly limited by the top metal thickness. Maximum factors of 4.8 at 1 GHz and 8 at 7 GHz are seen for the 35 nH and 3 nH inductors, respectively.

Simulated and measured results for the amplifier, based on the SG-TFT BSIM-SOI transistor model and electromagnetic simulation for on-chip inductors, are listed in Table V. Fig. 19 shows the amplifier -parameters for both simulated and mea-sured data, which are comparable, thus validating the BSIMSOI transistor model. The 433 MHz ISM amplifier achieves useful RF gain of more than 10 dB, good isolation (lower than 25 dB), and an input third order intercept point (IIP3) of 10 dBm. Such an amplifier could also be used in the IF stage of a transmitter or receiver operating at a higher RF front-end frequency. An

Fig. 19. Measured(S m; S m; S m; S m) and simulated S-parameters (S s; S s; S s; S s) for the SG-TFT RF amplifier.

TABLE V

SG-TFT RF AMPLIFIERRESULTSUMMARY

off-chip inductor, , of 170 nH with a of 40, in series with the gate is needed for input matching of the 433 MHz ISM band cascode amplifier. The TFT technology permits such an inductor to be built and integrated together with the active de-vices if an insulating substrate is used. At the drain, an external series capacitor of 3.5 pF is required to resonate with the load inductor at 430 MHz to provide the output matching. In fu-ture work, small-signal noise of the SG-TFT will be character-ized and noise parameters defined for simulation and design of low-noise RF amplifiers using the modified BSIM-SOI model.

VII. APPLICATIONS

One of the applications originally proposed for -Czochralski fabricated SG-TFTs is e-paper, where electronic display and signal processing elements are embedded onto a paper-like flex-ible substrate. Since TFT technology is often associated with flat panel displays, any existing fast-response flat panel (or future display technology) could incorporate SG-TFTs for improved performance. Displays fabricated on a flexible or “rollable” sub-strate material could also incorporate this technology for pixel switching, pixel addressing, signal processing, and communi-cation electronics (both analog and digital). Other applicommuni-cations, such as wearable sensors, where a thfilm silicon sensor is in-tegrated together with interface electronics (e.g., A/D or D/A converters), RF communication circuitry, and a silicon solar cell as a power source may also be enabled by SG-TFT tech-nology. The current benchmark circuit result shows that low res-olution converters can be built. RF front-end for below 1 GHz range is the application that currently reachable based on this assessment. This technology is currently able to build low-cost low-performance wireless sensor systems.

The pixellated nature of the Si grains makes them suitable for implementation of image sensors on a flexible substrate. The pin photodiode implemented in this technology may make such applications possible. By adding the wireless communications functionality, short range low data rate applications for two-way communication, such as for smart cards and health monitoring for wearable biomedical implants or body area sensor networks can be realized. Moreover, by integrating the antenna and other passive elements directly with the RF integrated circuits without extra losses due to impedance matching and high sub-strate losses, a complete compact wireless SoC can be offered.

SG-TFT technology using -Czochralski process could enable vertical stacking of integrated circuits or 3-D ICs, for greater integration density. The increasing delay caused by the parasitic capacitance of on-chip interconnects and their resistance seen in 2-D SoCs could be solved by vertically stacking devices using SG-TFT technology. Feasibility of stacking SG-TFTs on successive silicon layers was recently demonstrated for a 3-D CMOS inverter [35].

VIII. CONCLUSION

Analog and RF circuit demonstrators using the SG-TFT technology were presented, which validated the performance of SG-TFTs in some key benchmarking circuits and verified a design flow from process to modeling and circuit design for this new technology. This included many analog/RF device options (e.g., linear resistor, inductors and pin diodes). With a minimum gate length of 1.5 m for the DIMES technology, transit frequencies in the range of 5–6 GHz for the SG-TFTs were obtained. A modified BSIM-SOI model was developed for circuit simulation, which was employed to design and realize opamps with more than 50 dB DC gain and a voltage reference with 50 dB PSRR successfully. RF amplifiers that can realize well over 10 dB gain below 1 GHz have also been implemented and demonstrated using the SG-TFT technology with integrated back-end metal spiral inductors. The results demonstrated in this work are a promising first step towards realization of 2-D,

and possibly 3-D ICs, that can enable electronics fabricated on low-cost substrate materials, where digital, analog and RF circuits could be integrated together with other technologies (e.g., flat-panel displays or imagers).

ACKNOWLEDGMENT

This work was made possible by the dedication and hard work of many process engineers in the DIMES facility, and enabled by the cleanrooms and measurement facilities at the DIMES re-search institute. The authors gratefully acknowledge the tech-nical support provided by Seiko-Epson and thank T. Shimoda, Y. Hiroshima, and D. Abe for many interesting and fruitful dis-cussions. The authors would like to express special thanks to S. van Herp, J. Slabbekoorn, P. Swart, and B. Goudena for their technical assistance and support.

REFERENCES

[1] V. Subramanian and K. C. Saraswat, “High-performance germa-nium-seeded laterally crystallized TFT’s for vertical device integra-tion,” IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1934–1939, Sep. 1998.

[2] Y. Matsueda, T. Ozawa, M. Kimura, T. Itoh, K. Kitawada, T. Nakazawa, and H. Ohsima, “A 6-bit-color VGA low-temperature poly-Si TFT-LCD with integrated digital data drivers,” in SID Symp. Dig. Tech. Papers, 1998, vol. 29, pp. 879–882.

[3] V. Rana, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker, “High performance P-channel single-crystalline Si TFTs fabricated inside a location-controlled grain by-Czochralski process,” IEICE Trans. Electron., vol. E87-C, pp. 1943–1946, Nov. 2004.

[4] P. C. van der Wilt, B. D. van Dijk, G. J. Bertens, R. Ishihara, and C. I. M. Beenakker, “Formation of location-controlled crystalline islands using substrate-embedded-seeds in excimer-laser crystallization of sil-icon films,” Appl. Phys. Lett., vol. 72, no. 12, pp. 1819–1822, Sep. 2001. [5] V. Rana, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker, “Dependence of single-crystalline Si thin-film transistor characteristics on the channel position inside a location-controlled grain,” IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2622–2628, Dec. 2005.

[6] W. Fang, A. van Genderen, R. Ishihara, R. Vikas, N. Karaki, Y. Hiroshima, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker, “Automated digital circuits design based on single-grain Si TFTs fabricated through the-Czochralski (grain filter) process,” in AM-FPD Dig. Tech. Papers, 2006, pp. 47–50.

[7] N. Saputra, M. Danesh, A. Baiano, R. Ishihara, J. R. Long, J. W. Met-selaar, C. I. M. Beenakker, N. Karaki, Y. Hiroshima, and S. Inoue, “Single-grain Si thin-film transistors for analog and RF circuits,” in Proc. ESSDERC, 2007, pp. 107–110.

[8] J. L. Botrel, O. Savry, O. Rozeau, F. Templier, and J. Jomaah, “Polysil-icon high frequency devices for large area electronics: Characteriza-tion, simulation and modeling,” Thin Solid Films, vol. 515, no. 19, pp. 7422–7427, 2007.

[9] J.-H. Ahn, H.-S. Kim, K. J. Lee, Z. Zhu, E. Menard, R. G. Nuzzo, and J. A. Rogers, “High-speed mechanically flexible single-crystal silicon thin-film transistors on plastic substrates,” IEEE Electron Device Lett., vol. 27, no. 6, pp. 460–462, Jun. 2006.

[10] M. He, R. Ishihara, J. W. Metselaar, and C. I. M. Beenakker, “h100i-textured self-assembled square-shaped polycrystalline silicon grains by multiply shots excimer-laser crystallization,” J. Appl. Phys., vol. 100, pp. 1–5, 2006.

[11] M. He, R. Ishihara, E. J. J. Neihof, Y. van Andel, H. Schellevis, J. W. Metselaar, and K. Beenakker, “Large polycrystalline silicon grains pre-pared by excimer-laser crystallization of sputtered amorphous silicon film with process temperature at 100 C,” Jpn. J. Appl. Phys., vol. 46, no. 3B, pp. 1245–1249, 2007.

[12] Y. Hiroshima, C. Iriguchi, R. Ishihara, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker, “Single-grain Si TFTs fabricated by the-Czochralski process on a large glass substrate,” in Tech. Dig. 2004 Int. Workshop on Active-Matrix Liquid-Crystal Displays, Tokyo, Japan, Jul. 2004, pp. 307–308.

SAPUTRA et al.: ASSESSMENT OF µ-CZOCHRALSKI, SINGLE-GRAIN SILICON THIN-FILM TRANSISTOR TECHNOLOGY 1575

[13] R. Ishihara, D. Danciu, F. Tichelaar, M. He, Y. Hiroshima, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker, “Microstruc-ture characterisation of location-controlled Si-islands crystallised by excimer laser in the-Czochralski (grain filter) process,” J. Crystal Growth, vol. 299, no. 2, pp. 316–321, 2007.

[14] R. Ishihara, M. He, V. Rana, Y. Hiroshima, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker, “Electrical property of coincidence site lattice grain boundary in location-controlled Si island by excimer-laser crystallization,” Thin Solid Films, vol. 487, no. 1–2, pp. 97–101, 2005.

[15] C. Iriguchi, S. Inoue, T. Shimoda, A. Nobari, and T. Iba, “0.5m-gate poly-Si TFT fabrication on large glass substrate,” in AMLCD Dig. Tech. Papers, 2003, pp. 9–12.

[16] G. Yang, S. Hur, C. Kim, and C. Han, “A physical based analytical turn on model of polysilicon thin-film transistors for circuit simulation,” in IEEE Int. Electron Device Meeting Tech. Dig., 1995, pp. 953–956. [17] M. Shur, M. Hack, and Y. Byun, “Circuit model and parameter

extrac-tion technique for polysilicon thin-film transistors,” in Proc. 2nd Int. Semiconductor Device Research Symp., 1993, pp. 165–168. [18] BSIMSOI Model. Dept. EECS, Univ. California, Berkeley [Online].

Available: www-device.eecs.berkeley.edu /~bsimsoi

[19] J. Y. W. Seto, “The electrical properties of polycrystalline silicon films,” J. Appl. Phys., vol. 46, no. 12, pp. 5247–5254, Dec. 1975. [20] A. Baiano, R. Ishihara, N. Karaki, S. Inoue, W. Metselaar, and K.

Beenakker, “DC modeling of single-grain Si TFTs using BSIMSOI,” in Int. TFT Conf. Dig. Tech. Papers, 2007, pp. 200–203.

[21] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, no. 2, pp. 1193–1202, Feb. 1982.

[22] P. J. van Wijnen, H. R. Claessen, and E. A. Wolsheimer, “A new straightforward calibration and correction procedure for ’on wafer’ high frequency S-parameter measurements (45 MHz–18 GHz),” in IEEE Bipolar Circuits Technol. Meeting (BCTM) Tech. Dig., 1987, pp. 70–73.

[23] H. P. Tuinhout, “Electrical characterisation of matched pairs for evalu-ation of integrated circuit technology,” Ph.D. dissertevalu-ation, Delft Univ. of Technol., Delft, The Netherlands, 2005.

[24] H.-K. Lim and J. G. Fossum, “Threshold voltage of thin-film sil-icon-on-insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. 30, no. 10, pp. 1244–1251, Oct. 1983.

[25] M. Roser, S. R. Clayton, P. R. de la Houssaye, and G. A. Garcia, “High mobility fully depleted thin-film SOS MOSFET’s,” IEEE Trans. Elec-tron Devices, vol. 39, no. 11, pp. 2665–2666, Nov. 1992.

[26] A. A. Owusu, M. D. Jacunski, M. S. Shur, and T. Ytterdal, “Spice model for the kink effect in polysilicon TFTs,” Proc. Electrochem. Soc., vol. 96-23, pp. 289–295, 1997.

[27] A. Lewis and R. Bruce, “Circuit design and performance for large area electronics,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1990, pp. 222–223.

[28] R. J. Baker, CMOS Circuit Design, Layout and Simulation. New York: Wiley Interscience, 2005, pp. 711–770.

[29] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effect of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996.

[30] D. Dzahini and H. Ghazlane, “Auto-zero stabilized CMOS amplifiers for very low voltage or current offset,” in IEEE Nuclear Science Symp. Conf. Record, 2003, vol. 1, pp. 6–10.

[31] F. Krummenacher, R. Vafadar, A. Ganesan, and V. Valence, “A high-performance autozeroed CMOS opamp with 50V offset,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1997, pp. 350–351.

[32] N. Saputra, M. Danesh, A. Baiano, R. Ishihara, S. Inoue, N. Karaki, and J. R. Long, “Analog and RF design using the-Czochralski single grain TFT technology,” presented at the ProRISC Conf., Veldhoven, The Netherlands, Nov. 2007.

[33] G. C. M. Meijer, G. Wang, and F. Fruett, “Temperature sensors and voltage references implemented in CMOS technology,” IEEE Sensors J., vol. 1, no. 3, pp. 225–234, Oct. 2001.

[34] S. Adriaensen, V. Dessard, and D. Flandre, “A voltage reference com-patible with standard SOI CMOS process and consuming 1 pA to 50 nA from room temperature up to 300 C,” in IEEE Int. SOI Conf. Tech. Dig., 2002, pp. 130–131.

[35] M. R. T. Mofrad, “Monolithic, low temperature fabrication of three-dimensional ICs,” M.Sc. thesis, Faculty of EEMCS, Delft Univ. of Technol., Delft, The Netherlands, 2007.

Nitz Saputra (S’07) was born in Bandung,

In-donesia, in 1980. He received the B.Eng. degree from Nanyang Technological University, Singapore, in 2002, and the M.Sc. degree from Delft University of Technology, Delft, The Netherlands, in 2005. He is currently pursuing the Ph.D. degree from Delft University of Technology.

From 2002 to 2003, he was an analog design engi-neer with Marvell Asia, Singapore, where he devel-oped high-speed and low-noise preamplifiers for data storage applications. In 2005, he was an intern stu-dent with Philips Semiconductor, Tempe, AZ, where he developed low-power successive array approximation ADCs. His current research interests include analog and RF circuit design.

Mina Danesh (S’93–M’99–SM’05) received the

B.Eng. degree from Concordia University, Montreal, Canada, in 1996, and the M.A.Sc. degree from the University of Toronto, Toronto, Canada, in 1999, and is currently working toward the Ph.D. degree at the Delft University of Technology, Delft, The Netherlands, all in electrical engineering. She received the M.B.A. degree from HEC Montreal, Montreal, Canada, in 2004.

From 1999 to 2005, she was an RF Design Engi-neer with the Microwave Communications Division, Harris Corporation, Montreal, Canada, where she developed digital microwave radio transceivers for broadband wireless access and point-to-point products. During the summer of 2001, she was a Visiting Research Scientist at the Univer-sity of Ulm, Ulm, Germany, where she designed high-frequency SiGe MMICs. Since 2005, she has been an Engineering Researcher at the Delft University of Technology, involved in ultra-low-power wireless microsystems. Her current re-search interests include wireless communications, RF/MMIC design, and wire-less system integration.

Alessandro Baiano was born in Napoli, Italy, in

1979. He received the M.S. degree (cum laude) in electronics engineering from the University of Naples Federico II, Naples, Italy, in 2005, after com-pleting his Master thesis within the Department of Microelectronics and Information Technology of the Royal Institute of Technology, Stockholm, Sweden, on analysis of deep-submicron fully depleted sil-icon-on-insulator MOSFETs. In October 2005, he joined the Faculty of Electrical Engineering, Math-ematics and Computer Science, Delft University of Technology, Delft, The Netherlands, where he is currently pursuing the Ph.D. degree within the Laboratory of Electronic Components, Technology and Materials of Delft Institute of Microsistems and Nanoelectronics (DIMES).

His research interests include fabrication, characterization and modeling of high-performance single-grain thin-film transistors and circuit applications.

Ryoichi Ishihara received the B.E., M.E., and Ph.D.

degrees from the Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan, in 1991, 1993, and 1996, respectively. In the graduate school, he performed research on amorphous-Si and polycrystalline-Si TFTs with low-temperature CVD of SiN and excimer-laser crystallization of Si films.

Since April 1996, he has been working for Delft Institute of Microsystems and Nanoelectronics (DIMES), Delft University of Technology, Delft, The Netherlands. There he has initiated a new research field of single-grain Si TFTs. Currently, he is an Associate Professor in the Faculty of Electrical Engineering. He is in charge of a number of projects related to thin-film transistor technologies for flexible displays and 3-D ICs.

John R. Long (M’83) received the B.Sc. degree

in electrical engineering from the University of Calgary, Canada, in 1984, and the M.Eng. and Ph.D. degrees in electronics from Carleton University, Ottawa, Canada, in 1992 and 1996, respectively.

He was employed for 10 years by Bell-Northern Research, Ottawa (now Nortel Networks R&D), in-volved in the design of ASICs for Gb/s fiber-optic transmission systems, and from 1996 to 2001 as an Assistant, and then Associate Professor, at the Uni-versity of Toronto, Toronto, Canada. Since January 2002, he has been Chair of the Electronics Research Laboratory at the Delft Uni-versity of Technology, Delft, The Netherlands. His current research interests in-clude low-power and broadband transceiver circuitry for highly-integrated wire-less applications, energy-efficient wirewire-less sensors, mm-wave integrated elec-tronics, and electronics design for high-speed data communications systems.

Prof. Long currently chairs the RF circuits subcommittee for the 2008 IEEE International Solid-State Circuits Conference (ISSCC), and is a member of the technical program committees for the European Solid-State Circuits (ESS-CIRC) and ICUWB conferences. He is a Distinguished Lecturer for the IEEE Solid-State Circuits Society, and Co-Chair of the 2008 European Microwave IC(EuMIC) in Amsterdam. He is also a former Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and Past General Chair of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). He received the NSERC Doctoral Prize, Douglas R. Colton and Governor General’s Medals for research excellence, and Best Paper Awards from ISSCC in 2000 and 2007, IEEE BCTM 2003, the 2006 RFIC Symposium, and EuMW 2006.

Nobuo Karaki (M’97) received the Ph.D. degree

in electrical engineering and computer science from Kyushu University, Japan.

He is currently a researcher at Frontier Device Research Center, Seiko Epson Corporation, Nagano, Japan. From 1998, he spent 10 years for researching on an ASIC-style asynchronous circuit design technique dedicated to flexible microelectronics featuring low-temperature-processed polysilicon thin-film transistor (LTPS TFT) technology and a surface-free fabrication technique, SUFTLA. He is now researching an asynchronous circuit design technique for enabling ultra-low-power VLSIs based on the deep-submicron process technologies, and 3-D fabrication technologies.

Dr. Karaki is a member of the IEEE Solid-State Circuit Society, ACM, and IEICE.

Satoshi Inoue (M’00–SM’07) received the B.S.

degree in applied physics from Nagoya University, Japan, in 1982. He received the Ph.D. degree in electrical and electric engineering from Tokyo University of Agriculture and Technology, Tokyo, Japan, in 2002.

He joined Toshiba Corporation in 1982, and worked on the research of EEPROMs, DRAMs, and ULSI technology at ULSI Research Center. He joined Seiko Epson Corporation, Nagano, Japan, in 1990, and has been working on the research of TFTs and displays using TFTs at Frontier Device Research Center.

Dr. Inoue is a member of the SID, Japan Society of Applied Physics, and the IEEE Electron Devices Society.