CD22101

Description

CD22101 and CD22102 crosspoint switches consist of 4 x 4 x 2 arrays of crosspoints (transmission gates) with a 4-line to 16-line decoder and 16 latch circuits. Any one of the sixteen crosspoint pairs can be selected by applying the appropriate four-line address, corresponding crosspoints in each array are turned on and off simultaneously. Any number of crosspoints can be turned on simultaneously.

In the CD22101, the selected crosspoint pair can be turned on or off by applying a logic ONE or ZERO, respectively, to the data input, and applying a ONE to the strobe input. When the device is “powered up”, the states of the 16 switches are indeterminate. Therefore, all switches must be turned off by putting the strobe high, data-in low, and then addressing all switches in succession.

The selected pair of crosspoints in the CD22102 is turned on by applying a logic ONE to the K_A(set) input while a logic ZERO is on the K_Binput, and turned off by applying a logic ONE to the K_B(reset) input while a logic ZERO is on the K_Ainput. In this respect, the control latches of the CD22102 are similar to SET/RESET flip-flops. They differ, however, in that the simultaneous application of ONEs to the K_Aand K_Binputs turns off (resets) all crosspoints. All crosspoints in both devices must be turned off as V_DDis applied.

Features

• Low ON Resistance . . . 75Ω (Typ) at V_DD = 12V

• “Built - In” Latched Inputs

• Large Analog Signal Capability . . . . ±V_DD/2

• Switch Bandwidth . . . 10MHz

• Matched Switch Characteristics

∆R_ON = 8Ω (Typ) at V_DD= 12V

• High Linearity - 0.25% Distortion (Typ) at f = 1kHz, V_IN= 5V_P-P, V_DD - V_SS = 10V, and R_L = 1kΩ

• Standard CMOS Noise Immunity

Applications

• Telephone Systems

• PBX

• Studio Audio Switching

• Multisystem Bus Interconnect

Ordering Information

PART NUMBER

TEMP.

RANGE (^oC) PACKAGE PKG. NO.

CD22101E -40 to 85 24 Ld PDIP E24.6

CD22101F -55 to 125 24 Ld CERDIP F24.6

CD22102E -40 to 85 24 Ld PDIP E24.6

February 1999

Pinouts

CD22101 (PDIP, SBDIP)

TOP VIEW

CD22102 (PDIP) TOP VIEW 1

2 3 4 5 6 7 8 9 10 11 12 D

16 17 18 19 20 21 22 23 24

15 14 13

A VDD

VSS

DATA STROBE X1'

Y2' B C X2' Y1'

X4' X3' Y4' Y3'

X2 Y1 Y2 X4 X3 Y4 Y3 X1

1 2 3 4 5 6 7 8 9 10 11 12 D

16 17 18 19 20 21 22 23 24

15 14 13

A VDD

VSS X1' Y2' B C X2' Y1'

X4' X3' Y4' Y3'

X2 Y1 Y2 X4 X3 Y4 Y3 X1 K_A K_B

Functional Diagram

4 X 4 SWITCH

4 X 4 SWITCH 16

16

ADDRESS

CONTROL

OUT (IN)

IN (OUT)

OUT (IN) IN (OUT)

DECODER LATCH

16

CD22101, CD22102

CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory

[ /Title (CD22 101, CD221 02) /Sub- ject (CMO S 4 x 4 x 2 Cross- point Switch with Con- trol Mem- ory) / Author () /Key- words (Har- ris Semi- con- ductor, Tele- com, SLICs, SLACs , Tele- phone, Tele- phony, WLL, Wire- less

OBSOLETE PRODUCT NO RECOMMENDED REPLA

CEMENT Call Central Applications 1-800-442-7747

or email: centapp@harris.com

Absolute Maximum Ratings Thermal Information

Supply Voltage (V_DD) (Referenced to V_SS Terminal) . . . .-0.5 to 20V Input Voltage (All Inputs) . . . -0.5 to V_DD +0.5V Supply Voltage Range

For T_A = Full Package Temperature Range . . . 3V to 18V Input Current (Any One Input) (Note 1) . . . .±10mA Power Dissipation

For T_A = -40^oC to 60^oC (Package Type E) . . . 500mW For T_A = 60^oC to 85^oC

Package Type E) . . . Derate Linearly 12mW/^oC to 200mW For T_A = -55^oC to 100^oC (Package Type D, F) . . . 500mW For T_A = 100^oC to 125^oC

(Package Type D, F) . . . Derate Linearly 12mW/^oC to 200mW Device Dissipation per Output Transistor

For T_A = Full Package Temperature Range (All Types) . . . 100mW

Maximum Junction Temperature . . . 175^oC Maximum Junction Temperature (Plastic Package) . . . 150^oC Maximum Storage Temperature Range . . . -65^oC≤ T_A≤ 150^oC Maximum Lead Temperature (Soldering 10s) . . . 300^oC

Operating Conditions

Temperature Range

Package Type D, F. . . -55^oC≤ T_A≤ 125^oC Package Type E . . . -40^oC≤ T_A≤ 85^oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

PARAMETER SYMBOL

TEST CONDITIONS -55^oC -40^oC 85^oC 125^oC 25^oC

UNITS FIGURE V_DD(V) MAX MAX MAX MAX MIN TYP MAX

STATIC CROSSPOINTS Quiescent Device Current

I_DD (Max) 1 5 5 5 150 150 - 0.04 5 µA

1 10 10 10 300 300 - 0.04 10 µA

1 15 20 20 600 600 - 0.04 20 µA

1 20 100 100 3000 3000 - 0.08 100 µA

On Resistance R_ON (Max) Any Switch V_IS = 0 to V_DD

14 5 475 500 725 800 - 225 600 Ω

15 10 135 145 205 230 - 85 180 Ω

- 12 100 110 155 175 - 75 135 Ω

16 15 70 75 110 125 - 65 95 Ω

∆ON Resistance ∆RON Between Any Two Switches

5 - - - 25 - Ω

10 - - - 10 - Ω

12 - - - 8 - Ω

15 - - - 5 - Ω

OFF Leakage Current I_L (Max) All Switches OFF, V_IS= 18V

4 18 ±1000 - ±1 ±100

(Note 2) nA

STATIC CONTROLS

Input Low Voltage V_IL (Max) OFF Switch I_L < 0.2µA 5 1.5 - - 1.5 V

10 3 - - 3 V

15 4 - - 4 V

Input High Voltage V_IH (Min) ON Switch See R_ON Characteristic

5 3.5 3.5 - - V

10 7 7 - - V

15 11 11 - - V

Input Current I_IN (Max) Any Control V_IN = 0, 18V

2 18 ±0.1 ±0.1 ±1 ±1 - ±10^-5 ±0.1 µA

NOTES:

1. Maximum current through transmission gates (switches) = 25mA.

2. Determined by minimum feasible leakage measurement for automatic testing.

Electrical Specifications

PARAMETER SYMBOL

TEST CONDITIONS

MIN TYP MAX UNITS FIGURE

f_IS (kHz)

R_L (kΩ)

V_IS (V) (Note 3)

V_DD (V) DYNAMIC CROSSPOINTS

Propagation Delay Time,

(Switch ON) Signal Input to Output

t_PHL, t_PLH 5 - - 5 5 - 30 60 ns

- 10 10 10 - 15 30 ns

15 15 - 10 20 ns

C_L = 50pF; t_R , t_F = 20ns Frequency Response (Any Switch

ON)

f_3dB 19 1 1 5 10 - 40 - MHz

Sine Wave Input,

Sine Wave Response (Distortion) THD - 1 1 2.5 5 - 1 - %

1 1 5 10 - 0.25 - %

1 1 7.5 15 - 0.15 - %

Feedthrough (All Switches OFF) F_DT 13 1.6 0.6 2 (Note 4) 10 - -96 - dB

Sine Wave Input

Frequency for Signal Crosstalk F_CT 12 - 0.6 1 (Note 4) 10

Attenuation of 40dB

Sine Wave Input

- 2.5 - MHz

Attenuation of 95dB 0.1 kHz

Capacitance:

X_N to Ground C_IS - - - - 25 - pF

Y_N to Ground - - - - 60 - pF

Feedthrough C_IOS - - - - 0.6 - pF

DYNAMIC CONTROLS Propagation Delay Time: High Impedance to High Level or Low Level

t_PZH, t_PZL 6 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 500 1000 ns

Strobe to Output, CD22101 10 - 230 460 ns

15 - 170 340 ns

Data-In to Output, CD22101 t_PZH, t_PZL 7 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 515 1000 ns

10 - 220 440 ns

15 - 170 340 ns

K_A to Output, CD22102 t_PZH, t_PZL - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 500 1000 ns

10 - 215 430 ns

15 - 160 320 ns

Address to Output CD22101, CD22102

t_PZH, t_PZL 8 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 480 960 ns

10 - 225 450 ns

15 - 155 300 ns

20log VOS

VIS --- = -3dB

Propagation Delay Time: High Level or Low Level to High Impedance

t_PHZ,t_PLZ 6 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 450 900 ns

Strobe to Output, CD22101 10 - 200 400 ns

15 - 135 270 ns

K_B to Output, CD22102 t_PHZ,t_PLZ - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 450 900 ns

10 - 200 400 ns

15 - 130 260 ns

Data-In to Output, CD22101 t_PHZ,t_PLZ - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 450 900 ns

10 - 165 330 ns

15 - 110 220 ns

K_A• K_B to Output, CD22102 t_PHZ,t_PLZ - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 280 560 ns

10 - 130 260 ns

15 - 90 180 ns

Address to Output CD22101, CD22102

t_PHZ,t_PLZ 8 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 425 850 ns

10 - 190 380 ns

15 - 130 260 ns

Minimum Strobe Pulse Width, CD22101

t_W 6 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 260 500 ns

10 - 120 240 ns

15 - 80 160 ns

Address to Strobe Setup or Hold Times, CD22101

t_SU,t_H 9 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - -160 0 ns

10 - -70 0 ns

15 - -50 0 ns

Strobe to Data-In Hold Time, CD22101

t_HHL, t_HLH 10 R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 200 400 ns

10 - 80 160 ns

15 - 60 120 ns

Address to K_Aand K_BSetup or Hold Times, CD22102

t_SU, t_H - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - -160 0 ns

10 - -70 0 ns

15 - -50 0 ns

Minimum K_A• K_B Pulse Width, CD22102

t_W - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 375 750 ns

10 - 160 320 ns

15 - 110 220 ns

Minimum K_A Pulse Width, CD22102 t_W - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 425 850 ns

10 - 175 350 ns

15 - 120 240 ns

Electrical Specifications

PARAMETER SYMBOL

TEST CONDITIONS

MIN TYP MAX UNITS FIGURE

f_IS (kHz)

R_L (kΩ)

V_IS (V) (Note 3)

V_DD (V)

Functional Block Diagram

Minimum K_B Pulse Width, CD22102 t_W - R_L = 1kΩ, C_L = 50pF, t_R, t_F = 20ns

5 - 200 400 ns

10 - 90 180 ns

15 - 70 140 ns

Control Crosstalk, Data-In, Address or Strobe to Output

11 100 10 5 - 75 - mV_PEAK

Square Wave Input = 5V, t_R, t_F = 20ns, R_S = 1kΩ

Input Capacitance C_IN Any Control Input - - 5 7.5 pF

NOTES:

3. Peak-to-peak voltage symmetrical about , unless otherwise specified.

4. RMS.

Electrical Specifications

PARAMETER SYMBOL

TEST CONDITIONS

MIN TYP MAX UNITS FIGURE

f_IS (kHz)

R_L (kΩ)

V_IS (V) (Note 3)

V_DD (V)

VDD ---2

SIGNALS IN (OUT) SIGNALS IN (OUT)

SIGNALS OUT (IN)

SIGNALS OUT (IN)

0 1 2 3

7 6 5 4

8

12 13

9 10 11

15 14

Y1

Y2

Y3

Y4 17 16 20 21

19 18 22 15

X1 X2 X3 X4

0’ 1’ 2’ 3’

7’

6’

5’

4’

8’

12’ 13’

9’ 10’ 11’

15’

14’

Y1’

Y2’

Y3’

Y4’

8 9 5 4

6 7 3 10

X1’ X2’ X3’ X4’

16

16 16 16

14 13

CD22102 ONLY

K_A K_B

CD22101 ONLY

STROBE DATA

ADDRESS

D 11

DECODER

2 1 23

C B A

LATCHES (NOTE)

INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK

V_DD

V_SS (NOTE)

(NOTE)

(NOTE)

(NOTE)

(NOTE)

NOTE:

Schematic Diagram

DECODER TRUTH TABLE ADDRESS

SELECT

ADDRESS

SELECT

A B C D A B C D

0 0 0 0 X1Y1 and X1’Y1’ 0 0 0 1 X1Y3 and X1’Y3’

1 0 0 0 X2Y1 and X2’Y1’ 1 0 0 1 X2Y3 and X2’Y3’

0 1 0 0 X3Y1 and X3’Y1’ 0 1 0 1 X3Y3 and X3’Y3’

1 1 0 0 X4Y1 and X4’Y1’ 1 1 0 1 X4Y3 and X4’Y3’

0 0 1 0 X1Y2 and X1’Y2’ 0 0 1 1 X1Y4 and X1’Y4’

1 0 1 0 X2Y2 and X2’Y2’ 1 0 1 1 X2Y4 and X2’Y4’

0 1 1 0 X3Y2 and X3’Y2’ 0 1 1 1 X3Y4 and X3’Y4’

1 1 1 0 X4Y2 and X4’Y2’ 1 1 1 1 X4Y4 and X4’Y4’

23 A

A A

1 B

B B

2 C

C C

11 D

D D

V_SS 12

V_DD

24 D Q

ø ø

0 1 2 3

LATCH

TG TG TG TG

4 5 6 7

TG TG TG TG

8 9 10 11

TG TG TG TG

12 1314 15

TG TG TG TG

15 22 18 19

17 16 20 21

Y4 Y3 Y2 Y1

X4 X3

X2 X1

D

ø ø

p n

ø ø

p n DETAIL OF LATCHES

V_DD V_DD

V_SS

IN

OUT Q

DETAIL OF TRANSMISSION GATES STROBE

13 14

DATA IN

V_DD

V_SS INPUTS PROTECTED

BY COS/MOS PROTECTION NETWORK

TO 15 OTHER LATCHS TO 15 OTHER

NANDS

TO X1’ Y1’

10

(

) (

) (

) (

)

4

(

)

5

(

)

9

(

)

8

(

)

CD22101 A

B C D

A B C D

D

ø ø

Q

R

TO 15 OTHER LATCHES

CD22102

Q TO 15 OTHER

NANDS K_A (SET)

14 13 K_B (RESET)

(NOTE) (NOTE)

(NOTE) (NOTE)

(NOTE)

(NOTE)

(NOTE)

(NOTE)

NOTE:

Metallization Mask Layout

CONTROL TRUTH TABLE FOR CD22101

FUNCTION

ADDRESS

STROBE DATA SELECT

A B C D

Switch ON 1 1 1 1 1 1 15 (X4Y4) and 15’ (X4’Y4’)

Switch OFF 1 1 1 1 1 0 15 (X4Y4) and 15’ (X4’Y4’)

No Change X X X X 0 X X X X X

1 = High Level 0 = Low Level X = Don’t Care

CONTROL TRUTH TABLE FOR CD22102

FUNCTION

ADDRESS

K_A K_B SELECT

A B C D

Switch ON 1 1 1 1 1 0 15 (X4Y4) and 15’ (X4’Y4’)

Switch OFF 1 1 1 1 0 1 15 (X4Y4) and 15’ (X4’Y4’)

All Switches OFF (Note 5)

X X X X 1 1 All

No Change X X X X 0 0 X X X X

1 = High Level 0 = Low Level X = Don’t Care

NOTE:

5. In the event that K_Aand K_Bare changed from levels 1, 1 to 0, 0 K_Bshould not be allowed to go to 0 before K_A, otherwise a switch which was off will inadvertently be turned on.

Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10^-3 inch).

Test Circuits and Waveforms

FIGURE 1. QUIESCENT CURRENT TEST CIRCUIT FIGURE 2. INPUT CURRENT TEST CIRCUIT

FIGURE 3. DYNAMIC POWER DISSIPATION TEST CIRCUIT FOR CD22101AND TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF SWITCHING FREQUENCY

1 2 3 4 5 6 7 8 9 10 11 12

16 17 18 19 20 21 22 23 24

15 14 13 V_SS

V_SS V_DD

V_DD

I_DD

1 2 3 4 5 6 7 8 9 10 11 12

16 17 18 19 20 21 22 23 24

15 14 13 V_SS

V_SS V_DD

V_DD

I_I

MEASURE INPUTS SEQUENTIALLY TO BOTH V_DD AND V_SS CONNECT ALL UNUSED INPUTS TO EITHER V_DD OR V_SS

CLOSE SWITCH S AFTER APPLYING V_DD 1

2 3 4 5 6 7 8 9 10 11 12

16 17 18 19 20 21 22 23 24

15 14 13

2kΩ V_DD

I_D

0.1µF 500µF

S Q₁

C_L

C_L

C_L

C_L

2kΩ V_SS

C_L

C_L C_L

C_L

Q₄

2kΩ Q₃ Q₂ CD4029

CLK Q₁ Q₂ Q₃ Q₄ CLK

2kΩ

V_DD = 15V 10V

5V T_A = 25^oC

SWITCHING FREQUENCY (Hz)

POWER DISSIPATION PER PACKAGE (µW)

10² 10³ 10⁴ 10⁵ 10⁶ 10⁷

10⁵

10⁴

10³

10²

10

C_L = 50pF C_L = 15pF 10V

FIGURE 4. OFF SWITCH INPUT OR OUTPUT LEAKAGE CURRENT TEST CIRCUIT (16 OF 32 SWITCHES)

FIGURE 5. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (SIGNAL INPUT TO SIGNAL OUTPUT, SWITCH ON)

FIGURE 6. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (STROBE TO SIGNAL OUTPUT, SWITCH TURN-ON OR TURN-OFF)

Test Circuits and Waveforms

1 2 3 4 5 6 7 8 9 10 11 12

16 17 18 19 20 21 22 23 24

15 14 13

V_SS

V_DD

I_L SW

ON

V_IS

V_OS

10kΩ 50pF

SW = ANY CROSSPOINT STROBE = DATA - IN = V_DD

V_IS V_OS

V_DD

V_DD t_PLH

t_PHL 0

0

50% 50%

50%

50%

V_IS SW V_OS

1kΩ 50pF V_DD

STROBE DATA-IN

SW = ANY CROSSPOINT

STROBE

V_DD DATA-IN

V_OS

50%

90%

10%

t_S

t_H

t_PZH

0

50% 50% 50%

t_S t_H

V_DD

V_DD 0 0

t_W t_W

t_PHZ

FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (DATA-IN TO SIGNAL OUTPUT, SWITCH TURN-ON TO HIGH OR LOW LEVEL)

FIGURE 8. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (ADDRESS TO SIGNAL OUTPUT, SWITCH TURN-ON OR TURN-OFF)

Test Circuits and Waveforms

V_IS SW V_OS

1kΩ 50pF V_DD

DATA-IN

SW = ANY CROSSPOINT STROBE = V_DD

V_IS SW V_OS

50pF 1kΩ V_DD

V_DD DATA-IN

V_DD

0

V_OS 0

50%

10%

t_PZH

V_DD DATA-IN

V_DD

0

V_OS 0

50%

90%

t_PZL

DATA-IN

V_OS2 ADDRESS

V_OS1

V_IS SW V_OS1

1kΩ 50pF V_DD

ADDRESS = 0

SW = ANY CROSSPOINT STROBE = V_DD

V_IS SW V_OS2

1kΩ 50pF V_DD

ADDRESS = 1

V_DD V_DD 0

0

50%

90%

t_PZH 0

0 V_DD V_DD

10%

50% 50%

t_H t_S

t_PHZ

FIGURE 9. ADDRESS TO STROBE SETUP AND HOLD TIMES FIGURE 10. STROBE TO DATA-IN HOLD TIME t_H, FOR CD22101

FIGURE 11. TEST CIRCUIT AND WAVEFORMS FOR CROSSTALK (CONTROL INPUT TO SIGNAL OUTPUT)

FIGURE 12. TEST CIRCUIT AND TYPICAL CROSSTALK AS A FUNCTION OF FREQUENCY BETWEEN SWITCH CIRCUITS IN THE SAME PACKAGE

Test Circuits and Waveforms

STROBE

DATA

t_SU t_H

ADDRESS

OUTPUT OF SWITCH ADDRESSED

IF SETUP AND HOLD TIMES PROVIDED ARE TOO SHORT, AN UNADDRESSED SWITCH MAY BE TURNED ON OR OFF SIMULTANEOUSLY WITH THE ADDRESSED SWITCH

50%

50%

DATA-IN

t_HLH t_HHL

t_HLH

STROBE

1µs Y2

SET ALL SWITCHES TO OFF INITIALLY APPLY VDD TO ALL X INPUTS AND RETURN ALL Y OUTPUTS TO VSS THROUGH 1kΩ. ADDRESS X1Y2 (ABCD) WITH fIN = 10kHz

1µs 1µs

50%

50%

CONTROLS

10kΩ SW

0 0 V_DD

V_OS CONTROL

75mV 1kΩ

Y (N) X (N)

SW = ANY CROSSPOINT

5µs

ON

600Ω SW

600Ω V_IS

SW = ANY CROSSPOINT

OFF

600Ω SW

600Ω

V_OS

T_A = 25^oC R_S = 600Ω V_IS= 1V_RMS R_L = 600Ω

INPUT SIGNAL FREQUENCY (Hz) CROSSTALK20logV OS VIS---dB=

0 -20 -40 -60 -80 -100 -120

10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ V_DD = 5V

15V 10V -140

FIGURE 13. TEST CIRCUIT AND TYPICAL FEEDTHROUGH AS A FUNCTION OF FREQUENCY (ANY OFF SWITCH)

Typical Performance Curves

FIGURE 14. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT V_DD = -V_SS = 2.5V

FIGURE 15. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT V_DD = -V_SS = 5V

Test Circuits and Waveforms

600Ω ANY

600Ω

V_OS V_IS

ISOLATION (dB) = 20 LOG VOS

VIS

---

OFF SWITCH

INPUT SIGNAL FREQUENCY (Hz) 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ -140

-120

-100

-80

-60

-40

VOS FEEDTHROUGH20log---dB= VIS -20

T_A = 25^oC R_L = 600Ω R_S = 600Ω

7.5V, -7.5V, 3V_RMS

V_DD = 2.5V, V_SS = -2.5V V_IS = 1V_RMS

5V, -5V, 2V_RMS

V_DD = 2.5V, V_SS = -2.5V

SWITCH “ON” RESISTANCE (Ω)

INPUT SIGNAL (V) 300

250

200

150

100

50

0

-2 -1 0 1 2

350

T_A = 125^oC

25^oC

-55^oC

V_DD = 5V, V_SS = -5V

T_A = 125^oC

25^oC

-55^oC

SWITCH “ON” RESISTANCE (Ω)

INPUT SIGNAL (V)

-4 -2 0 2 4

150

125

100

75 50

25

0 175

FIGURE 16. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT V_DD = -V_SS = 7.5V

FIGURE 17. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT T_A = 25^oC

FIGURE 18. TYPICAL SWITCH ON TRANSFER CHARACTERISTICS (1 OF 16 SWITCHES)

FIGURE 19. TYPICAL SWITCH ON FREQUENCY RESPONSE CHARACTERISTICS

T_A = 125^oC

25^oC

-55^oC

SWITCH “ON” RESISTANCE (Ω)

INPUT SIGNAL (V)

-10 -8 -6 -4 0 2 6 8 10

100

75

50

25

0

V_DD = 7.5V, V_SS = -7.5V

-2 4

T_A = 25^oC

SWITCH “ON” RESISTANCE (Ω)

INPUT SIGNAL (V) 300

250 200

150 100

50

0

V_DD = 2.5V, V_SS = -2.5V

±7.5V

±5V

-10 -5 0 5 10

350 400

V_DD = 10V T_A = 25^oC

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V) 10

8

6

4

2

0 2 4 6 8 10

R_L = 1MΩ, 100kΩ, 10kΩ

500Ω

1kΩ

SW V_IS

V_OS R_L STROBE = V_DD DATA-IN = V_DD

V_SS

R_L = 1MΩ

1kΩ 10kΩ

OUTPUT SIGNAL (VOS) RMS (V)

INPUT SIGNAL FREQUENCY (Hz) 2.5

2

1.5

1

0.5

0

10⁵ 10⁶ 10⁷ 10⁸

T_A = 25^oC V_DD = 5V, V_SS = -5V V_IS= 5V_P-P= SINE WAVE 1.77V_RMS

V_DATA-IN = 5V C_L = 15pF

RF VOLTMETER BOONTON RADIO MODEL 91-CA OR EQUIV.

f_IS SW V_OS (RMS)

C_L R_L V_IS

C_IOS = 0.4pF