Bias Temperature Instability Analysis,
Monitoring and Mitigation for
Nano-scaled Circuits
Bias Temperature Instability Analysis,
Monitoring and Mitigation for Nano-scaled
Circuits
Proefschrift
ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,
op gezag van de Rector Magni cus Prof.ir. K.Ch.A.M. Luyben, voorzitter van het College voor Promoties,
in het openbaar te verdedigen
op dinsdag 17 september 2013 om 12:30 uur door
Seyab
Master of Science in Information Technology
Pakistan Institute of Engineering and Applied Sciences (PIEAS), Islamabad geboren te Swat, Pakistan.
Copromotor: Dr.ir. S. Hamdioui
Samenstelling promotiecommissie:
Rector Magni cus voorzitter
Prof.dr. K.L.M. Bertels Technische Universiteit Delft, promotor Dr.ir. S. Hamdioui Technische Universiteit Delft, copromotor Prof.dr. F. Catthoor Katholieke Universiteit Leuven, Belgium Prof.dr. M. Tahoori Karlsruhe Institute of Technology, Germany Prof.dr. G. Leus Technische Universiteit Delft, The Netherlands Prof.dr. G.Q. Zhang Technische Universiteit Delft, The Netherlands Dr.ir. M. Meijer NXP Semiconductor, Eindhoven, The Netherlands Prof.dr. A.J. van der Veen Technische Universiteit Delft, reservelid
This thesis has been submitted in partial ful llment of the requirement for the degree of Doctor of Philosophy at Delft University of Technology (TU Delft), The Netherlands. The research compiled in this thesis was supported by Computer Engineering (CE) Laboratory, TU Delft, Interuniversity Microelectronics Centre (IMEC) Belgium and Higher Education Commission (HEC) Pakistan. I thank them sincerely for their support.
Published and distributed by: Seyab Email: m.seyab.khan@gmail.com ISBN: 978-94-6186-209-9
Subject headings: Semiconductor reliability, Failure mechanisms, Negative Bias Temperature Instability, Failure monitoring, Static mitigation techniques, Dynamic mitigation techniques. Copyright c 2013 by Seyab
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any mean, without permission of the author.
Bias Temperature Instability Analysis, Monitoring
and Mitigation for Nano-scaled Circuits
Seyab
Summary
Technology scaling along with the process developments has resulted in performance improvement of the transistor, which is one of the basic building blocks in almost all the electronic systems. However, the unabated scaling trend following Moore's law surface threats from process variation and reliability degradation. Nowadays, meeting the reliability requirements is more eorts demanding than ever before and needs: (a) understanding the transistor level degradations (b) developing realistic gate level degra-dation models (c) analyzing circuit degradegra-dations under dierent operating conditions and workloads, and (d) developing techniques to monitor and mitigate the degradations both at the design time and during the operation.
In this dissertation, reliability degradation analysis together with the degradation monitoring and mitigation are presented. First, a classi cation of the reliability failures has been presented, while the scope of the dissertation is targeting Bias Temperature Instability (BTI); an intrinsic reliability failure mechanism that degrade transistors during their on states. Time, temperature and oxide eld dependencies of BTI and its impact on transistor parameters such as threshold voltage, carrier mobility and drain current have been investigated analytically and simulated for several technology nodes. Second, the transistor level degradation has been translated into the gate level and a realistic BTI induced gate delay model has been established. At the gate level BTI simulation analysis, various types of gates and inputs have been used to demonstrate the design and input stimuli dependencies of BTI. Third, BTI mechanism has been addressed in both combinational and sequential logic circuits. Initially, BTI impact has been analyzed in several benchmark and synthetic circuits under dierent input stimuli. Thereafter, techniques have been developed to monitor BTI induced circuit delay degradation in both types of circuits. Finally, both static (design time) and dynamic (run time) techniques have been proposed to mitigate BTI in the circuits. Eectiveness and limitations of the techniques have been demonstrated through analysis of several benchmark circuits. Fourth, the combined impact of BTI and partial open defects in Static Random Access Memory (SRAM) decoders has been analyzed. Initially, BTI impact on decoders is analyzed by considering dierent decoder types under various addressing schemes. Thereafter, the impact of partial resistive opens in up and pull-down networks of the decoder is analyzed. Finally, the combined impact of BTI and resistive open is analyzed for various decoders under various addressing schemes.
Bias Temperature Instabiliteit analyse, monitoring
and Mitigation voor nano-schaal Circuits
Seyab
Samenvatting
Het schalen van technologie naast de procesontwikkelingen heeft geleid tot prestatie-verbetering van de transistor, die een van de bouwstenen is in bijna alle elektrische systemen. Echter, de onverminderde trend van schalen dat de wet van Moore volgt stimuleert dreigingen van procesvariatie en betrouwbaarheidsdegradatie mechanismen. Tegenwoordig vereist het voldoen aan de betrouwbaarheidseisen meer inspanningen dan ooit tevoren veeleisender dan ooit en behoeften: (a) het begrijpen van de transistor niveau degradaties (b) het ontwikkelen van realistische gate level degradatie modellen (c) het analyseren van circuit degradaties onder verschillende omstandigheden en work-loads, en (d) het ontwikkelen van technieken om toezicht te houden op de degradaties en het inperken van hen zowel tijdens ontwerpfase als gedurende werking.
In dit proefschrift worden betrouwbaarheid degradatie analyses samen met de degra-datie toezicht en mitigatie gepresenteerd. Ten eerste, is er een classi catie van relia-bility failures gepresenteerd, terwijl de wijdte van het proefschrift gericht is op Bias Temperatuur instabiliteit (BTI); een intrinsieke betrouwbaarheid faalmechanisme dat transistoren verslechterd tijdens hun aan toestand. Tijd, temperatuur en oxide eld afhankelijkheden van BTI en de impact ervan op transistor parameters zoals threshold voltage, carrier mobiliteit en drain current zijn analytisch onderzocht en gesimuleerd voor verschillende technology nodes. Ten tweede is de transistor niveau degradatie vertaald naar gate niveau poort en een realistische BTI geà nduceerde gate delay is vastgesteldk. Op gate niveau BTI simulatieanalyses zijn verschillende soorten gates en inputs gebruikt om het ontwerp en input stimuli afhankelijkheden van BTI te demon-streren. Ten derde, is de BTI mechanisme behandeld zowel voor combinatorische en sequentiele logische schakelingen. Aanvankelijk is de BTI impact geanalyseerd voor ver-schillende benchmark en synthetische circuits voor verver-schillende input stimuli. Daarna zijn technieken ontwikkeld om toezicht te houden op BTI geinduceerde circuit vertrag-ingsdegradatie voor beide soorten circuits. Ten slotte zijn zowel statische (ontwerpfase) als dynamisch (runtime). technieken voorgesteld om BTI in de circuits te verminderen. De eectiviteit en beperkingen van de technieken zijn door middel van analyses en een aantal referentie circuits gedemonstreerd. Ten vierde, zijn de gecombineerde eecten van BTI en partial open defects in Static Random Access Memory (SRAM) decoders geanalyseerd. Aanvankelijk is de BTI impact op decoders geanalyseerd door verschil-lende types decoders onder verschilverschil-lende adresseringsschema's te overwegen. Daarna is de impact van partial resistive opens in de pull-up and pull-down netwerken van de de-coder geanalyseerd. Ten slotte zijn de gecombineerde eecten van BTI en resistive open geanalyseerd voor verschillende decoders onder verschillende adresseringsschema's.
Acknowledgments
This dissertation is not only a result of hard work, perseverance and continuous eorts in the past several years, but also encouragement, cooperation and support from many people. I would like to take this opportunity to acknowledge them.
This work was sponsored by Higher Education Commission (HEC) Pakistan, Com-puter Engineering (CE) group, TU Delft and Interuniversity Microelectronics Centre (IMEC) Belgium. I acknowledge their support and trust on me.
I would like to express my utmost gratitude to my adviser Dr.ir. Said Hamdioui, who nourished me to become an independent researcher. Said kept me progressing even when I had less con dence on myself. He encouraged me to critically analyze scienti c issues, educated me the art of precise evaluation of scienti c and non-scienti c problems. Besides that he coached me to acknowledge eorts of the scienti c community and taught me the skills to introduce novel solutions to solve problems. His inexorable dedication to research, sincerity and attaining perfection earned my admiration.
I would like to specially thank to my promotor Prof.dr. Koen Bertels and members of the examining committee for devoting their precious time to scrutinize my thesis, and for some of them, their travel to Delft for the pubic defense of this dissertation. Moreover, I would like to thank the reliability group at IMEC, Leuven Belgium; especially, Prof. Francky Catthoor, Praveen Raghavan, Ben Kaczer and Halil Kukner. Thanks for the hospitality, providing the models, designs, and tools.
Furthermore, I like to thank my past and present o ce friends: Kazeem, Zaidi, Christos, Mottaqiallah, Mafalda and Innocent who made me learn about dierent re-search topics and dierent cultures. Many thanks to CE friends: Yao, Mihai, Changlin, Marius, George, Askhan, Arash, Ghazaleh, Andrew just to name a few. Special thanks to Mottaqiallah (khpal kaar kawa) for translating my abstract and propositions into Dutch.
Thanks to Lidwina Tromp for her supporting role in the administrative matters dur-ing my stay. Additionally, HEC, NUFFIC and CICAT provided their help in various administrative matters. I would like to thank sta in these organizations for their help, in particular Mrs. Faryal Nosheen, Mrs. Franca Post and Mrs. Loes Minkmen. Special thanks to Bert Meijs, Erik de Vries and Eef Hartmen for providing a exible and excel-lent working environment for my research. I am special thankful to the Dutch society and heartedly admire their punctuality and sincerity towards work. My recognitions also goes to the e cient tra c management system that made cycling fun on the roads.
During my stay in Delft, I was surrounded by many Pakistani friends in the past and present. Although it is not possible for me to name them all. I extend my special thanks to Laiq, Hamayun, Mehfooz, Nadeem, Zubair, Tariq, Umer Altaf, Aqeel, Faisal, Imran, Fakhar, Hamid, Iftikhar, Cheema, Bilal, Usama, Umer Ijaz, Hannan, Atif, Sajjad and Faheem. I am also thankful to my friends in Leuven especially: Shahab, Shahid, Khurram, Rashid and Ahmad khan. Our weekends in Delft and Leuven would have been boring without my cricket playing Pakistani and Indian friends. I am thankful to them who made the time unforgettable in both places.
Last but not the least, comes my family. Death is quite ruthless that takes our beloveds away from us but life is merciful that gifts us their memories. I am always surrounded by the love of my patient mother and cherished father. I cannot express the feelings better than Shelly did:
Music, when soft voices die, Vibrates in the memory; Odours, when sweet violets sicken, Live within the sense they quicken. Rose leaves, when the rose is dead, Are heaped for the beloved's bed; And so thy thoughts, when thou art gone,
Love itself shall slumber on.
P.B. Shelly I am thankful to all my family members for their love and respect. I am really indebted to the care and vision of my siblings who always stood with me and motivated me in the time of sorrow and happiness. I am very delighted to see youngsters in my family who always try to outshine each other but Za hum la buda na yama. I am thankful to my wife for her patience during my study. Without her love and support it would have been troublesome to complete my study. I still have to learn more about her simplistic approach towards life. I also want to extend my thanks to the family of my wife for love and support.
Delft Seyab
Contents
1 Introduction 1
1.1 Reliability Philosophy . . . 2
1.2 Reliability Research Challenges . . . 3
1.3 Research Contributions. . . 5
1.4 Thesis Organization . . . 7
2 Reliability Failure Mechanisms 9 2.1 MOS Transistors . . . 10
2.2 Reliability Failures Classi cation . . . 11
2.2.1 Intrinsic failures . . . 11
2.2.2 Extrinsic failures . . . 13
2.3 Intrinsic Failure Mechanisms. . . 14
2.3.1 Transistor failure mechanisms . . . 15
2.3.2 Interconnect failure mechanisms. . . 22
2.4 Extrinsic Failure Mechanisms . . . 24
2.4.1 Soft errors . . . 24
2.4.2 Latchup . . . 26
2.5 Summary . . . 28
3 Bias Temperature Instability Modeling and Analysis 29 3.1 Brief Notes from History . . . 30
3.2 BTI Mechanism . . . 30
3.2.2 Recovery phase . . . 32
3.3 BTI Dependencies . . . 33
3.3.1 Time dependence . . . 33
3.3.2 Temperature dependence . . . 36
3.3.3 Technology dependence . . . 40
3.4 Impact on Transistor Parameters . . . 41
3.4.1 Threshold voltage increment . . . 41
3.4.2 Carrier mobility reduction . . . 42
3.4.3 Drain current reduction . . . 44
3.5 Summary . . . 46
4 Gate Level BTI Analysis 47 4.1 BTI Induced Gate Delay Model . . . 48
4.2 Analysis Framework and Experiments . . . 49
4.2.1 Analysis framework. . . 49
4.2.2 Experiments. . . 51
4.3 Design Dependencies Results . . . 52
4.3.1 Gate type . . . 52
4.3.2 Stress location . . . 55
4.3.3 Drive strength . . . 56
4.4 Input Stimuli Dependencies Results. . . 57
4.4.1 Duty cycle. . . 57
4.4.2 Frequency . . . 59
4.5 BTI and Parameter Variations . . . 60
4.5.1 Parameter variations . . . 60
4.5.2 BTI and parameter variations . . . 63
4.6 Power Degradation . . . 64
4.7 Summary . . . 66
5 BTI Impact on Combinational Circuits 67 5.1 Circuit Level BTI Model . . . 68
Contents vii
5.2 BTI Impact Analysis . . . 72
5.2.1 Analysis framework and experiments . . . 73
5.2.2 Circuit topology dependence . . . 73
5.2.3 Input stimuli dependence . . . 75
5.3 BTI Monitoring . . . 77
5.3.1 BTI monitoring concept . . . 77
5.3.2 BTI monitoring scheme . . . 78
5.3.3 Transition time comparator . . . 79
5.3.4 Time-to-voltage converter . . . 81 5.3.5 Control circuit . . . 82 5.4 BTI Mitigation . . . 83 5.4.1 Static technique . . . 83 5.4.2 Dynamic technique . . . 89 5.5 Summary . . . 94
6 BTI in Sequential Logic Circuits 95 6.1 BTI Impact Analysis . . . 96
6.1.1 Sequential logic circuits . . . 96
6.1.2 Analysis framework and experiments . . . 97
6.1.3 Experimental results and analysis . . . 98
6.2 BTI Monitoring . . . 100
6.2.1 Monitoring concept. . . 100
6.2.2 Monitor implementation . . . 101
6.3 BTI Tolerance. . . 103
6.3.1 Proposed technique. . . 103
6.3.2 Case study and analysis . . . 105
6.4 Summary . . . 108
7 BTI Impact on SRAM Decoder 109 7.1 SRAM Decoder . . . 110
7.1.2 Two stage decoder . . . 112
7.2 Analysis Framework and Experiments . . . 113
7.2.1 Analysis framework. . . 113
7.2.2 Performed experiments . . . 113
7.3 NBTI/PBTI Impact on the Decoders . . . 114
7.3.1 Wordline delay degradation . . . 114
7.3.2 Transistor location dependency . . . 116
7.3.3 Decoder scaling and BTI impact . . . 116
7.3.4 Workload dependency . . . 117
7.3.5 Leakage current degradation. . . 120
7.3.6 Combined BTI impact on SRAM decoder . . . 121
7.4 Resistive Defects in the Decoders . . . 123
7.4.1 Inside Pull-up network impact. . . 124
7.4.2 Inside pull-down network impact . . . 125
7.5 BTI and Resistive Defect Impact on SRAM Decoder . . . 125
7.6 Summary . . . 128
8 Conclusion and Future Work 129 8.1 Conclusion of the Chapters . . . 130
8.2 Thesis Contribution . . . 131
8.3 Topics for Future Research. . . 133
Bibliography 135
List of Figures
2.1 Schematic cross section of an NMOS transistor. . . 10
2.2 Schematic icons of NMOS and PMOS transistors . . . 11
2.3 Reliability failures classi cation . . . 12
2.4 Intrinsic failures classi cation . . . 12
2.5 Dierent type of bonds inside the silicon and the oxide layer . . . 13
2.6 Extrinsic failures classi cation . . . 14
2.7 Bias Temperature Instability mechanism inside a MOS transistor . . . . 15
2.8 Random Telegraph Noise mechanism . . . 17
2.9 Time dependent dielectric breakdown mechanism inside the MOS oxide layer . . . 18
2.10 Hot Carrier Injection mechanism . . . 21
2.11 Electromigration mechanism . . . 23
2.12 Soft error mechanism . . . 25
2.13 Parasitic thyristor inside a CMOS structure . . . 26
3.1 Schematic view of (a) Stress phase: Si-H bond breaking, H and H2 dif-fusion toward gate (b) Relaxation phase: H and H2 diusion toward the silicon-oxide interface and ≡Si- bond annealing . . . 31
3.2 (a) Interface traps at dierent stress times (b) Interface traps under static and dynamic input stresses . . . 34
3.3 Temperature variation in microprocessor for 16sec [64] . . . 36
3.4 (a) Equivalent time for diusion variation due to temperature changes in stress phase of 200 sec. (b) Equivalent time for H-to-H2 variation due to temperature changes in stress phase of 200 sec. . . 39
3.5 Interface traps density (NIT/m2) in dierent technologies at dierent
temperatures after 108 seconds stress . . . 41
3.6 Threshold voltage increments due to NBTI (a) at dierent temperatures (b) in various MOS technologies . . . 43
3.7 (a) Mobility degradation in 90nm PMOS transistor, (b) Percent mobility degradation in dierent technology nodes at various temperatures . . . . 44
3.8 (a) Saturation current reduction in 90nm PMOS transistor, (b) Percent current degradation in dierent technology nodes at various temperatures 45
4.1 Schematics of the BTI and parameter variations analysis framework . . 49
4.2 (a) BTI induced ∆Vth of PMOS and NMOS transistors as a function of
time (b) Inverter delay increments (∆D) due to NBTI and PBTI . . . . 50
4.3 (a) Transistor organization in a NOR gate and percent delays of the gate due to NBTI and PBTI (b) Transistor organization in a NAND gate and percent delays of the gate due to NBTI and PBTI . . . 53
4.4 Transistor organization in a complex gate implementing A.(B + C) + D.E function and percent delay (rising and falling output transition time in-crement) of the complex gate due to NBTI and PBTI . . . 54
4.5 (a) Percent delay increment of due to NBTI induced ∆Vth in transistor
P1 or P2 of Fig. 4.3(a), (b) Percent delay increment due to PBTI induced
∆Vth in transistor N1 or N2 of Fig. 4.3(a) . . . 55
4.6 Rising and falling transition delay increments of an inverter with dierent drive strengths . . . 57
4.7 (a) Percent delay increments of NOR due to NBTI and PBTI at 20%, 50% and 80% input duty cycles (b) Percent delay increments of NAND due to NBTI and PBTI at 20%, 50% and 80% input duty cycles . . . . 58
4.8 BTI induced delays in INV, NOR and NAND gates at dierent frequen-cies and identical duty cycles . . . 59
4.9 BTI and parameter variations in MOS transistors . . . 60
4.10 (a) Variations in temperature of a gate (b) Variation in the process pa-rameter (PMOS length) of NOR gate (c) Percent delay variation in the NOR gate under temperature variation (d) Percent delay variation in the NOR gate under process parameter variations . . . 62
List of Figures xi
4.12 (a) Percent delay variation of a NOR gate under BTI and parameter variations . . . 64
4.13 Static power reduction in as a function of time . . . 65
5.1 An example circuit to illustrate correlation of BTI impact among gates in a circuit. . . 68
5.2 (a) ∆Vth γ values, (b) ∆DintY of inverter Y with no degradation in the
preceding inverter X . . . 70
5.3 (a) ∆τoX due to NBTI induced VthX at γ=50% (b) ∆DfedY variation
with time at γ=50% . . . 71
5.4 (a) Schematics of C17 ISCAS-85 benchmark circuit,(b) ∆DRise∆DFallof
gates in the benchmark circuit with γ=50% at the primary inputs. . . . 74
5.5 Variation in the critical path delay of C17 benchmark circuit for dierent activity factors at the inputs. . . 76
5.6 (a) Trise of a gate with BTI and without NBTI (b) BTI monitoring by
comparing Vgoutwith reference voltages Vref1 and Vref2. . . 77
5.7 (a) Block diagram of the proposed BTI monitoring scheme that compares gate output with two reference voltages (b) Timing diagram of BTI monitor 78
5.8 Schematic of transition time comparator . . . 79
5.9 (a) Low-to-high transitions of TTC1 and TTC2; Active high duration of XOR without and (b) with NBTI . . . 80
5.10 (a) Schematics of TVC, (b) Output characteristics of TVC . . . 81
5.11 Stat diagram of the control circuit . . . 82
5.12 Directed Acyclic Graph (DAG) of C17 ISCAS-85 benchmark circuit. . . 84
5.13 (a) Scaling factors for unconstrained sizing of the C17 ISCAS-85 bench-mark circuit (a) percentage delay increment of gates in C17 ISCAS-85 benchmark circuit after transistor unconstrained sizing . . . 87
5.14 (a)Scaling factors for constrained sizing of the C17 ISCAS-85 benchmark circuit (a) percentage delay increment of gates in C17 ISCAS-85 bench-mark circuit after transistor optimal sizing . . . 88
5.15 (a) Schematic of the self adjusting threshold voltage scheme (b) The modi ed Vbb due to the TVC output (Vout) variation (c) Trise and Tfall
increments with the SATV. . . 91
5.16 (a) Samples of Osc_Ctr and Osc_F req waveforms (b) Frequency degra-dation under, no BTI, BTI and BTI with DfR techniques . . . 92
5.17 Leakage current reduction under: no BTI, BTI, and BTI with DfR tech-niques . . . 93
6.1 Schematics of a synthetic pipeline circuit . . . 98
6.2 NBTI induced delay distribution among four stages of the circuit . . . . 99
6.3 BTI monitoring circuit (a) High level view of BTI monitor, (b) Signal waveforms without BTI in the CLC (c) Signal waveforms with BTI in the CLC . . . 101
6.4 Schematics of BTI monitoring circuit with BTI Delay Detector (BDD), C-element and the Keeper circuit . . . 101
6.5 Signal waveforms of the BTI monitor for (a) NDD without considering BTI in the CLC, (b) NDD with BTI in the CLC, (c) C-element and Keeper circuit . . . 102
6.6 Simulation waveforms of the BTI monitor (a) without considering BTI in CLC, (b) with considering BTI in CLC . . . 103
6.7 A stage delay with (a) maximum allowable delay of the CLC and FF, (b) Time borrowing by a CLC using setup margin of FF in the next stage104
6.8 Schematic of Time borrowing technique: (a) Master slave ip op with a Specialized Clocking Scheme, (b) Specialized Clocking Scheme for the master latch . . . 104
6.9 Signal waveforms of the time borrowing: (a) Clock to the master latch without error indication of monitor, (b) Clock to the master latch with error indication of monitor . . . 105
6.10 Comparison of time borrowing with; Vdd reduction [13] , Temperature
reduction [13] and Gate over-sizing [119] techniques . . . 106
6.11 Area and power overheads comparisons of the proposed technique with other BTI monitoring and tolerating approaches (Vdd reduction [13] ,
Temperature reduction [13] and Gate over-sizing [119] ) . . . 107
7.1 Functional model of SRAM system . . . 110
7.2 Schematic view of (a) Single stage static decoder (b) Single stage Dy-namic decoder (c) Two stage static decoder . . . 111
7.3 Wordline activation and de-activation delays in the single stage static decoder . . . 112
7.4 Delay degradation of single stage static decoder under (a) NBTI only (b) PBTI only . . . 115
List of Figures xiii
7.5 Wordline additional delay due to (a) NBTI induced degradation in Mref1
and Mref3 (b) PBTI induced degradation in Mref2 and Mref4 . . . 116
7.6 (a) Activation and de-activation delays in 4X16, 5X32 and 6X64 decoders (b) BTI impact on the decoders . . . 117
7.7 NBTI induced mean delay in single stage static and dynamic, and two stage static decoders . . . 118
7.8 PBTI induced mean delay in single stage static and single stage dynamic, and two stage static decoder . . . 119
7.9 NBTI impact on (a) Leakage current degradation (b) Overall power degradation . . . 120
7.10 Bias temperature instability (both NBTI and NBTI) impacts on wordline activation and de-activation of single stage static decoder . . . 121
7.11 BTI induced mean delay in all decoders under dierent addressing schemes122
7.12 Resistive defects in the pull-up and the pull-down networks of single stage static decoder . . . 124
7.13 (a) Impact of resistance in the pull-down network (b) Impact of resistance in the pull-up network (c) Impact of the variable resistances in the pull-up and the pull-down networks . . . 125
7.14 Impact of the variable resistances in the pull-up and the pull-down networks126
List of Tables
4.1 Inverter delays at dierent drive strengths . . . 56
4.2 Static power (Watt) in INV, NAND and NOR gates without BTI . . . . 65
5.1 Delays at input gates, output gates and paths in benchmark circuits . . 75
5.2 Area analysis of the proposed techniques for C17 ISCAS-85 benchmark circuit . . . 89
5.3 Area analysis of the proposed techniques for some ISCAS-85 benchmark circuit . . . 89
Chapter 1
Introduction
1.1 Reliability Philosophy 1.2 Research Challenges 1.3 Research Contributions 1.4 Thesis OrganizationReliable operation for the entire operational lifetime under the speci ed conditions is an important aspect of the semiconductor devices. With the ongoing scaling trend in the semiconductor technologies, reliability of the devices is signi cantly threatened. The threat increases further with every newer technology generation. Precise and realistic analysis of the reliability degradation, monitoring the degradation and mitigating it are essential. The main objectives of this dissertation are analyzing the reliability degradation at the transistor, gate and circuit levels; monitoring the degradation during the operation and mitigating the degradation at the circuit level using both static (at the design time) and dynamic (during operation) approaches.
This introductory chapter rst starts with the sources of reliability failures in the semiconductor devices. Second, it describes the reliability research challenges at dier-ent levels, ranging from transistor to system. Third, it presdier-ents contributions of this dissertation in the eld of reliability failure analysis, monitoring and mitigation. Fi-nally, it presents organization of the dissertation.
1.1 Reliability Philosophy
The relentless developments in the semiconductor technology and its unprecedented impact on human lives are due to the Complementary Metal Oxide Silicon Field Eect Transistor (C-MOSFET); abbreviated as CMOS. The CMOS success is propelled by its: (a) scalability of the physical dimensions and the supply voltage, (b) ease of fabrication and introduction of novel materials, and (c) unabated performance improvements due to scaling and novel designs. These features have resulted in higher CMOS density inside a chip, increased chip functions, reduced cost and power consumption per func-tion. Presently, Ultra Large Scale Integrated (ULSI) circuits that contain from several millions to over several billion transistors can be easily found in numerous appliances. These circuits face a signi cant threat of failure during operation; initiated by the fail-ure mechanisms rooted deep inside the CMOS devices and/or from the external sources. The more advance the circuit in term of speed or size (in term of the area and com-plexity), the greater the probability of having failure during the operation. From the economical point of view, device failure during operation is not a viable option, hence pondering on the lifetime reliability during the design and operation is an important aspect of CMOS based semiconductor devices. Below, we will describe impacts of the above mentioned features on the device reliability.
From the scalability perspective, Moore's law [1] drives scaling of the CMOS de-vices. Under the ideal scaling scenario, in each newer technology generation, the device dimensions (both horizontal and vertical) and the supply voltages scale down by a given factor (k=0.7) the gate delay decreases by 30%, the transistor density doubles and the dynamic power decreases by 50%. However, in the current technology generations, the supply voltage scaling deviates from the ideal scaling scenario due to the reduced oper-ational margin and the quest to maintain the frequency doubling trend in each newer generation [2]. The non-ideal voltage scaling together with the operation at the higher frequency results in an elevated operational stress on the devices [3]. The higher stress initiates and accelerates the failure mechanisms rooted inside the devices. Additionally, the scaled devices become more susceptible to the hazards from the external sources [4]. These hazards deposit charges in the sensitive areas of the devices causing state changes in the storage elements and transients in the logic elements.
From the fabrication point of view, CMOS developments have allowed the manu-facturers to introduce novel materials and advanced processes. However, these devel-opments have surfaced reliability concerns both inside the MOS transistors and the interconnects [3]. For instance, the modi cations in the oxide layer process of the transistors is threatening its core properties of: (a) perfect isolation between gate and channel (b) negligible charges at silicon-oxide interface and (c) zero charges inside the oxide layer. The alterations in the process initiate/accelerate mechanisms of charges
1.2. Reliability Research Challenges 3 generation at the silicon-oxide interface and inside the oxide layer resulting in multiple failure mechanisms, such as Bias Temperature Instability (BTI) [5], Random Telegraph Noise (RTN) [8], Hot Carrier Degradation (HCI) [6] and Time Dependent Dielectric Breakdown (TDDB) [7]. Additionally, copper interconnects and low-k dielectrics are replacing aluminum interconnects and silicon-dioxide dielectrics, respectively. These process developments initiate issues such as stress migration of the copper interconnect and time dependent dielectric breakdown of the low-k dielectric. In conclusion, the process changes/developments cause signi cant increment in the reliability failures per transistor and per unit length of the interconnects.
Finally, for the performance improvements due to smart design and semiconduc-tor technology scaling, the ULSI circuits must continue to be designed with smaller dimensions and operate at higher clock speed. Operation under these conditions lead to a higher operational temperature. The higher temperature threatens reliability by initiating and accelerating electro-chemical reactions in the transistors and intercon-nects. In extreme conditions, physical failures can occur before the speci ed life. In less severe cases, a gradual increase in the reactions will occur leading to the parameters degradation.
In conclusion, keeping in view the above technology trends and the reliability con-cerns; semiconductor reliability research must continually evolve to analyze the causes of the time dependent failures, model the mechanisms leading to the failures and develop appropriate techniques to avoid the failures in the existing and future technologies.
1.2 Reliability Research Challenges
The previous section described the ongoing technology trends and their impacts the semiconductor reliability failures. This section categorically describes the research chal-lenges in the semiconductors reliability at dierent levels such as transistor, gate, circuit and system.
1. Transistor level
High resolution lithography, ion implantation and advancements in the oxide layer process are the forces behind the CMOS developments [9]. Silicon dioxide, scaled to its fundamental limits of ≈1.2nm suers from reliability failures due to charges generated inside the oxide layer and at the silicon-oxide interface. Additionally, High-k dielectrics are introduced in 45nm and smaller technology nodes [10]. As the sources of silicon dioxide failures (i.e., charge generation and their transport) were not adequately
un-derstood [5, 6, 7, 8, 11]; the introduction of high-k dielectrics added further layers of complexities that are yet to be analyzed, understood and mitigated.
2. Gate level
Inside the logical gates (both simple and complex), MOS transistors of dierent types, con gurations and numbers degrade at dierent proportions due to the failure mechanisms named in the previous section. Furthermore, the input, temperature, volt-age dependencies of the mechanisms bring more complexity to the gate level reliability modeling and analysis. A simpli ed gate degradation model has been presented in [12]. However, accurate and generic gate reliability degradation models for several failure mechanisms are still to be established, veri ed through simulation results and indus-trial measurements.
3. Circuit level
Circuit level reliability concerns are more complicated since there are many unre-solved challenges at the transistor and gate levels. As argued by the authors in [13,14], the increasing complexity, workload and variations dependencies make reliability qual-i cation at the circuit level more di cult than that at the lower levels. Furthermore, distribution of the degradation in the gates poses a serious challenge for the design and placement of the e cient reliability monitors in the circuits [6, 15]. Finally, the reliability failures mitigation techniques with the minimum overheads are critical and yet to be investigated.
4. Architecture and system level
System level reliability threat is an accumulation of all the lower (transistor, gate and circuit) levels concerns. The strict performance requirements of the modern com-plex systems dictate thorough analysis to fully understand and quantify the failure mechanisms at the lower levels and propagate their impact to the system level. Ensur-ing the system level reliability must incorporate all the subsystem concerns and develop compact suitable reliability models. Furthermore, formal methodologies must be inves-tigated that incorporate a clear understanding of reliability implications from transistor to the system level. Finally, suitable techniques for reliability failure monitoring and mitigation are essential and must be researched.
1.3. Research Contributions 5
1.3 Research Contributions
The research carried out in the course of this Ph.D project is motivated by the reliability failures encountered by the semiconductor devices, the challenges in characterizing the failures and the quest for techniques to mitigate/tolerate them. Overall, the objectives are to analyze the reliability degradations in the semiconductor devices and ensure re-liability of the devices by proposing several measures at the circuit level. The outcome of this research are published in several scienti c publications; they are described as follows.
1. Survey of state-of-the-art
The state-of-the-art discusses the semiconductor failures by giving a classi cation. The classi cation is based on intrinsic and extrinsic sources of the failures. Further-more, it describes origin of the reliability failure mechanisms along with the strengths and weaknesses of their well known models. A review of the state-of-the-art is given in chapter 2 of this dissertation and presented at Pro-Risc 2008 [16] and Design and Technology of Integrated Systems (DTIS) 2010 [17].
2. Transistor level BTI analysis
The analysis incorporates the impact of time, workload, temperature and voltage on Bias Temperature Instability (BTI) mechanism in the MOS transistors. Furthermore, BTI impact on several transistor parameters such as threshold voltage, carrier mobil-ity and drain current are analytically investigated and simulated for several technology nodes. The investigation and simulations are given in chapter 3 of this dissertation and presented at Design and Test in Europe (DATE) 2010 [18], International On-line Test Symposium (IOLTS) 2010 [19] and Workshop on Design for Reliability (DFR) 2010 [20]. 3. Gate level analysis
Both simple and complex gates are analyzed for BTI and parameter variations im-pacts. BTI analysis focused on the gate type, drive strength and degraded transistor location dependencies. Additionally, it analyzed input stimuli (i.e., duty factor and frequency) dependencies of BTI. Furthermore, the impacts of BTI and parameter vari-ations are combined. The investigvari-ations are given in chapter 4 of this dissertation and presented in Design and Diagnostics of Electronic Circuits and Systems (DDECS) 2012 [21], MEDIAN 2012 [22], Design and Fault Tolerance symposium (DFT) 2012 [23] and
Transaction on Device and Material Reliability (TDMR) [24].
4. Two schemes for BTI mitigation in combinational circuits
Initially, a gate level BTI induced delay model is presented that incorporates degra-dation of transistors inside the gate under consideration and the adjacent gates. The model is used to analyze BTI impact on the combinational circuits. Thereafter, a BTI monitoring scheme that uses transition time of the gate output as a metric is presented. Finally, two schemes employing static (at the design time) and dynamic (during op-eration) approaches are presented to mitigate BTI in the circuits. These outcomes are presented in Chapter 5 of this dissertation and published at Design for Reliability (DFR) 2012 [25], International On-line Test Symposium (IOLTS) 2011 [26], Design and Fault Tolerance symposium (DFT) 2011 [27] submitted to IEEE Transactions on Nan-otechnology [28].
5. A BTI mitigation scheme in sequential logic circuits
Initially, the distribution of BTI induced additional delays in dierent stages of a sequential logic circuit is analyzed. Thereafter, a monitoring scheme is presented that uses the setup time violation of the critical ip op as a metric of BTI impact on the circuit. Finally, a dynamic mitigation scheme that uses the time borrowing concept is presented. The proposed monitoring and the mitigation scheme are given in chapter 6 of this dissertation and presented at International Design and Test Symposium (IDT) 2011 [29].
6. SRAM decoder analysis
The impacts of BTI and partial open defects on the Static Random Access Mem-ory (SRAM) decoders are analyzed. Initially, both static and dynamic decoders are analyzed for BTI impact under dierent addressing schemes. Thereafter, BTI impact is combined with the partial resistive open defects in the pull-up and pull-down net-works of a static decoder. The analysis are given in chapter 7 of this dissertation and presented in International Design and Test Symposium (IDT) 2012 [30], Design for Re-liability (DFR) 2013 [31] and European Test Symposium (ETS) 2013 papers [32].
1.4. Thesis Organization 7
1.4 Thesis Organization
The structure of the thesis is designed to initially guide the reader from a broader view of the reliability failures leading to the thorough understanding of the Bias Temperature Instability (BTI). Thereafter, the state-of-the-art scienti c understanding of BTI at the transistor level is presented, followed by an analysis to quantify its impact at the gate and circuit levels. Furthermore, several approaches to monitor BTI impact at circuit level are presented. Additionally, both static and dynamic techniques are presented to mitigate BTI impact in the circuits. Finally, BTI impact on several decoder designs under dierent addressing schemes are analyzed. A brief review of each chapter is given below to the quickly walk readers through the overall dissertation.
Chapter 2 presents an overview of the semiconductor failures. Initially, it presents a classi cation of the failures on the basis of their sources and locations. Thereafter, it presents physical origin of the failure mechanisms and a review of their well known models published so far.
Chapter 3 presents the underlying physical mechanism of BTI by focusing on the involved sub-processes. Initially, it describes BTI dependencies on dierent physical and electrical parameters. Thereafter, it describes analytical formulation and simulation of BTI impact on several electrical parameters of the MOS transistor.
Chapter 4 analyzes BTI and parameter variations impact on both simple and com-plex logic gates. Initially, it illustrates BTI dependence on the gate type, gate drive strength and location of the degraded transistor in a gate. Thereafter, it describes BTI dependence on the input stimuli parameters such as duty factor and frequency. Finally, it combines the impact of BTI and parameter (process and temperature) variations on the gates.
Chapter 5 deals with BTI in combinational circuits. Initially, it presents a BTI induced gate delay model suitable for circuit reliability analysis. Thereafter, it presents BTI impact analysis for the combinational circuits. Additionally, it provides a scheme to monitor BTI impact on the circuits. Finally, it describe two techniques to mitigate BTI impact on the circuits. The techniques include both static and dynamic approaches.
Chapter 6 focuses on BTI in sequential logic circuits. Initially, it presents analysis of BTI impact on dierent stages of a sequential logic circuits. The analysis shows dis-tribution of BTI induced delay in dierent stages of the circuit. Thereafter, it presents a scheme to monitor BTI impact in the circuits. Finally, it applies time borrowing technique to mitigate BTI in the circuits.
Chapter 7 presents BTI and partial open defects analysis of the SRAM decoders. Initially, the analysis focuses on BTI impact on both static and dynamic decoders under dierent addressing schemes. Thereafter, it analyzes the impact of resistive defects in
both pull-up and pull-down networks of a static decoder. Finally, it presents an analysis that combines both BTI and resistive defects in the decoders.
This dissertation ends with chapter 8, summarizing the chapters and the main con-tributions, followed by a number of recommendations for future research in the area of the semiconductor reliability.
Chapter 2
Reliability Failure Mechanisms
2.1 MOS Transistors
2.2 Reliability Failures Classi cation
2.3 Intrinsic Failure Mechanisms
2.4 Extrinsic Failure Mechanisms
2.5 Summary
Reliability failure mechanisms are electrical, chemical, physical and/or metallurgical phenomena stimulated by parameters like electric eld, electronic charges, semicon-ductor doping, temperature, radiations and/or moisture. A single or combination of multiple reliability mechanisms result in parameter variations, functional failures and/or structural damages of the semiconductor devices.
This chapter is intended to provide a brief review of the reliability failure mech-anisms through a short literature survey. The emphasis is on the physical origin of the mechanisms and a review of their well known models published so far. In this re-gards, Section2.1describes the basic MOS transistor structure. Section 2.2presents a reliability failures classi cation. Section 2.3 describes some prominent intrinsic failure mechanisms that take place inside the transistors and the interconnects. Section 2.4
presents some extrinsic failure mechanisms initiated by the external hazards. Finally, Section2.5presents a short summary to concludes the chapter.
2.1 MOS Transistors
The Metal Oxide Semiconductor Field Eect Transistor (MOSFET, henceforth known as MOS transistor) is a semiconductor device used for switching electronic signals. MOS transistors can be classi ed into two types, N-type i.e., NMOS transistor and P-type i.e., PMOS transistor. Figure 2.1 shows the basic structure of an NMOS transistor, which is obtained by implanting two identical and strongly doped negative (n) regions inside a lightly doped (p) substrate. The negatively doped regions of the transistor are
(SiO2)
Figure 2.1: Schematic cross section of an NMOS transistor.
connected to the drain (D) and the source (S) terminals, while the positively doped substrate is connected to the body or bulk (B) terminal. The source and drain are physically equivalent, the name assignment depend on the direction of current ow between them. The gate structure (G) is obtained by depositing an oxide layer and a poly metal (polycrystalline silicon is commonly used instead of metal) on top of the substrate. Conduction between the drain and source terminals of the transistor is controlled by the voltage on the gate (G) terminal. The PMOS structure (not shown) is complementary to the NMOS transistor, which has a negatively doped substrate and two identical strongly doped positive regions.
The area under the oxide layer and between drain and source is called channel. When a positive voltage is applied across the gate terminal of an NMOS transistor, it modi es the charge distribution in the channel. The voltage creates a depletion layer in the substrate by pulling the negatively charged carriers (electrons) toward the gate and semiconductor interface. If the gate voltage is high enough, high concentration of electrons forms an inversion layer in the channel. Conventionally, the gate voltage at
2.2. Reliability Failures Classi cation 11 which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage. At a su cient gate voltage, above the threshold voltage value, a conducting channel extends between the source and the drain, and current ows through it when a voltage is applied between the source and drain terminals.
Figure2.2shows the symbols generally used to represent NMOS and PMOS transis-tors in electrical schematics, where the drain, source, and gate terminals of the transistor are indicated by D, S, and G, respectively. The fourth terminal of MOS transistors, the substrate (B), is usually ignored in the schematics.
NMOS PMOS G G D S S D B B
Figure 2.2: Schematic icons of NMOS and PMOS transistors
2.2 Reliability Failures Classi cation
Reliability failures refer to the temporal degradations that lead to the parameter varia-tion, functional failure and/or structural damage of the semiconductor devices. To avoid reliability failures of semiconductor devices during their expected operational lifetimes under the speci ed conditions, it is necessary to identify and classify the failures, ana-lyze the underlying failure mechanisms and apply appropriate measures by re-mediating the design and/or improve the process to prevent/counteract them.
Fig. 2.3 presents a high level classi cation of the failures based on their sources. The gure shows that the failures can be categorized into two types, i.e. intrinsic and extrinsic. These failures are brie y described below and explained in the rest of this chapter.
2.2.1 Intrinsic failures
The failures in this category result from the reliability mechanisms that are rooted inside the semiconductor devices and are activated by the operational stress. These failures
Intrinsic
Extrinsic
Reliability Failures
Figure 2.3: Reliability failures classi cation
can be further categorized in two types. The rst type covers the mechanisms taking place inside the MOS transistors. While the second type covers the mechanisms that take place inside the interconnects. A detailed classi cation of the failure mechanisms (related to both transistors and interconnects) causing the failures is shown in Fig. 2.4
and described below.
Intrinsic failures
Transistor failure mechanisms Interconnect failure mechanisms
TDDB HCI
BTI RTN Oxide Breakdown Electromigration
Figure 2.4: Intrinsic failures classi cation
Transistor failure mechanisms
Transistor related failure mechanisms are mainly related to their oxide layers. Scaling of the oxide layer without corresponding reduction in the supply voltage has resulted in a stronger electric eld [2]. The eld degrade transistor behaviors by bringing physical changes to the oxide layer such as breaking Silicon-Silicon (Si-Si) and/or Silicon-Oxide (Si-O) bond inside the oxide layer and/or Hydrogen (Si-H) bond at Silicon-Silicon Dioxide (Si-SiO2) interface as shown in Fig. 2.5. Depending on the type and
location of bond breaking, the transistor related failure mechanisms can be further classi ed into four types as shown in Fig. 2.4. The Si-H bond breaking at Si-SiO2
2.2. Reliability Failures Classi cation 13
Figure 2.5: Dierent type of bonds inside the silicon and the oxide layer
evolves from trapping and de-trapping of carriers by the defects inside the oxide. Si-Si bond breakage inside oxide results in Time Dependent Dielectric Breakdown (TDDB). Similarly, Si-O and Si-Si bond breakage in SiO2 layer and Si-H bond breaking at the
Si-SiO2 interface and result in Hot Carrier Injection (HCI). These mechanisms are
explained in the next sections.
Interconnect failure mechanisms
The dominant mechanisms associated with the interconnect are the current induced metal migration the oxide breakdown. The ongoing scaling trends and the increasing chip functions have reduced the interconnect dimensions and increased the current stress; as a result the interconnect metal migrate from their original positions.
The metal migration is a general term that is used to describe material transport due to electrical stress, mechanical force, chemical reaction or temperature variation. In a chip interconnects, the migration is mainly dominated by electrical stress. A general term in the literature to describe the migration is Electromigration (EM). The elec-tromigration mainly takes place at Silicon (Si) and interconnect contact and produces short and/or open faults. Additionally, with the low-k materials introduced between the metal layers, the interconnects suer from the oxide breakdown.
2.2.2 Extrinsic failures
The failures in this category result from the failure mechanisms that are activated by the sources external to the semiconductor devices. These mechanisms can be further classi ed into two types, i.e. manufacturing and environmental as shown in Fig. 2.6.
The underlying mechanisms of these failures are brie y described below.
Extrinsic failures
Manufacturing failure mechanisms Environmental failure mechanisms
RTN Soft error Latchup
Figure 2.6: Extrinsic failures classi cation
Manufacturing failure mechanisms
The mechanisms in this category are activated at the time of manufacturing. During assembly and packaging semiconductor devices come into contact with dierent surfaces (i.e. machines, charged surfaces and human bodies) that deposit charges over them. These charges develop voltages in the sensitive areas of the devices that disturb the normal device parameters and cause electrical and/or structural failures.
Environmental failure mechanisms
The mechanisms in this category are stimulated during operation by environmental hazards such as, higher energy particles and radiations. For instance, energetic al-pha particles ejected from the semiconductor packaging and metalization impinge on the sensitive areas to disturb their normal operation. Additionally, interaction of the energetic radiation with the silicon disturb device parameters.
The work in this thesis mainly focuses on the reliability failures during operation. Therefore, only environmental failure mechanisms will be detailed later in this chapter.
2.3 Intrinsic Failure Mechanisms
This section focuses on the intrinsic failure mechanisms associated with both transistors and interconnects. For each failure mechanism, initially, it describes the physical origin and its impact on the transistor parameters. Thereafter, it presents a critical analysis of their well reputed models.
2.3. Intrinsic Failure Mechanisms 15
2.3.1 Transistor failure mechanisms
The transistor related failure mechanisms aect basic properties of the MOS transistors, particularly of their oxide layers. Well known transistor failure mechanisms include BTI, RTN, TDDB and HCI. A detailed discussion about these mechanisms is given below. 2.3.1.1 Bias temperature instability
Bias Temperature Instability (BTI) mechanism takes place inside the MOS transistors during their on states operating under a temperature range of 100-300oC and an oxide
eld of ∼6MV/cm. The aftereects of BTI on the transistors include, channel mobility reduction, linear and saturation currents reductions, and threshold voltage increment [44]. Si H Si Si Si H Si H H−H H H
Silicon
Gate Oxide
Poly
Figure 2.7: Bias Temperature Instability mechanism inside a MOS transistor The exact physical mechanism of BTI is not entirely understood and is still an active topic in the research community [3,11,33]; however, its origin is unanimously attributed to the generation of charges at silicon-oxide interface and/or inside the oxide layer of the transistors. In BTI mechanism, there are two distinct phases, i.e., stress phase and recovery phase [3]. For the stress phase, it is argued that the channel carriers tunnel through 1-2 ˚A of the oxide layer and are captured by the ≡Si-H bonds. The carriers capturing weaken the ≡Si-H bonds that are broken at higher temperature as shown in Fig. 2.7. The released H species move away from the silicon-oxide interface leaving charged interface states (interface traps) that cause the threshold voltage increment. For the recovery phase, the H species move back towards the silicon-oxide interface to anneal the broken ≡Si- bonds. The bond annealing lowers the threshold voltage increment.
As mentioned above, the exact mechanism of BTI is still not completely understood. Nevertheless, several well known BTI models are presented such as Reaction Diusion model [5, 3], Disorder-Controlled-Kinetics model [11] and Statistical mechanics based model [33]. These models along with their strengths and weaknesses are detailed below.
Reaction diusion model
Jeppson et al., in [5] proposed the fundamental concept of the Reaction Diusion(RD) model that prompted many researchers [3, 34, 35] to model BTI mechanism. The essence of the RD model is that interface traps are the main cause of BTI. About the temporal stages of the interface traps generation, the model argues that their generation rate is initially controlled by the Si-H bond breaking rate (kf) in the Reaction limited
regime and later by diusion of the hydrogen specie from the silicon-oxide interface in the Diusion limited regime. The reaction limited regime is quicker and the number of interface traps (NIT) generated in this regime has a linear relationship with the time,
i.e., NIT∼ No.kf.t. However, the diusion limited regime is slower and interface traps
generated in this regime has fractional-power law time dependence i.e., NIT∼ (Dt)n.
Exact value of the n depends on the type of the diusing specie, for example, for atomic hydrogen diusion n=1/4, and for molecular hydrogen diusion n=1/6 [35].
RD model claims BTI frequency independence, temperature dependence and advo-cated distinct behavior in the stress and recovery phases. However, the model cannot explain the quick annealing of ≡Si- bonds after the stress removal.
Disorder-controlled kinetics model
Kaczer et al., in [11] proposed a model that considers interface traps as the prime source of BTI induced degradation in the MOS transistors. For H specie transport inside the oxide layer, the model argues that energy distribution in the oxide layer makes it a disordered system. This disorder dictates dispersive diusion of the charged hydrogen species inside the oxide layer. Furthermore, the model suggests temperature dependent time exponent which implies that temperature acceleration cannot follow Arrhenius law as proposed by RD model [3]. However, it suggests temperature independence of ≡Si-H breaking and ≡Si- annealing by assumption that their temperature dependence are identical, therefore, both cancel each other. Furthermore, the model states that during recovery, the electric eld propel the charged hydrogen species movement towards the silicon-oxide interface that results in a higher recovery speed than proposed by RD model.
The model claims closeness to reality and more useful specially for the real time applications. However, the model has higher time complexity and cannot predict BTI impact on the transistors for longer time.
2.3. Intrinsic Failure Mechanisms 17
Statistical mechanics based model
Zafar in [33,36] proposed a model that relates BTI induced degradation to the charged traps at the silicon-oxide interface like the aforementioned models. However, the model also considers generation of charged states inside the oxide layer. The salient features of the model are that it: (a) uses statistical mechanics for breaking of ≡Si-H bonds at the silicon-oxide interface (b) relates saturation of BTI impact at longer stress duration with the depletion of ≡Si-H bonds at the silicon-oxide interface (c) considers hydrogen moving in the oxide layer as positively charged Hydrogen ion (H+) (d) assumes that
the moving ions leave traps at the interface and create charges inside the oxide layer and (e) assumes the power law exponent to be temperature dependent and oxide eld independent.
Like the previous models, this model assumes BTI dependence on the temperature, oxide eld, voltage and stress time.
2.3.1.2 Random telegraph noise
In Random Telegraph Noise (RTN), the alternate capture and emission of an individual active trap inside the oxide layer generates discrete switching in the MOS transistor threshold voltage and drain current.
Figure 2.8: Random Telegraph Noise mechanism
In the current MOS transistors, the channel is squeezed to the extent that there is a possibility of having an active oxide trap in the vicinity of silicon-oxide interface [8], as shown in Fig. 2.8. Furthermore, there are few carriers available in the channel and their transport is signi cantly aected by the traps within tunneling distance of the inversion layer. Capture and emission of a trap results in discrete stepwise variations -due to Coulombic repulsion- in the channel current resembling a random telegraph noise
in the communication. Although there is no agreed mechanism of RTN, generally it can attributed either to the mobility degradation due to enhanced Coulomb scattering or due to the carrier number uctuation caused by trapping.
Trap size model
Ohata et al. [37] proposed a model that related the uctuation in the drain current (∆Id) caused by a trap to its size (length and width). Analytical formulation of the
trap impact on the drain current is given by: ∆Id
Id
= wl(σo− σ)
W L(σo− σ) − w(L − l)(σo− σ) (2.1)
where w and l are the width and length of the hole; W and L are width and length of the channel; and σo and σ are the conductivity of the channel and in the cored out
region, respectively.
2.3.1.3 Time dependent dielectric breakdown
In Time Dependent Dielectric Breakdown (TDDB), the dielectric layer that isolates gate and substrate of the MOS transistor loses its insulating properties due to the stronger electric eld [38]. The aftereects of TDDB include loss of gate control over the channel current and an abrupt increment in the gate leakage currents.
TDDB is a two step linked process that consists of accumulation and thermal run-way. In the accumulation step, charges are generated inside the oxide layer, with the passage of time their density increases to a critical value. The step is followed by
ther-Accumulation
Thermal runaway
Figure 2.9: Time dependent dielectric breakdown mechanism inside the MOS oxide layer
2.3. Intrinsic Failure Mechanisms 19 currents that causes an abrupt increment in the gate leakage currents. Many studies have focused on the nature and origin of the accumulated charges [38]. It is argued that the accumulated charges include inter-facial oxide charges, xed oxide charges, and oxide trapped charges [39]. These charges follow Fowler-Nordheim (FN) tunneling [40], Direct tunneling [41], or Percolation theory [42] to constitute the leakage currents and initiate the breakdown.
The aforementioned charge collection and the resultant leakage current ow mech-anisms can be used to describe dierent steps of TDDB. However, the exact operative mechanisms and equations that completely de ne TDDB are still matter of controversy. Nevertheless, main attempts to model TDDB include the E-model, 1/E model, and the leakage current dependent power law model [43,44].
The E-model
The E-model, originally formulated by McPherson et al. in [45] states that the TDDB is due to breaking of Si-Si bond inside the oxide layer. The weaker Si-Si bonds with oxygen vacancy break under the oxide eld stress to generate the charges. These charges accumulate to a critical value and result in the oxide breakdown. The Mean Time To Fail (MTTF) due to TDDB has exponential dependence on the oxide electric eld and can be analytically represented by [7]:
M T T F = A · e(−γ·E)· e(k.TEa), (2.2)
where A is a constant, γ is a eld acceleration parameter, E is the oxide eld, Ea is the
activation energy, k is Boltzmann's constant and T is the absolute temperature. The model attained acceptability on the basis of experimental veri cation. However, it ignores the role of tunneling carriers and is un-adequate for the ultra thin oxides. Additionally, Vogel et al. in [46] conducted Substrate Hot Electron (SHE) injection experiment to show that the breakdown is dominated by the eect of energetic electrons and not by the oxide eld.
The 1/E model
The 1/E model proposed by Duschl in [47] states that the TDDB is an energy and uence-driven mechanism caused by the impact ionization and the hole injection in the oxide layer. According to the model, electrons are injected into the oxide layer by FN tunneling. Some of the electrons gain energy by the impact ionization to produce electron-hole pair. The generated holes travel towards the cathode under the in uence of the oxide eld. Additional holes are injected from the anode that accumulate with
the generated holes until they reach a critical density. The accumulated holes generate a local eld of considerable strength inside the oxide layer and initiate Stress Induced Leakage Current (SILC) that subsequently results in the oxide breakdown [38]. The MTTF due to TDDB depends inversely on the SILC which in turn strongly depends on the eld thus it gets the name reciprocal eld (1/E) model. The MTTF predicted by the model can be expressed mathematically as [7]:
M T T F = τo· e(
G E)· e(
Ea
kT), (2.3)
Where τoare G are constants. The 1/E model explains the current driven degradation in
the FN dominated region [47]. However, the model ignores the direct tunneling current in the ultra thin oxides and the thermal diusion that takes place in all material over time even in the absence of the electric eld [7].
For TDDB driven MTTF predictions, the linear E-model gives too much pessimistic assessment, on the other hand, the over progressive 1/E prediction is not demonstrated in practical life.
Power law Model
Fen et al. in [48] proposed a TDDB model based on the percolation concept [42]. The model incorporates TDDB dependence on the oxide thickness, trap density, FN current and tunneling current in the form of average leakage current (Iavg) inside oxide layer.
The model states that the MTTF of thin gate oxide (1.7-6.8nm) due to TDDB decreases inversely with the Iavg at the constant voltage stress and within the selected
temperature range [48]. The TDDB has power law dependence on Iavg as given by:
M T T F = A In
avg
· e(k·TEa), (2.4)
where A is a constant and n is a thickness dependent variable. The value of n increases from 1 to about 10 when the oxide thickness is reduced from 6.8 to 1.7nm.
The power law model is universal to t in dierent thickness, and even for dierent conduction mechanisms such as FN current, direct tunneling and space charges. 2.3.1.4 Hot carriers injection
In Hot Carriers Injection (HCI), the channel carriers generate charges at the silicon-oxide interface and/or inside the silicon-oxide layer that degrade transistor's threshold voltage, trans-conductance, and saturation current [43,49].
2.3. Intrinsic Failure Mechanisms 21
Figure 2.10: Hot Carrier Injection mechanism
The hot carrier injection mechanism is a manifestation of three queued stages as shown in Fig2.10. In the rst stage, the channel carriers -electrons and holes- become hot as they shoot out from the source region and gain energy (1.5eV for Si) by several means in the channel. In the second stage, majority of the carriers are collected at the drain to constitute the drain current, however, few carriers continue to gain energy (3.2-3.8 eV) until they overcome the oxide layer barrier and are injected into the oxide layer. In the nal stage, the injected carriers break ≡Si-H bonds at the silicon-oxide interface or Si-O2 inside the oxide layer. The broken bonds act as charge states that
aect the transistor parameters.
The main models that describe the hot carrier injection into the oxide layer include Lucky Electron Model (LEM) [6], Electron-Eective Temperature Model (EETM) [50], and the dominant energy Model [51].
Lucky electron model
Hu et al. in [6] presented the Lucky Electron Model (LEM) view to explain the HCI mechanism. The model is based on the "Lucky electrons" that gain su cient energy from the channel electric eld and are directed toward the oxide layer. The energetic electrons enters the oxide layer to generate charged states. According to this model, HCI induced MTTF can be analytically represented as [6]:
M T T F = C5·
W Id
· eϕit/(q·λ·Em) (2.5) where C5 and W are technology dependent constant and channel width, respectively.
While, I−1 d ·e
ϕit/(q · λ · E
m)is the hot carrier supply rate with Idbeing the drain current,
ϕit the critical energy to create charged state, λ being the hot carrier mean free path
LEM model provided guideline to the HCI modeling. However, one of the major limitations of the model is that the Electron Energy Distribution Function (EEDF) that enables the carriers injection into the oxide layer is only determined by the channel eld. This is the case for long-channel length and high energy (low gate voltage and high drain voltage) case. However, HCI eect in the short channel length and high gate voltage cannot be explained using the approach advocated by LEM.
Electron-eective temperature model
Rauch et al., in [50] proposed Electron-Eective Temperature Model (EETM) model to extend the LEM approach in explaining HCI at moderate gate voltages. The model incorporates electron-electron scattering as an additional source of the carrier energy by stating that at higher gate voltages there is a higher carrier concentration at the silicon-oxide interface that result in: (a) a higher electron-electron scattering per electron to increase its energy, (b) closeness to the silicon-oxide interface increases their chances of injection into the oxide layer. The MTTF due to HCI predicted by this model is given by [50]:
M T T F ∝ (g(Is, VDS)rmii)
−1 (2.6)
where riiis the impact ionization ratio near the silicon-oxide interface, and m is a tting
parameter that has dierent values depending on the drain voltage values. The model has commonalities with the LEM model and also owns its limitations, for instance the model does not consider the quasi-ballistic transport of the carriers.
Rauch et al., has recently argued in [51] that dominant energy is the main driving force in the HCI rather than peak lateral electric eld as it is in LEM. The model explains HCI over a large range of bias conditions (both Vg, and Vd), channel lengths,
and oxide thickness. Details of the model can be studied in [51].
2.3.2 Interconnect failure mechanisms
The interconnect failure mechanisms are stimulated by electrical stress, mechanical force, chemical reaction and/or temperature variation. The mechanisms resulting from the electrical stress include electromigration, inter-facial degradation between dierent metal layers, and whiskers. This section describes electromigration only as it is the most signi cant interconnect failure mechanism.
2.3. Intrinsic Failure Mechanisms 23 2.3.2.1 Electromigration
In electromigration, the interconnect metal atoms migrate from their initial positions to new locations due to the higher current stress. The migration degrade interconnect electrical parameters by producing high and low resistances, short and open faults.
Figure 2.11: Electromigration mechanism
The physical mechanism of electromigration can be explained by inspecting the interconnect structure that consists with grains of nearly identical constructions but dierent orientations. The high density current (electrons wind) owing through the interconnect interact with grains and force them to ow in their own direction as shown in Fig. 2.11. Driving forces of the ow are electrons-grains momentum exchange and electric eld force applied to the interconnect. It is argued that the eld force is insignif-icant and can be ignored in many cases. Therefore, momentum exchange is considered to be mainly responsible for the metallic ow [53]. The momentum exchange driven metal ow can be expressed using Einstein's equation as follows [52]:
J = D.C.Z
∗.e.ρ.j
k.T (2.7)
where J is the grain ow, D is the diusion coe cient, C is a technology constant, Z∗ is the eective charge number that represent magnitude and sign of momentum
exchange, e is the absolute value of electron charge, ρ is the metallic resistivity, j is the current density, k is the Boltzmann's constant and T is the absolute temperature. The equation states that the electromigration induced metal ow is directly proportional to the current density, the diusion coe cient and the concentration of diusing atoms.
Electromigration was recognized as an important reliability issue since 1960's. Black in [54] proposed a model that since then with some modi cations persisted its impor-tance to explain electromigration. The original model along with one of its variant are described below.
