Institut für Elektrotechnik und

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Institut für Elektrotechnik und

Informationstechnik Fachgebiet Datentechnik Prof. Dr. Sybille Hellebrand

E-Mail: sybille.hellebrand@uni-paderborn.de

UNIVERSITÄT PADERBORN |33095PADERBORN

Report on the Thesis

“Testing Digital Integrated Circuits with Novel Low Power High Fault Coverage Techniques and a new Scan Architecture”

submitted by Jedrzej Solecki

In his thesis Jedrzej Solecki focuses on built-in self-test (BIST) with power constraints and high qual- ity requirements. In my opinion this topic is of particular importance, because integrated systems manufactured in state of the art technologies suffer from an increasing susceptibility to defects as well as from parameter variations. Efficient test procedures are required throughout the whole life cycle of a system to screen out defective devices. While manufacturing test can still rely on automatic test equipment (ATE), periodic maintenance testing in the field must cope with the test infrastructure on chip only. Here, the key challenge for today’s highly complex systems is to achieve high fault cover- age in reasonable test time and with acceptable test data storage. For low power devices additional constraints must be observed to limit the energy budget of the test and to avoid damages due to excessive switching activities not foreseen during functional mode. In this context Jedrzej Solecki presents three new BIST architectures, the details of which are discussed in the sequel.

The manuscript starts with a short introduction describing the background of the thesis. To motivate his work, Jedrzej Solecki briefly discusses failure mechanisms and quality requirements, both result- ing in the need for efficient test techniques. After introducing the standard design for test (DFT) approaches and explaining power-related issues during test, he states the goal of his thesis. New DFT techniques are envisaged which reduce the ATE time, provide high quality in-field testing capabilities and allow accurate power control during test application.

The following three chapters contain the new test schemes developed within the framework of this

thesis. Chapter 2 is devoted to a scheme for low power BIST. Before the scheme is described in detail,

the state of the art in low power testing is reviewed in subsection 2.1. In particular it is pointed out that

during scan testing the major challenge is to minimize the toggle rate during shifting while keeping the

fault coverage high. Subsequently, the main idea for a new pseudo-random generator with controllable

toggle rate is presented in subsection 2.2. The developed PRESTO (PRESelected TOggling) generator

combines a standard pseudo-random pattern generator with controllable T flip-flops that allow to

switch between toggle and hold phases during shifting. The toggle control is realized by additional

logic producing weighted random signals from the state of the pseudo-random generator and a 4-bit

switching code. The extended version of the PRESTO generator uses additional weighted random

signals (driven by toggle and hold codes) to partition the scan-in sequences into alternating toggle and

hold intervals of random length. After a first experimental analysis, a systematic procedure to properly adjust the parameters of the PRESTO generator to the needs of the circuit under test is presented.

Further experimental analysis confirms that the PRESTO generator can successfully be tuned to pro- vide the desired toggle rates, but it also shows that the achieved fault coverage is not always sufficient.

Therefore a generator with improved fault coverage and a hybrid generator combining the pseudo- random patterns with deterministic patterns are proposed in subsections 2.3 and 2.4. The PRESTO generator with improved fault coverage is obtained by analyzing deterministic test patterns and identi- fying “base” scan chains. Base scan chains are characterized by a higher number of specified bits and must be activated with the help of an additional deterministic toggle control register. For the hybrid generator the PRESTO hardware is extended, such that low power deterministic patterns can by ob- tained by reseeding the pseudo-random generator and decompressing the test information into toggle and hold intervals in a similar way as the pseudo-random patterns. This scheme is supported by an encoding procedure which partitions the original test cubes into suitable toggle and hold intervals.

With these extensions the PRESTO generator can achieve high fault coverage in an embedded test scenario with an ATE supplying the deterministic test data.

In Chapter 3 Jedrzej Solecki presents a new scheme for deterministic BIST, which smartly re-uses the known Star-BIST scheme in a multiple-scan environment. As in Star-BIST, the test relies on similari- ties between deterministic patterns and is composed of parent patterns and their associated children within Hamming distance one. While a straightforward multiple-scan implementation would require a complex control, the proposed scheme exploits the observation that most of the specified bits of a pattern are concentrated in a single scan chain. A simple control generates the children by inverting complete scan slices. However, here the question is whether flipping complete scan-slices introduces unnecessary switching activity that could be avoided by a more fine-grained control scheme. The amount of test data to be stored for a fully autonomous BIST mainly depends on the number of parent patterns. To minimize the storage requirements, Jedrzej Solecki has developed both a comprehensive search algorithm and an iterative procedure interleaving the generation of parent patterns with fault simulation of the pattern and its associated children. An experimental study shows that in the iterative procedure closely approaches the results of the comprehensive search and can efficiently handle even very large circuits. To minimize the test time, the scheme also allows working with subsets of children instead of applying all children for each parent pattern.

Although the BIST schemes in Chapters 2 and 3 provide an excellent trade-off between test time, test

data storage, fault coverage, and power for traditional scan-based BIST, they still have, as any scan-

based scheme, a high ratio of test time to fault coverage and cannot fully cover new fault models re-

lated to the latest technology nodes. Section 4 is therefore dedicated to a new BIST architecture that

applies test patterns after every shift-cycle. To avoid the disadvantages of classical test-per-clock

schemes, the proposed approach partitions the flip-flops into three groups: flip-flops in stimuli mode,

compaction mode, and mission mode. The flip-flops in stimuli mode work similarly as conventional

scan chains, but the patterns are applied to the circuit under test in every clock cycle. The flip-flops in

compaction mode constitute a response compactor, and the flip-flops in mission mode work in normal

operation mode. As only a subset of the flip-flops is involved in testing, this scheme is also well suita-

ble for low power applications. However, several configurations with different assignments of mode

may be necessary for a complete test. To make the idea practical, Jedrzej Solecki proposes a dedicated

algorithm for scan stitching, an algorithm for selecting test configurations, as well as an algorithm for

test generation. Finally, Chapter 5 concludes the manuscript with a short review of the three developed techniques.

Overall, Jedrzej Solecki has developed very good solutions for a clearly formulated research problem of high relevance. In addition to the conceptual work, he has validated the proposed architectures and procedures by experimental case studies targeting large industrial designs. His work is based on a comprehensive yet concise review of the relevant literature and relies on appropriate strategies. As confirmed by the experimental analysis, the three BIST schemes developed within the framework of the thesis support a high quality test throughout the life cycle of a system at reduced test cost and time while taking into account power constraints. The achieved results are clearly ahead of the state of the art, which is also confirmed by a number of peer-reviewed publications in internationally recognized conferences and journals as well as by two US patents and several patent applications. Furthermore, due to the successful cooperation with Mentor Graphics Corp., the thesis is also very strong with re- spect to its practical applicability. The underlying assumptions are based on realistic industrial data, and the developed procedures can easily be integrated into an industrial design flow. Nevertheless, it would have been desirable to see more comparisons with independent work from the literature.

The manuscript provides a clear description of the developed approaches and gives the expert reader a complete picture of the work. For the non-expert reader, it would have been helpful to include a more self-contained description of the state of the art and explain the drawbacks of existing solutions more clearly. Similarly, the explanations of the new solutions could have been enhanced with more exam- ples highlighting the key features and challenges.

Despite these small deficiencies, the thesis fulfills the requirements for the degree of Doctor of Philosophy as stated by the current law and its quality is clearly above the average. Therefore, I strongly recommend accepting thesis as submitted and rating it as “very good”.

Paderborn, October 7, 2015 Univ.-Prof. Dr. Sybille Hellebrand