Multi-Scale Material and Technology for Heterogeneous Integration

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(1)M ULTI -S CALE M ATERIAL AND T ECHNOLOGY FOR H ETEROGENEOUS I NTEGRATION.

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(3) M ULTI -S CALE M ATERIAL AND T ECHNOLOGY FOR H ETEROGENEOUS I NTEGRATION. Proefschrift ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K. C. A. M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op woensdag 20 januari 2016 om 12:30 uur. door. Regnerus Hermannus P OELMA Werktuigkundig ingenieur geboren te Hefshuizen, Nederland.

(4) Dit proefschrift is goedgekeurd door de promotor: Prof. dr. G. Q. Zhang promotor: Prof. dr. P. M. Sarro Samenstelling promotiecommissie: Rector Magnificus,. voorzitter. Prof. dr. G. Q. Zhang,. Technische Universiteit Delft. Prof. dr. P. M. Sarro,. Technische Universiteit Delft. Onafhankelijke leden: Prof. dr. C. P. Wong. Georgia Institute of Technology. Prof. dr. X. J. Fan. Lamar University USA. Prof. dr. F. Roozeboom,. Technische Universiteit Eindhoven. Prof. dr. K. M. B. Jansen,. Technische Universiteit Delft. Prof. dr. H. E. J. G. Schlangen,. Technische Universiteit Delft. Keywords: multi-scale materials, integration, carbon nanotubes, modelling and experimentation Printed by: Ipskamp drukkers. Copyright © 2016 by R.H. Poelma All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the prior written permission of the copyright owner. ISBN: 978-94-028-0025-8 An electronic version of this dissertation is available at. http://repository.tudelft.nl/..

(5) C ONTENTS 1 Introduction. 1. 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1. 1.1.1 Bridging the gap between 2D and 3D . . . . . . . . . . . . . . . .. 2. 1.1.2 Advanced multi-scale materials . . . . . . . . . . . . . . . . . . .. 3. 1.1.3 Size-dependent materials . . . . . . . . . . . . . . . . . . . . . .. 4. 1.1.4 The route towards applications . . . . . . . . . . . . . . . . . . .. 5. 1.2 Outline of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7. 2 Through Polymer Vias. 11. 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 Processing thick film photo resist . . . . . . . . . . . . . . . . . . 15 2.2.2 Silicon pillars . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3 Carbon nanotube pillars . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 Thin film conformal metallization . . . . . . . . . . . . . . . . . . 19 2.2.5 Wafer-level-packaging and film assisted moulding. . . . . . . . . . 23 2.3 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 Tailoring the Mechanical Properties of Carbon Nanotube Arrays using a-SiC Coatings. 31. 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 Experimental Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.1 CNT sample preparation . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.2 CNT coating procedure . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.3 Correlation between coating thickness and porosity . . . . . . . . . 36 3.2.4 Raman spectroscopy . . . . . . . . . . . . . . . . . . . . . . . . . 38 v.

(6) vi. C ONTENTS. 3.2.5 Nanoindentation measurements. . . . . . . . . . . . . . . . . . . 39 3.3 Discussion and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.1 Compressive failure of uncoated CNT pillars. . . . . . . . . . . . . 44 3.3.2 Compressive failure of coated CNT pillars . . . . . . . . . . . . . . 46 3.3.3 Young’s modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4 Modelling the Effects of Nanoscale Coating and Structure on Carbon Nanotube Arrays. 59. 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2 Experimental Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.1 Carbon Nanotube Array Nanostructure . . . . . . . . . . . . . . . 62 4.2.2 Nanoscale Conformal Coating . . . . . . . . . . . . . . . . . . . . 63 4.3 Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.1 Co-rotational Beam Theory . . . . . . . . . . . . . . . . . . . . . 64 4.3.2 Bending Stiffness. . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.3 Normal Forces and Bending Moments . . . . . . . . . . . . . . . . 68 4.3.4 Material and Geometric Stiffness Matrix . . . . . . . . . . . . . . . 69 4.3.5 Contact Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.6 Contact Stiffness and Sticking Friction . . . . . . . . . . . . . . . . 72 4.3.7 Assembly Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.8 Multi-Scale Mesh . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.9 Periodic Boundary Conditions . . . . . . . . . . . . . . . . . . . . 75 4.3.10 Matrix Failure and Fiber Fracture . . . . . . . . . . . . . . . . . . 77 4.4 Solution Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.5 Validation of the theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.1 Literature Benchmark Problems . . . . . . . . . . . . . . . . . . . 85 4.5.2 Van der Waals Interaction . . . . . . . . . . . . . . . . . . . . . . 89 4.6 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.6.1 Compressive Strength and Elastic Modulus . . . . . . . . . . . . . 92 4.6.2 Carbon Nanotube Waviness . . . . . . . . . . . . . . . . . . . . . 96 4.6.3 Nanotube Friction . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.4 Post-failure behaviour . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6.5 Effects of Periodic Boundary Conditions and Unit-Cell Size . . . . . 99 4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.

(7) C ONTENTS. vii. 5 Effects of single vacancy defect position on the stability of carbon nanotubes 107 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.2 Theory: Molecular dynamics . . . . . . . . . . . . . . . . . . . . . . . . 109 5.2.1 Forcefields and Potential energy . . . . . . . . . . . . . . . . . . . 109 5.2.2 Boundary conditions and reaction forces . . . . . . . . . . . . . . 112 5.2.3 Numerical procedure . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3 Results and validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.3.1 Euler buckling theory . . . . . . . . . . . . . . . . . . . . . . . . 115 5.3.2 Defect free CNT buckling . . . . . . . . . . . . . . . . . . . . . . 116 5.3.3 Defective CNT buckling results . . . . . . . . . . . . . . . . . . . 118 5.4 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6 A novel approach for characterizing the properties of ultra-thin films. 125. 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.2 Fabrication and geometry characterization . . . . . . . . . . . . . . . . . 128 6.2.1 Fabrication of nanocantilevers . . . . . . . . . . . . . . . . . . . . 128 6.2.2 Geometry characterization. . . . . . . . . . . . . . . . . . . . . . 130 6.3 Electrostatic pull-in instability: Experiment. . . . . . . . . . . . . . . . . 131 6.3.1 Measurement apparatus . . . . . . . . . . . . . . . . . . . . . . . 132 6.4 Electrostatic pull-in instability: Model . . . . . . . . . . . . . . . . . . . 133 6.4.1 Analytical approximation . . . . . . . . . . . . . . . . . . . . . . 134 6.4.2 Thin film stress. . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.4.3 Numerical approach . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.5 Results and discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.5.1 Sensitivity analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.7 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.7.1 Bio Sensing Application . . . . . . . . . . . . . . . . . . . . . . . 148 6.7.2 Wafer-Level-Packaging Application . . . . . . . . . . . . . . . . . 149 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7 Thermal Conductivity of Carbon Nanotubes in Anodic Aluminum Oxide Membranes. 157. 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.2 Experimental section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.2.1 Sample fabrication and geometry characterization . . . . . . . . . 159.

(8) viii. C ONTENTS. 7.2.2 Thermal conductivity measurement . . . . . . . . . . . . . . . . . 162 7.3 Theoretical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.3.1 Effective-mean-field approach . . . . . . . . . . . . . . . . . . . . 166 7.3.2 Numerical validation. . . . . . . . . . . . . . . . . . . . . . . . . 167 7.4 Results and discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.4.1 Thermal conductivity . . . . . . . . . . . . . . . . . . . . . . . . 169 7.4.2 Recommendation: Sensitivity analysis . . . . . . . . . . . . . . . . 170 7.5 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 8 Multi-LED Package Design and High-Aspect-Ratio Optics Moulding. 175. 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 8.2 Design requirements and fabrication . . . . . . . . . . . . . . . . . . . . 176 8.3 Thermal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.3.1 Modelling Approach . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.3.2 Optimized heat-sink . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.3.3 Thermal Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.4 High aspect ratio optical lenses for LEDs . . . . . . . . . . . . . . . . . . 186 8.4.1 Model description . . . . . . . . . . . . . . . . . . . . . . . . . . 187 8.5 Constitutive relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 8.5.1 Ogden Hyperelasticity . . . . . . . . . . . . . . . . . . . . . . . . 189 8.5.2 Material Data Fitting . . . . . . . . . . . . . . . . . . . . . . . . . 190 8.5.3 Stress Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 9 Concluding Remarks and Recommendations. 195. 9.1 On the heterogeneous integration of high-aspect-ratio microstructures (Chapter 2 and 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 9.1.1 Recommendations regarding packaging . . . . . . . . . . . . . . . 196 9.2 On the multi-scale material behaviour and characterization (Chapter 3, 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 9.2.1 Recommendations regarding experiments . . . . . . . . . . . . . . 197 9.3 On the modelling and simulation of materials (Chapter 4 and 5) . . . . . . 197 9.3.1 Recommendations regarding modelling . . . . . . . . . . . . . . . 198 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199.

(9) C ONTENTS. A appendix-a. ix. 201. A.1 Supporting Information Chapter (2) . . . . . . . . . . . . . . . . . . . . 201 A.1.1 Conformal metallization using ALD . . . . . . . . . . . . . . . . . 201 A.1.2 Electro / electro-less plating . . . . . . . . . . . . . . . . . . . . . 202 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 B appendix-b. 205. B.1 Supporting Information Chapter (4) . . . . . . . . . . . . . . . . . . . . 205 C appendix-c. 213. C.1 Supporting Information Chapter (6) . . . . . . . . . . . . . . . . . . . . 213 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Summary. 215. Samenvatting. 219. List of Publications. 223.

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(11) 1 I NTRODUCTION 1.1. B ACKGROUND. H. ETEROGENEOUS. system integration combines different devices and materials into. a single microelectronic system. It enables cost effective and reliable approaches. to achieve more functionality "More than Moore" and minimization of geometric size and power consumption [1–4]. Heterogeneous devices and materials often originate from different technological backgrounds and processes and can be used for a variety of different applications ranging from wafer-level-packaging, micro/nano electromechanical systems (MEMS/NEMS) towards solid-state-lighting (SSL). This will also become clear in this thesis, as we touch upon several distinct topics ranging from application oriented research such as the fabrication of high-aspect-ratio vertical interconnects, waferlevel-packaging and high-aspect-ratio optics moulding, towards the development and characterization of multi-scale materials for fabrication of novel micro/nano-architectures with uniquely fine-tuned material behaviour. Notably, "More than Moore" is closely linked with material research. Especially since dissimilar materials are used on different size-scales, we encounter problems such as interface delamination, size-effects and even fracturing. It is not always clear on which scale failure originates or how to define material properties and model a multi-scale system. "Moore" drives miniaturization. When reaching the nano-scale, new size dependent material properties and behaviour are encountered, also known as "size-effects". 1.

(12) 2. 1. 1. I NTRODUCTION. 1.1.1. B RIDGING THE GAP BETWEEN 2D AND 3D Vertical interconnect access (VIAs) are a key technology enabler for 3D heterogeneous system integration, leading towards smaller systems and shorter overall interconnect length. As a consequence, 3D integration can offer a new level of high-frequency performance, power efficiency and form factor reduction for the entire semiconductor industry. The microelectronics industry is moving towards 3D integration of system in package (SiP) and stacking of package on package (PoP) to meet the demands for increased functionality, miniaturization, cost reduction of smart systems and improved electrical performance. This is illustrated by the package evolution, which is spread out over several decades in Figure 1.1. The package cross-sections reveal a more complex structure and show the need for through package vertical interconnects to enable 3D integration. However, current state-of-the-art technology to create through polymer VIAs (TPV) is still high cost and not suitable for mass-production. Therefore we investigate a novel solution for creating high input-output (IO) count TPVs using high-aspect-ratio (HAR) micropillars and wafer-level-packaging (WLP) through film assisted transfer moulding.. Figure 1.1: Microelectronics packaging and integration evolution showing the new focus on 3D interconnect technology. Source: Yole Development Semicon Taiwan 2012 [5].. Three distinct processes were developed for the fabrication of high aspect ratio, lithographically defined micropillars and microstructures that are suitable for mass production, Figure 1.2a-c. The processes for fabrication and packaging of these microstructures are scalable due to the parallel fabrication method, unlike wirebonding processes, where connections are made one by one. The functionality and material properties of the pillars can then be modified using coatings of different materials and thicknesses. Furthermore, the transfer moulding technique employed for wafer-level-packaging and encapsulation of the pillars, is also a parallel fabrication method since multiple chips are.

(13) 1.1. B ACKGROUND. 3. packaged in one step Figure 1.2d. In addition, transfer moulding can help produce millimetre to centimetre sized structures, where microfabrication technology is not feasible any more, to create e.g. structures such as silicone optical lenses Figure 1.2e. Henceforth, micro/nano fabrication and transfer moulding are complimentary technologies that support each other and when combined they lead to new solutions. • High aspect ratio micro-pillars lithographically defined in thick (dry) film photoresists Figure 1.2a. • Deep reactive ion etching (DRIE) of high aspect ratio silicon micro-pillars Figure 1.2b. • Vertically aligned carbon nanotube pillars, grown through a bottom-up process using low pressure chemical vapour deposition Figure 1.2c.. Micro/nano fabrication technology (a). (b). Thick-film photo-resist pillar Coating. (c). DRIE etched pillar. Mask. Carbon nanotube pillar. Catalyst particles. Transfer moulding technology (d). Through polymer via. (e) Epoxy moulding compound. Transfer moulded silicone optics LED. Figure 1.2: Micro/nano fabrication technology is employed to create different high aspect ratio micropillars for interconnect applications: (a) thick film photo-resist pillar, (b) micro-pillar in bulk silicon by deep reactive ion etching (DRIE), (c) micro-pillar grown from vertically aligned CNT arrays. Transfer moulding technology is employed to, (d) encapsulate the micropillars creating through polymer vertical interconnects, (e) fabricate high aspect ratio silicone lenses for optical applications.. 1.1.2. A DVANCED MULTI - SCALE MATERIALS Nanoscale materials, unlike bulk materials, are one of the few engineering materials that can be grown from the bottom up in a controlled manner. The ability to accurately. 1.

(14) 4. 1. 1. I NTRODUCTION. control material behaviour and properties becomes indispensable for applications requiring design for reliability. For example, controlling the coefficient of thermal expansion mismatch between dissimilar materials, or the manipulation of compliance and ductility, can minimize thermal and mechanical stress. Here, the porous nature of carbon nanotube (CNT) arrays allows for the unique opportunity to tailor their mechanical response and functionality by the infiltration and deposition of different nanoscale conformal coatings [6]. The vertically aligned CNT arrays in photo-lithographically defined patterns have been recognized as a promising structural material for the fabrication of high-aspect-ratio, 3D micro- and nano-architectures [6, 7]. The material plays an important role in the advancement of vertical interconnect technology [8], thermal interface materials [9–12], 3D super-capacitors [13], tunable Fresnel lenses [14], flexible batteries [15], stamps for nano-imprint lithography [16] and NEMS and MEMS [7, 17]. However, CNT array structures are also multi-scale in nature, spanning length scales from nanometres towards centimetres [18, 19]. This tremendous size-range and interlinked scale make the material behaviour challenging to model. It has been postulated that there is not yet a quantitative theory that can predict the mechanical behaviour of CNT arrays as a function of its microstructure let alone the effects of conformal coating. We propose and develop a novel semi-continuum multi-beam modelling approach to bridge the gap between discrete and continuum theory. Figure 1.3 shows part of the multi-scale regime which we aim to cover in this thesis. We use the method to study the effects of nano/micro-structure and coating on the material properties of nano-porous materials [20]. Thein-situ compression of the CNT micro-pillars inside a scanning electron microscope revealed significant changes in deformation behaviour as function of coating material. See Video 1 and Video 2 for the CNTs coated with silicon carbide and Video 3 for pillars modified by atomic layer deposition (ALD) of Pt. In this thesis we perform a theoretical and experimental analysis of the effects of coating on the mechanical properties of CNT arrays.. 1.1.3. S IZE - DEPENDENT MATERIALS Thin film technology is found in a wide range of applications ranging from microelectronics, sensors, actuators towards structural and sacrificial layers [21]. The need for more integrated functionality, minimization of material and energy consumption is driving the ongoing miniaturization. As a consequence, materials are processed on the micro- and nanometre scale. Recent studies, both experimental [22, 23] and theoretical [24, 25], have shown and predicted that mechanical and material properties such as.

(15) 1.1. B ACKGROUND. 5. CNT 3D architecture. 1. Size Scale Paradigm. Different failure modes dependent on coating Missing link 50 um CNT array micro/nano structure. 2 um Single CNT. 100 nm Multi-Scale Materials. Molecular Dynamics. Semi-Continuum Mechanics. Continuum Mechanics. Figure 1.3: Bridging the gap for multi-scale materials using a semi-continuum finite element modelling approach to simulate the effects of nanoscale coating on carbon nanotube arrays.. Young’s modulus and yield stress become noticeable functions of size on the micro- and nanoscale. This is also known as a size effect [26, 27]. Characterization of the material and mechanical response at device level is crucial for reliable and predictable performance of systems. Therefore, great interest is shown in the effects of size and structure on the material properties. However, variations in experimental results and difficulties in experimental methods, make accurately determining nanoscale properties a challenge. In this work we present a robust and versatile experimental approach, known as electrostatic pull-in instability, for characterizing the size-dependent elastic properties of nanoscale films [28]. Expanding the physics domain from electro-mechanic towards fluid-structure interactions, we also showed that capillary pull-in instability can be exploited for wafer-level-packaging applications [29].. 1.1.4. T HE ROUTE TOWARDS APPLICATIONS Heterogeneous system integration covers not only the microelectronics industry but can also be expanded towards the solid-state-lighting industry. Here, the light emitting diodes (LEDs) are currently one of the most energy efficient light sources available. Consequentially, high brightness LEDs become the cheapest light source over time compared to incandescent light bulbs and compact fluorescent lamps for lighting ap-.

(16) 6. 1. 1. I NTRODUCTION. plications. However, the integration of multiple high brightness LEDs into a single microelectronic package leads to several challenges in the fields of thermal and optical management. This can be explained by the fact that bare LED dies are very small and concentrated light and heat sources. These devices typically need additional optical and thermal elements such as lenses and heat-sinks for extraction and distribution of light and heat. Controlling the heat dissipation from the LEDs is crucial for reducing the LED junction temperature and improving its lifetime. This sometimes requires novel and unconventional solutions ranging from intricate MEMS based thermal switches towards advanced materials such as highly thermally conductive CNTs [10, 30]. Encapsulation of multiple devices in one moulding step can reduce cost and size of heterogeneous systems. More so, the transfer moulding of 3D high-aspect-ratio optical silicone lenses directly on multi-LED packages improves the optical performance [31, 32].. 1.2. O UTLINE OF THIS T HESIS The outline of the research presented in this thesis is shortly summarized below for each chapter. In Chapter (2) we focus on developing a novel solution for robust throughpolymer-via (TPV) interconnects for 3D heterogeneous system integration (3D-HSI), suitable for high input/output (I/O) count. Here, we fabricate photo-lithographically defined high-aspect-ratio micro-pillars in a thick layer of photo sensitive film on a carrier wafer. The pillars are conformally coated with an electrical conductive layer at low temperature and encapsulated using a film assisted wafer-level-packaging approach. In Chapter (3) we focus on fabrication of high-aspect-ratio micro-pillars employing advanced multi-scale materials such as carbon nanotube (CNT) arrays. The porous nature of CNT arrays allows for the unique opportunity to tailor their mechanical response by the infiltration and deposition of nanoscale conformal coatings. We demonstrate this behaviour by performing flat-punch nano-indentation experiments on pillars with various aspect-ratios and coating thicknesses. In Chapter (4) we systematically investigate the effects of nanostructure and nanoscale conformal coating on the mechanical behaviour of vertically aligned CNT arrays through a novel semi-continuum modelling approach. The discrete length scales of CNT array structures span from nanometres towards centimetres. This tremendous size-range and interlinked-scale make the material behaviour challenging to model. Consequently, it has been postulated in the literature that there is not yet a quantitative method that can predict the mechanical behaviour of CNT arrays as function of its micro/nanostructure. Henceforth we, try to shed light on this issue by using a custom build finite element analysis (FEA) program, which re-.

(17) R EFERENCES. 7. lies on a co-rotational multi-beam semi-continuum formulation. Our modelling approach accounts for the porous nanostructure of the array, which contains multiple CNTs with random waviness, van der Waals interactions, fracture strain, contacts and frictional forces present among them. In Chapter (5), we study the mechanics of both single- and multi-wall CNTs under unidirectional compression. The nanotubes are influenced by temperature effects and vacancy defects and their mechanical behaviour is predicted using discrete modelling approach such as molecular dynamics (MD). This computational method allows for the detailed study of defects. However, it is not suitable for capturing the macro-structure efficiently, due to large number of simulated particles that is required to reach the micrometre scale for CNT arrays. In Chapter (6) a novel experimental approach for measurement of the effective Young’s modulus and its size effect in homogeneous nanoscale films is demonstrated using a nano-electromechanical-system (NEMS). We introduced a novel measurement technique to help improve and study materials at smaller size-scales. The thermal conductivity of materials plays a fundamental role in the thermal management of small electronic devices. Consequently, materials are often primarily selected on their thermal performance. The expected thermal conductivity of CNTs used in composites appears to be significantly lower than individual (freely suspended) carbon nanotubes. Henceforth, Chapter (7) focuses on the characterization of the effective thermal conductivity of porous anodic aluminium oxide (AAO) membranes before and after the catalyst free CNT synthetisation. The thermal conductivity was measured using a steady-state heat transfer experiment. In Chapter (8) a thin package containing multiple light emitting diodes (LEDs) is designed, manufactured and its thermal performance is characterized. Bare LED dies are very small and concentrated light and heat sources. These devices typically need additional optical and thermal elements such as lenses and heat-sinks for extraction and distribution of both light and heat. In this chapter we first analyse the thermal management of high brightness multi-LED packages. Secondly, we study the transfer moulding of 3D high-aspect-ratio optical silicone lenses directly on the multi-LED package. Chapter (9) concludes the thesis and gives an outlook towards future work.. R EFERENCES [1] W. Chen, W. R. Bottoms, K. Pressel, and J. Wolf, The next step in assembly and packaging: System level integration in the package (sip), SiP White Paper V9.0 (2013). [2] International Technology Roadmap for Semiconductors, Tech. Rep. (2013 Edition). [3] G. Q. Zhang, M. Graef, and F. van Roosmalen, The rationale and paradigm of "more than moore", in Electronic Components and Technology Conference. Proceedings. 56th (2006) p. 7. 1.

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(21) 2 T HROUGH P OLYMER V IAS 2D integrated systems such as system in package (SiP) and systems on chip (SoC) products in consumer electronics have become the main drivers of the semiconductor industry in terms of volume. 3D integrated systems composed of heterogeneous devices are the next logical step addressing the increased wiring density challenges by enabling package on package and chip stacking. In this study we focus on developing a novel solution for robust through-polymer-via (TPV) interconnects for 3D heterogeneous system integration (3D-HSI), suitable for high input/output (I/O) count. The approach relies on the lithographic patterning of micro-pillars in a thick layer of photo sensitive film on a carrier wafer or substrate. The pillars are conformally coated with an electrical conductive layer at low temperature using an IC-compatible process. The layer can then be used as electrical interconnect layer, or seed-layer for electro and electro-less plating of Cu, Ni, Au and/or other metals. After the metallization process the pillars are encapsulated inside an epoxy moulding compound (EMC) using a thin film assisted transfer moulding technique. This approach keeps the topside of the vertical interconnects clean of EMC, creating vertical through-polymer interconnect vias (TPV).. 11.

(22) 12. 2. T HROUGH P OLYMER V IAS. 2.1. I NTRODUCTION System in package (SiP) and systems on chip (SoC) products in consumer electronics have become the main drivers of the semiconductor industry in terms of volume [1].. 2. Heterogeneous system integration (HSI) combines different silicon dies and materials into a single microelectronic package. It enables “More than Moore” functionality and minimization of size and power consumption [1–4]. Heterogeneous integrated systems can be composed of a variety of devices, such as; logic, memory, analogue, RF and MEMS. The systems have a wide impact on applications such as smart electronics, mobile communication and others which require miniaturized, multi functional and energy efficient microelectronics [1]. Smart systems in package (SSiPs) containing wireless communication devices, are occupying frequencies in the multi gigahertz regime. At these high frequencies, the signal integrity is negatively influenced by transmission line effects in long planar interconnects and wire bonds. Even today, looking from the outside, we can still imagine the microelectronic package as a simple black plastic box with a small silicon die on the inside and electrical contacts on the outside, or in other words, a silver-legged black insect with a company logo on the top [5], see for example in Figure 1.1 the dual inline package (DIP) produced around 1970s. Packaging microelectronics would therefore seem easy to the outsider. Since, in theory, it consists of breaking up the wafer in small individual dies, providing the electrical connections to the substrate and then encapsulating the entire thing in molten plastic to make it easy to handle [5]. However, the cross-section of the package reveals a more complex structure, which is illustrated by the package evolution over several decades in Figure 1.1. The many different materials, interfaces and technologies have to be low cost, mass-produced, compatible and reliable to create a successful microelectronic package. The package is mass-produced by transfer moulding technology, where encapsulation materials such as epoxy moulding compound (EMC) are used to encapsulate the systems [6]. Encapsulation materials can contain different ratios of epoxy resins, hardeners, accelerators, flexibilizers, fillers, flame retardants, coupling agents, and release agents all tuned to achieve certain desirable properties [7]. The microelectronics industry is moving towards 3D integration of system in package (SiP) and stacking of package on package (PoP) to meet the demand for increased functionality, miniaturization, cost reduction of smart systems and improved electrical performance [8]. The cross-section of the package reveals a complex structure and evolution towards 3D. Vertical interconnect access (VIAs) connect chips, devices, interconnection layers, wafers and microelectronic packages in out of plane direction. The advantage of VIAs for 3D heterogeneous system integration are shorter total length of.

(23) 2.1. I NTRODUCTION. 13. the interconnections, lower resistance, reduction in the signal delay, and minimization of parasitic inductances. Vertical interconnects are therefore a key enabler for 3D system integration. They address the challenges of increased wiring density which in turn can lead towards improved high-frequency performance, power efficiency and form factor reduction for the semiconductor industry [1, 2, 9–13].. 2.1.1. S TATE OF THE A RT The increasing complexity of 3D packages requires novel and more robust approaches for achieving high-density VIAs to connect multiple systems in out of plane direction. Currently existing 3D technologies for creating through-package interconnects, have limited usage due to significant fabrication challenges and high production costs. Some examples are given below: 1. A well defined and active research area that is currently enabling vertical interconnects, is based on the through silicon vias (TSV) and the TSV interposers [9, 12, 14, 15]. Some of the problems involved with TSV fabrication are the conformal coverage of complex surfaces, filling of narrow high-aspect-ratio (HAR) structures, wafer thinning and cracking of the Si wafer due to the material property mismatch with metals [16]. Furthermore, accurate placement and the electrical connection of a TSV interposer with interconnect layers is a challenge on its own. 2. Another approach is the through mold via (TMV), which can be formed using a process for epoxy-molding-compound drilling and residue cleaning. Afterwards they are filled with solder using for example a screen printing process [17]. However, this process is not very suitable for 3D integration due to the large via diameter d ≥ 450µm, low aspect ratio of 1:1 and the high resistance of the solder material. 3. Conventional SU8 polymer micro-structures can also be used as templates for the bottom up plating of vertical interconnects such as micro-bumps or pillars. However, the plating template has to be removed after growth of the interconnect microstructure to make room for the die attachment. Furthermore, the bottom-up plating in small holes is difficult as is the removal of cured SU-8 after the plating process [18]. In this work we focus on developing robust through-polymer-via (TPV) interconnects for 3D-HSI, suitable for high I/O count and high frequency applications. Figure 2.1 shows the scope of this article. We take an unconventional route: instead of making. 2.

(24) 14. 2. T HROUGH P OLYMER V IAS. holes and filling the via holes with electrical conductive material, we create lithographically defined high-aspect-ratio (height/diameter ≥ 10:1) pillars which can be carbon nanotube based [19], polymer or silicon based. The pillar structures are then made con-. 2. ductive by using different conformal deposition methods. Afterwards the pillars (vias) and dies are encapsulated inside an epoxy moulding compound (EMC) using a thin film assisted wafer-level-packaging approach [6]. The results consist of packaged 100mm diameter Si wafers with high aspect ratio TPVs. It was found crucial that the top surface of the pillars remained clean of epoxy moulding compound for fan-out. With the use of thin film clamping technology and transfer moulding, this was achieved for pillars with extreme aspect ratios. Systems in a package (IC chips). Scope Package 1. Package 2. Figure 2.1: Cross-section of two microelectronic packages stacked on top of each other. The through polymer via (TPV) connects top and bottom package interconnect layers. This allows for vertical stacking of wafers and packages.. 2.2. A PPROACH In this section the fabrication process of the through polymer interconnect via (TPV) is discussed. In our demonstrator, the carrier substrate consist of 100 mm diameter Si wafers. However, other substrates can also be used such as lead-frames, Si interposers and organic ball-grid-array (BGA) boards, since the required temperature budget is relatively low (150 ◦C) in the case of the photoresist pillar process. Three distinct processes were developed for the fabrication of high aspect ratio, lithographically defined micropillars and microstructures that are suitable for mass production, Figure 2.2. The processes for fabrication and packaging of these microstructures are scalable due to the parallel fabrication method. The functionality and material properties of the pillars can then be modified using coatings of different materials and thicknesses. Furthermore, the transfer moulding technique employed for wafer-level-packaging and encapsulation of the pillars, is also a parallel fabrication method since multiple chips are packaged in one step..

(25) 2.2. A PPROACH. 15. • High aspect ratio micro-pillars lithographically defined in thick (dry) film photoresists Figure 2.2a. • Deep reactive ion etching (DRIE) of high aspect ratio silicon micro-pillars Fig-. 2. ure 2.2b. • Vertically aligned carbon nanotube pillars, grown through a bottom-up process using low pressure chemical vapour deposition Figure 2.2c. • Wafer-level-packaging and encapsulation of the pillars using film assisted transfer moulding Figure 2.2d.. Microfabrication technology (a). (b). Thick-film photo-resist pillar Coating. DRIE etched silicon pillar. Mask. Nanofabrication. Transfer moulding technology. (c). (d). Carbon nanotube pillar. Through polymer via. Epoxy moulding compound. Catalyst particles. Figure 2.2: Concepts to show how micro/nano fabrication technology is employed to create different high aspect ratio micropillars for interconnect applications: (a) thick film photo-resist pillar, (b) micro-pillar in bulk silicon by deep reactive ion etching (DRIE), (c) micro-pillar grown from vertically aligned CNT arrays [19]. Transfer moulding technology is employed to, (d) encapsulate the micropillars creating through polymer vertical interconnects.. In Figure 2.3 we show a schematic overview of the metallization process and interconnect patterning of the TPV. As example we take a micro-pillar which is defined in photoresist. The following paragraphs discuss the steps in more detail.. 2.2.1. P ROCESSING THICK FILM PHOTO RESIST The first step consists of creating high-aspect ratio micro-pillars by patterning thick negative tone photo resist on a carrier substrate, see Figure 2.3 step 1. Two different types.

(26) 16. 2. T HROUGH P OLYMER V IAS. Thick-film photo-resist. 2. Substrate. Step 1: Lithographically define pillars on substrate/wafer using thick film photo-resist.. Step 2: Sputter conformal metal (seed) layer.. Masking with negative resist. Masking with positive resist. Step 3a: Exposure and development of spray-coated photo-resist.. Step 3b: Exposure and development of spray-coated photo-resist.. Step 4a: Bottom-up plating.. Step 4b: Etch metal layer.. Step 5a: Strip photo-resist and etch seed layer.. Step 54b: Strip photo-resist.. Figure 2.3: Flowchart showing the 2 parallel routes towards the fabrication of high-aspect-ratio metallized pillars on a carrier substrate.. of thick film photo-resists were used for the micro-pillar interconnect fabrication. The first type is the well-known SU8 negative-tone photo-resist that is available in a highviscosity liquid form with a solvent that requires spin coating for deposition. Some of the challenges are getting a uniform and consistent film thickness. However, we were able to spin coat 350 µm thick films at low 300 rpm levels for about 45 s and then a short high intensity spin at 2000 rpm for 5 s for edge-bead flattening. Another approach is the.

(27) 2.2. A PPROACH. 17. direct transfer moulding of resist onto the substrate, which could be a good approach to get a thick and more uniform film. Figure 2.4 shows several arrays of SU8 pillars. The pillars are about 350 µm tall and have lithographically defined diameters ranging from (5 ± 1) µm to (150 ± 1) µm. The maximum length to diameter L/D aspect ratio that results in highly vertical pillars is about 350:20. Pillars with a diameter of 10 µm, are deflected (see Figure 2.4) while the smaller 5 µm diameter pillars have released from the substrate. Ø=20 μm H=350 μm. Ø=10 μm H=350 μm. Ø=100 μm H=350 μm. Figure 2.4: Scanning-electron-microscopy (SEM) image of different aspect ratio polymer pillars after exposure and development of SU8 photo-resist. The thickness resist is about 350 µm. The pillars are metallized by sputtering aluminium at room temperature.. A second approach is the use of thick dry film (TDF) photo-resist sheets from SUEX®. This is a uniform solid resist coating between two layers of disposable polyester (PET) film in a 100 µm to 750 µm thickness range. A standard hot rolling lamination approach is used to apply the TDF resist sheets on the substrate, see Figure 2.5a. This allows for the imaging of the resist sheets within minutes and provides a coating with no edge bead and no solvent gradient through the film [20]. These major advantages make the new TDF photo-resist sheets a promising choice for the interconnect fabrication. Furthermore, the film assisted moulding technique combined with thick photo sensitive films allows for manufacturing of other through mould micro/macro-structures and channels. Consequently, the thick film resists combined with wafer-level-packaging can also be extended to other fields such as vertical microfluidic channels, vertical-optical-fibers and lab-on-a-chip. In addition, small dry-film photo-resist blocks can also be locally placed by pick and place equipment so that cost and material waste is further reduced. Figure 2.5b shows what can be achieved with laminated and exposed TDF photoresist. Studies of different photo-lithographic techniques consisting of wafer stepper. 2.

(28) 18. 2. T HROUGH P OLYMER V IAS. exposure and lithographic drilling versus contact aligner can lead to more novel shapes and structures. For example coax and triax vertical interconnects and tapered structures can be investigated. However, the current work is aimed at vertical interconnects for the. 2. microelectronics industry.. (a) Representative wafer being laminated by dry film (b) Scanning-electron-microscopy (SEM) image of photo-resist. Johnson et. al. [20]. dry film laminated photo-resist structures after exposure and development. Figure 2.5: Thick (350 µm) dry film photo-resist lamination procedure. The results shows that coaxial structures can be exposed in the negative tone photo-resist including a variety of other shapes and structures (Dimes and TUD logos).. 2.2.2. S ILICON PILLARS Silicon pillars were also fabricated in addition to polymer photo-resist based structures. The Si based pillars were prepared by deep reactive ion etching (DRIE) of a silicon wafer inside a SPTS DRIE Rapier etcher. As opposed to etching via holes inside the wafer, which is usually done for fabrication of through silicon vias, we etch the surrounding material (negative). As a result we obtain a thinned down silicon carrier wafer with protruding Si pillars. These samples were used as a Si interposer type of substrate suitable for higher temperatures as compared to the polymer pillars. The drawback of the Si pillar fabrication approach is the time consuming processing speed because of the sequential nature of the DRIE process.. 2.2.3. C ARBON NANOTUBE PILLARS Nanoscale materials, unlike bulk materials, are one of the few engineering materials that can be grown from the bottom up in a controlled manner. Here, the vertically aligned carbon nanotube (CNT) arrays in photo-lithographically defined patterns have been recognized as a promising structural material for the fabrication of high-aspect-ratio,.

(29) 2.2. A PPROACH. 19. 3D micro- and nano-architectures [19, 21]. Here, the porous nature of the CNT arrays allows for the unique opportunity to tailor their mechanical response and functionality by the infiltration and deposition of different nanoscale conformal coatings [19]. The first step consists of growing a 170 nm thick thermal silicon oxide layer on a silicon wafer substrate to prevent diffusion of the metal catalyst into the substrate. Next, a 15 nm thin layer of alumina (Al2 O3 ) is sputtered on the substrate to increase the CNT nucleation density from the catalyst particles [22]. Then a 2 nm thin layer of iron (Fe) catalyst is deposited on the Al2 O3 film by electron beam evaporation. The catalyst is patterned using optical lithography and a lift-off process. For the lift-off process we spin coat a film of 1.5 µm thick negative photo-resist (AZ Nlof2000) and use a NMP (C5 H9 NO) solvent at 70 ◦C for dissolving the resist during the lift-off. Next, (100 ± 2) µm tall vertically aligned multi-wall CNTs are grown in 5 minutes by low pressure chemical vapour deposition (LPCVD) in a commercial deposition system (Black Magic Pro, Aixtron). The CNTs are grown at a temperature of 600 ◦C using a gas flow mixture of 700 sccm hydrogen over 50 sccm acetylene (H2 /C2 H2 ) at 80 mbar. The CNT pillars are shown in, Figure 2.6. For these results we employed the same mask set as the photo-resist pillars and the DRIE etched silicon pillars. All three process allow for lithographically defined structures, the main difference being that the CNT process is relatively fast at the cost a higher processing temperature compared to the other methods.. Figure 2.6: On the left, SEM images of different aspect ratio CNT pillars including a high magnification image of the CNT array. On the right, photograph of the CNT pillars on wafer-level.. 2.2.4. T HIN FILM CONFORMAL METALLIZATION Metallization of polymer and high-aspect-ratio structures has been a challenging but important topic in various industries and academic research institutions for more than a century [23–25]. The common problems relate to mechanical stresses that can arise dur-. 2.

(30) 20. 2. T HROUGH P OLYMER V IAS. ing the multilayer fabrication and deposition of thin films. Therefore strong interfacial adhesion must be maintained in order to prevent de-lamination and achieve mechanical integrity. The adhesion of thin films depends on the formation of chemical bonds,. 2. mechanical interlocking and physical bonding at the interface [25]. Various techniques can be studied and applied to produce different quality conformal metallic layers on high-aspect-ratio polymer structures such as; physical vapour deposition (sputtering), atomic layer deposition (ALD) and electro-less/electro-chemical processes [23].Some of the different metallization routes for high aspect ratio through polymer vias (TPV) are shown in Figure 2.7. The following challenges need to be addressed to find robust, costeffective and reliable approaches for metallic film deposition on polymer structures: • Low temperature budget and appropriate coefficient of thermal expansion (CTE) mismatch • Limited out-gassing of the polymers in high vacuum deposition systems • Adhesion challenges between dissimilar materials • Conformity of the coating on high-aspect-ratio structures. C ONFORMAL METALLIZATION USING SPUTTERING Physical vapour deposition (PVD) or sputtering of metallic films onto the pillars is used to create a semi-conformal seed layer at low temperature. The sputtering system uses an ultra-high vacuum to reduce particle contamination and provide good quality films. Properties such as the thickness, step coverage and the grain structure can be controlled. Sputtering is a deposition technology where the material is removed from the source target at a lower temperature when compared to evaporation. The source target is bombarded inside a plasma causing atoms to release and condensate on the substrate surface. During the sputtering process, high-aspect-ratio pillars have the advantage over trenches due to their increased target visibility area. Their large exposed visibility area make pillars more suitable for conformal coating using sputtering. The structure of a sputtered film is strongly dependent on temperature. Consequently, a sputtering system provides temperature control of the chuck and wafers. Heat transfer from the wafer towards the chuck depends on the thermal conductivity of the materials, interfaces and the condensation heat of the sputtered material. Polymer based materials such as photo-resist micro pillars are sensitive to high temperatures and can be damaged. Here, polymers and thick films have a relatively high thermal resistance compared to standard bulk silicon processes which limits the heat flow. Therefore care should be taken with.

(31) 2.2. A PPROACH. 21. 2. Photo-resist pillar metallization routes. Seed-layer deposition. (Plasma-enhanced) atomic layer deposition of TiN. Physical Vapour Deposition of Cu, Al or other metals. Surface activation by Pd solution. Electro-less plating Au, Ag, Ni, Cu. Electroplating for thick film requirements. Electro-less plating for surface finish Figure 2.7: Illustration of the metallization routes of photo-resist structures..

(32) 22. 2. T HROUGH P OLYMER V IAS. respect to the metal deposition rate when metallizing polymers to avoid accumulation of heat and damage to the material. The main advantage of sputtering is that it provides a seed-layer that can be directly used for plating purposes since it doesn’t require acti-. 2. vation. Furthermore, the sputtered films have excellent adhesion to the substrates on which they are sputtered if we take care of a low cyclic deposition rate at room temperature. The polymer pillars are metallized using a Trikon Sigma sputter coater for the deposition of 1 micron Al saturated with 1%Si at 25 ◦C to prevent diffusion between the materials. To maintain a low temperature during deposition, we perform several deposition cycles of respectively 250 nm each. Between cycles a short pause is included which allows for cooling of the substrate and to protect damaging the polymer. The Si pillars were also metallized by sputtering. A standard recipe at higher temperature could be used because of the absence of organic compounds on the wafer. Figure 2.8 shows an example of a metallized silicon pillars with aluminium. The thickness of the metal layer is about 1 µm.. (a) SEM image showing an overview of the Si pillars (b) Overview of coplanar waveguide test structures and bottom interconnect layers after Al1Si sputterfor characterization of the TPV RF performance. ing and patterning. Figure 2.8: Scanning electron microscopy (SEM) images of metallized Si pillars at different magnifications.. The patterning of the bottom interconnect layer after metallization is performed using the process described in Figure 2.3 step 3b to step 5b. A conformal positive photoresist layer with thickness of about 6 µm is spray coated on the substrate and pillars. The layer is exposed using an ASML PAS5500 wafer-stepper. The stepper uses a lens to reduce the size and focus the image of the reticle on the bottom substrate. However, we observed a problem with exposure of the top-side of high-aspect ratio structures due to the beam angle of the image causing undesirable exposure, see Figure 2.9a. After etching.

(33) 2.2. A PPROACH. 23. of the metal layer, we noticed small damaged areas on which allowed for inspection of the side-wall thickness (Figure 2.9b). The grain boundaries of the aluminium are clearly visible. To solve the problem we gave the stepper a z-focus offset. This prevented damage to the top-side of the pillar but caused the bottom interconnect pattern to become less defined, see Figure 2.9c. For non-critical dimensions/structures this is not considered a problem.. Reticle Lens (not to scale). Focus offset. Undesired exposure Focus top plane (T). Out of focus exposure. (b) Undesired exposure (c) Well defined top side pillar. interconnect pattern.. Focus bottom plane (B). (a) Schematic illustration of the effects of focus offset during exposure.. (d) Top side undamaged. (e) Unsharp bottom interconnect pattern.. Figure 2.9: (a) Schematic illustration of the lithographic exposure with z-focus offset using an ASML PAS5500 wafer-stepper. Comparison between lithographic exposure with focus on the pillar top surface (b,c) versus focus on bottom substrate (d,e).. 2.2.5. WAFER - LEVEL - PACKAGING AND FILM ASSISTED MOULDING The film assisted moulding (FAM) process is schematically shown in Figure 2.10. The critical part of encapsulating the metallized pillars is that the pillars need to be clamped with sufficient pressure in order to keep the top-side clean from epoxy-moulding compound. Secondly, the pillar design needs to withstand the clamping pressure without structural collapse due to buckling or fracture. Furthermore, given that the epoxy moulding compound flow is perpendicular to the pillar orientation, high viscous forces can sweep the pillars away. Henceforth, lithographically defined pillar diameters ranging from (5 ± 1) µm to (150 ± 1) µm are included in the design, as to identify appropriate aspect-ratios. For critical pillar configurations, the lithographically enabled design freedom of the pillars enable optimized pillar shapes to minimize the impact of clamping force and fluid drag in the moulding process. Figure 2.10 shows a schematic illustration. 2.

(34) 24. 2. T HROUGH P OLYMER V IAS. 2. Figure 2.10: Schematic illustration of the film assisted moulding approach. (a) Film transport in open mould, (b) film vacuum forming, (c) loading of substrate with pillars, (d) mould closure and clamping, (e)-(f) mould filling with compound, (g) mould open and unloading (Video: Boschman FAM).. of the encapsulation process of the through polymer vias (TPV). Figure 2.11a shows the wafer with high aspect ratio metallized pillars being loaded inside the moulding cavity. A piston transfers the molten epoxy compound via several channels (runners) which are placed near the flat-edge of the Si wafer, inside the mould cavity. The moulding pressure ranges from 3 bar to 80 bar and the temperature is around 175 ◦C. When the mould cavity is filled, the curing of the EMC starts, which takes up to 90 s. Figure 2.11c shows a partially moulded wafer to demonstrate that delicate pillars with a high aspect-ratio of 20:350 survive the moulding and clamping process. Furthermore, the topside of pillars with different diameters remains clear of EMC. After encapsulation the packages with the through-polymer-interconnects are singulated by dicing the wafer in small (6x6 mm) dies, see Figure 2.11d. The cross-section.

(35) 2.2. A PPROACH. 25. 2. (a) The wafer with the vertical inter- (b) Close-up photograph of the metallized pillars connect pillars are shown inside a of differnt aspect ratio. moulding cavity. Ø=20 μm H=350 μm. Ø=100 μm H=350 μm. Ø=50 μm H=350 μm. (c) Partially moulded wafer to show that even the highest aspect ratio vias remain exposed and undamaged.. (d) Diced chip (6x6 mm) after VIA fabrica- (e) Cross-section showing 100µm diameter tion and wafer-level-packaging. TPVs going through the moulding compound. Figure 2.11: Wafer-level-packaging process showing the encapsulation of through-polymer-via pillars.Film assisted moulding is used to encapsulate the entire wafer and all vias in a single step.. reveals that the TPVs are going through the polymer moulding compound and are slightly sticking out (Figure 2.11e). This is caused by the low compliance of the film which is.

(36) 26. 2. T HROUGH P OLYMER V IAS. used in the film assisted moulding. It allows for the pillars to be pressed inside the film. As a consequence, the topside of the pillar will also be easily connected by a fan-out electrical routing layer or they might serve as micro-bumps for a flip-chip bonding step.. 2.3. C HARACTERIZATION To confirm the conformal deposition of metal on the micropillars we have measured the I-V curve from one pillar to another pillar using a 4-probe setup. The measurement and simulation results are shown in Figure 2.12a. Current is forced through the outer pillars (2 and 4) and the voltage drop is measured between the inner pillars (1 and 3) as is illustrated in the numerical model, Figure 2.12b. The extracted sheet resistivity of the aluminium film is about ρ = 2.7 ± 0.1 (Ω · m), which matches the bulk resistivity of aluminium. The measurements are repeatable and only show a small variation when the probes are repositioned.. 1.5 1 V1 − V3 (mV). 2. Simulation Markers indicate measurements. 0.5 0 -0.5 -1 -1.5 -100. -50. 0. 50. 100. Current (mA). (a) Four-probe electrical measurement com- (b) Finite element simulation of the 4-probe electrical repared to simulation. sistivity measurement. Figure 2.12: Four-probe electrical resistivity measurement and simulation. The inset shows the view in the probe station. 2.4. C ONCLUSION Different methods were employed to fabricate high aspect ratio and conductive micropillars to serve as through polymer via (TPV) interconnects. The pillars are succesfully incapsulated using thin film assisted wafer level packaging. Delicate high aspect ratio TPV structures (high aspect ratio ≥ 10) can be made in parallel, enabling electrical interconnects for high pin count packages. The use of film assisted moulding tech-.

(37) R EFERENCES. 27. nology is used to keep the top surface clean from epoxy bleed, which is indispensable for further electrical fan out routing. The TPV technology is applicable for 3D heterogeneous integration and packaging. Advantages of this technology are that pillars are 1.) more easily exposed and wetted by the plating solution than through holes vias. 2.) Metallization is faster than bottom-up plating due to the conformal seed layer. 3.) Lack of voiding and trapping of plating chemicals due to the exposed surfaces of the pillars. 4.) The position of the pillar vias is lithographically defined with high accuracy. Furthermore, the design freedom of using lithography, can enable the introduction of more complex through polymer structures and shapes with different functionality such as micro fluidic channels and optics. These advantages makes this technology promising for low-cost, large-scale parallel fabrication of micro-vias for 3D heterogeneous integration and packaging.. R EFERENCES [1] International Technology Roadmap for Semiconductors, Tech. Rep. (2013 Edition). [2] W. Chen, W. R. Bottoms, K. Pressel, and J. Wolf, The next step in assembly and packaging: System level integration in the package (sip), SiP White Paper V9.0 (2013). [3] G. Q. Zhang, M. Graef, and F. van Roosmalen, The rationale and paradigm of "more than moore", in Electronic Components and Technology Conference. Proceedings. 56th (2006) p. 7 pp. [4] W. Arden, M. Brillouet, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf, More-than-moore, White Paper (2013). [5] G. Zhang, W. Van Driel, and X. Fan, Mechanics of Microelectronics, Solid Mechanics and its Applications, Vol. 141 (Springer, 2006) p. 563. [6] L. Wang, A. Bos, T. van Weelden, and F. Boschman, The next generation advanced mems and sensor packaging, in Electronic Packaging Technology & High Density Packaging (ICEPTHDP), 2010 11th International Conference on, pp. 55–60. [7] W. Kim, J.-W. Bae, I.-D. Choi, and Y.-S. Kim, Thermally conductive emc (epoxy molding compound) for microelectronic encapsulation, Polymer Engineering & Science 39, 756 (1999). [8] Yole, 3DIC & TSV interconnects, Tech. Rep. (2012). [9] O. Chukwudi and et al., Influence of annealing conditions on the mechanical and microstructural behavior of electroplated cu-tsv, Journal of Micromechanics and Microengineering 20, 045032 (2010). [10] L. J. Ladani, Numerical analysis of thermo-mechanical reliability of through silicon vias (tsvs) and solder interconnects in 3-dimensional integrated circuits, Microelectronic Engineering 87, 208 (2010).. 2.

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(41) 3 TAILORING THE M ECHANICAL P ROPERTIES OF C ARBON N ANOTUBE A RRAYS USING A -S I C C OATINGS The porous nature of carbon nanotube (CNT) arrays allows for the unique opportunity to tailor their mechanical response by the infiltration and deposition of nano-scale conformal coatings. Here, we fabricate novel photo-lithographically defined CNT pillars that are conformally coated with amorphous silicon carbide (a-SiC) to strengthen the interlocking of individual CNTs at junctions using low pressure chemical vapour deposition (LPCVD). We further quantify the mechanical response by performing flat-punch nanoindentation measurements on coated CNT pillars with various high-aspect-ratios. We discovered new mechanical failure modes of coated CNT pillars, such as "bamboo" and brittle-like composite rupture as coating thickness increases. Furthermore, a significant increase in strength and modulus is achieved. For CNT pillars with high aspect ratio (1:10) and coating thickness of 21.4 nm, the compressive strength increases by an order of magnitude of 3, towards 1.8 GPa (from below 1 MPa for uncoated CNT pillars) and the elastic modulus increases towards 125 GPa. These results show that our coated CNT pillars, which can serve as vertical interconnects and 3D super-capacitors, can be transformed into robust high-aspect-ratio 3D-micro architectures. Parts of this chapter have been published in Advanced Functional Materials 24, 36 (2014) [1].. 31.

(42) 32. 3. TAILORING THE M ECHANICAL P ROPERTIES OF C ARBON N ANOTUBE A RRAYS USING A -S I C C OATINGS. 3.1. I NTRODUCTION Vertically aligned carbon nanotube (CNT) arrays or forests in photo-lithographically defined patterns have been recognized as a promising structural material for the fabrication of high-aspect-ratio, three-dimensional (3D) micro- and nano-architectures [2–6]. The exceptional properties of CNTs and related materials have triggered tremendous efforts not only to study their intrinsic properties but also to explore their applications. 3. in a large variety of fields [7–14]. These high-aspect-ratio 3D structures play an important role in the advancement of vertical interconnect technology [15–18], flexible batteries [4], stamps for micro/nanoimprint lithography [3, 19–22], compliant thermal interface materials for low inter-facial resistances [23–26], 3D super-capacitors [27, 28] and nano/micro-electromechanical systems (NEMS) and (MEMS) [2, 29–31]. The CNT arrays that we refer to in this work are composed of nominally vertical, interwoven, multi-wall carbon nanotubes [32, 33]. A common procedure for growing high-aspect-ratio CNT arrays is via chemical vapor deposition (CVD) on photo-lithographically defined catalyst areas [6, 10]. One of the limitation of this growth process, is the low packing density of the CNTs inside the array [16, 34]. The interwoven CNTs inside the array are held together by a weak van der Waals interaction, allowing tubes to slide along each other [35, 36]. The combination of low packing density and weak inter-tube forces, results in mechanical properties of CNT arrays that are significantly inferior to individual CNTs [7, 36]. Consequently, a considerable amount of effort is going into the development of new methods to optimize the full potential of individual CNTs in low density CNT arrays, either by densification or application of conformal coatings. A literature overview of coated nanoscale architectures can be found in [37]. Recent and remarkable examples of conformally coated CNT arrays include e.g., deposition of silicon coatings to create a flexible anode architecture for high-energy-density-batteries [4] and graphene coatings to create superelastic, lightweight and fatigue resistant aerogels [8]. Silicon carbide also proves to be an interesting coating material, mainly due to its diamond like characteristics [38]. The properties of SiC are especially attractive in applications which require contact, high temperatures, chemical inertness, high robustness, electrical conductivity and high resistance to electron beam damage [39–42]. Bulk composites containing SiC-coated CNTs have been produced by chemical vapour infiltration and were tested by bending and a pull-out method. One remarkable result was the protection of CNTs from being oxidized at 1600 ◦C in air for 1 hour [43]. Investigations have also shown that SiC-coated multi-walled CNTs dispersed in composites increase fracture toughness and hardness [44]. The porosity of CNT arrays allows for infiltration.