5 System Control
4. If there is valid data at address 0x0000.0004, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.000
5.2.5 Clock Control
5.2.5.2 Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the RCC register is required, include another register access after writing the RCC register and before writing the RCC2 register.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set withPWMDIVin RCC).
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.
Figure 5-5. Main Clock Tree
Main OSC
Precision Internal OSC
(16 MHz)
Internal OSC (30 kHz)
÷ 4
÷ 25
PWRDN
ADC Clock System Clock MOSCDISa
IOSCDISa
SYSDIVe
USESYSDIVa,d PWMDWa
USEPWMDIVa
PWM Clock
Hibernation OSC (32.768 kHz)
OSCSRCb,d
BYPASSb,d XTALa
PWRDNb
÷ 2 USB PLL
(480 MHz) ÷ 4 USB Clock
XTALa USBPWRDNc
RXINT
RXFRAC I2S Receive MCLK
I2S Transmit MCLK
PLL (400 MHz)
TXINT TXFRAC
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bitUSERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC registerSYSDIVfield, RCC2 registerSYSDIV2field if overridden withUSERCC2bit, or [SYSDIV2,SYSDIV2LSB] if bothUSERCC2andDIV400bits are set.
DIV400c
Note: The figure above shows all features available on all Stellaris® Firestorm-class microcontrollers. Not all peripherals may be available on this device.
Using the SYSDIV and SYSDIV2 Fields
In the RCC register, theSYSDIVfield specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASSbit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-5 shows how theSYSDIVencoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to theSYSDIVencoding plus 1. For a list of possible clock sources, see Table 5-4 on page 189.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
StellarisWare®Parametera Frequency (BYPASS=1)
Frequency (BYPASS=0) Divisor
SYSDIV
SYSCTL_SYSDIV_1b Clock source frequency/2
reserved /1
0x0
SYSCTL_SYSDIV_2 Clock source frequency/2
reserved /2
0x1
SYSCTL_SYSDIV_3 Clock source frequency/3
66.67 MHz /3
0x2
SYSCTL_SYSDIV_4 Clock source frequency/4
50 MHz /4
0x3
SYSCTL_SYSDIV_5 Clock source frequency/5
40 MHz /5
0x4
SYSCTL_SYSDIV_6 Clock source frequency/6
33.33 MHz /6
0x5
SYSCTL_SYSDIV_7 Clock source frequency/7
28.57 MHz /7
0x6
SYSCTL_SYSDIV_8 Clock source frequency/8
25 MHz /8
0x7
SYSCTL_SYSDIV_9 Clock source frequency/9
22.22 MHz /9
0x8
SYSCTL_SYSDIV_10 Clock source frequency/10
20 MHz /10
0x9
SYSCTL_SYSDIV_11 Clock source frequency/11
18.18 MHz /11
0xA
SYSCTL_SYSDIV_12 Clock source frequency/12
16.67 MHz /12
0xB
SYSCTL_SYSDIV_13 Clock source frequency/13
15.38 MHz /13
0xC
SYSCTL_SYSDIV_14 Clock source frequency/14
14.29 MHz /14
0xD
SYSCTL_SYSDIV_15 Clock source frequency/15
13.33 MHz /15
0xE
SYSCTL_SYSDIV_16 Clock source frequency/16
12.5 MHz (default) /16
0xF
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source.
TheSYSDIV2field in the RCC2 register is 2 bits wider than theSYSDIVfield in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to theSYSDIV2encoding plus 1. Table 5-6 shows how theSYSDIV2encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-4 on page 189.
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
StellarisWare Parametera Frequency (BYPASS2=1)
Frequency (BYPASS2=0) Divisor
SYSDIV2
SYSCTL_SYSDIV_1b Clock source frequency/2
reserved /1
0x00
SYSCTL_SYSDIV_2 Clock source frequency/2
reserved /2
0x01
SYSCTL_SYSDIV_3 Clock source frequency/3
66.67 MHz /3
0x02
SYSCTL_SYSDIV_4 Clock source frequency/4
50 MHz /4
0x03
SYSCTL_SYSDIV_5 Clock source frequency/5
40 MHz /5
0x04
...
...
...
...
...
SYSCTL_SYSDIV_10 Clock source frequency/10
20 MHz /10
0x09
...
...
...
...
...
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued)
StellarisWare Parametera Frequency (BYPASS2=1)
Frequency (BYPASS2=0) Divisor
SYSDIV2
SYSCTL_SYSDIV_64 Clock source frequency/64
3.125 MHz /64
0x3F
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source.
To allow for additional frequency choices when using the PLL, theDIV400bit is provided along with theSYSDIV2LSBbit. When theDIV400bit is set, bit 22 becomes the LSB forSYSDIV2. In this situation, the divisor is equivalent to the (SYSDIV2encoding withSYSDIV2LSBappended) plus one. Table 5-7 shows the frequency choices whenDIV400is set. When theDIV400bit is clear, SYSDIV2LSBis ignored, and the system clock frequency is determined as shown in Table 5-6 on page 192.
Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1
StellarisWare Parameterb Frequency (BYPASS2=0)a
Divisor SYSDIV2LSB
SYSDIV2
-reserved
/2 reserved
0x00
-reserved
/3 0
0x01 1 /4 reserved
-SYSCTL_SYSDIV_2_5 80 MHz
/5 0x02 0
SYSCTL_SYSDIV_3 66.67 MHz
/6 1
-reserved
/7 0
0x03
SYSCTL_SYSDIV_4 50 MHz
/8 1
SYSCTL_SYSDIV_4_5 44.44 MHz
/9 0
0x04
SYSCTL_SYSDIV_5 40 MHz
/10 1
...
...
...
...
...
SYSCTL_SYSDIV_63_5 3.15 MHz
/127 0
0x3F
SYSCTL_SYSDIV_64 3.125 MHz
/128 1
a. Note thatDIV400andSYSDIV2LSBare only valid whenBYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.