3 Cortex-M3 Peripherals
3.1 Functional Description
3.1.4 Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 81 for more information).
Table 3-2 on page 106 shows the possible MPU region attributes. See the section called “MPU Configuration for a Stellaris Microcontroller” on page 110 for guidelines for programming a microcontroller implementation.
Table 3-2. Memory Attributes Summary
Description Memory Type
All accesses to Strongly Ordered memory occur in program order.
Strongly Ordered
Memory-mapped peripherals Device
Normal memory Normal
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1 Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using anSTMinstruction.
Updating an MPU Region Using Separate Words This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address STRH R2, [R0, #0x8] ; Region Size and Enable STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then aDSBinstruction and anISBinstruction should be used. ADSBis required after changing MPU settings, such as at the end of context switch. AnISBis required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then anISBis not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable AnSTMinstruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that the MPU Region Base Address (MPUBASE) register (see page 164) contains the required region number and has theVALIDbit set. This method can be used when the data is statically packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in theSRDfield of the MPU Region Attribute and Size (MPUATTR) register (see page 166) to disable a subregion. The least-significant bit of theSRDfield controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, theSRD field must be configured to0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure theSRDfield for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 109 shows.
Figure 3-1. SRD Use Example
Region 1
Disabled subregion Disabled subregion
Region 2, with subregions
Base address of both regions
Offset from base address
0 64KB 128KB 192KB 256KB 320KB 384KB 448KB 512KB
3.1.4.2 MPU Access Permission Attributes
The access permission bits,TEX,S,C,B,AP, andXNof the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault.
Table 3-3 on page 109 shows the encodings for theTEX,C,B, andSaccess permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Stellaris Microcontroller” on page 110 for information on programming the MPU for Stellaris implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
Other Attributes Shareability
Memory Type B
C S
TEX
-Shareable
Strongly Ordered 0
0 xa 000b
-Shareable
Device 1
0 xa 000
Outer and inner write-through. No write allocate.
Not shareable Normal
0 1 0
000
Shareable Normal
0 1 1
000
Not shareable Normal
1 1 0
000
Shareable Normal
1 1 1
000
Outer and inner noncacheable.
Not shareable Normal
0 0 0
001
Shareable Normal
0 0 1
001
-Reserved encoding 1
0 xa 001
-Reserved encoding 0
1 xa 001
Outer and inner write-back. Write and read allocate.
Not shareable Normal
1 1 0
001
Shareable Normal
1 1 1
001
Nonshared Device.
Not shareable Device
0 0 xa 010
-Reserved encoding 1
0 xa 010
-Reserved encoding xa
1 xa 010
Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
Other Attributes Shareability
Memory Type B
C S
TEX
Cached memory (BB = outer policy, AA = inner policy).
See Table 3-4 for the encoding of the AA and BB bits.
Not shareable Normal
A A 0
1BB
Shareable Normal
A A 1
1BB
a. The MPU ignores the value of this bit.
Table 3-4 on page 110 shows the cache policy for memory attribute encodings with aTEXvalue in the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Corresponding Cache Policy Encoding, AA or BB
Non-cacheable 00
Write back, write and read allocate 01
Write through, no write allocate 10
Write back, no write allocate 11
Table 3-5 on page 110 shows theAPencodings in the MPUATTR register that define the access permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
Description Unprivileged
Permissions Privileged
Permissions APBit Field
All accesses generate a permission fault.
No access No access
000
Access from privileged software only.
No access R/W
001
Writes by unprivileged software generate a permission fault.
RO R/W
010
Full access.
R/W R/W
011
Reserved.
Unpredictable Unpredictable
100
Reads by privileged software only.
No access RO
101
Read-only, by privileged or unprivileged software.
RO RO
110
Read-only, by privileged or unprivileged software.
RO RO
111
MPU Configuration for a Stellaris Microcontroller
Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 110.
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers
Memory Type and Attributes B
C S TEX
Memory Region
Normal memory, non-shareable, write-through 0
1 0 000b
Flash memory
Normal memory, shareable, write-through 0
1 1 000b
Internal SRAM
Normal memory, shareable, write-back, write-allocate
1 1 1 000b
External SRAM
Device memory, shareable 1
0 1 000b
Peripherals
In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations.
3.1.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 79 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 151 for more information.