110 Port Address: 374 IW.! Desriptjog 7 (msb)
-unused-6 -un
used-5 -un~
~ ResetD!
4' CRTC Index Bit-4 PJW
3 CRTC Index Bit-3 RJW
2 CRTC Index Bit-2 RJW
1 CRTC Index Bit-l PJW
o
(Isb) CRTC Index Bit-O RJWReset State
The CRTC Index register points to the internal registers of the CRT Controller. The five least significant bits detennine which register will be pointed to in the next register read/write operation to 110 port 3B5/3D5.
Since only 5 bits of index register are currently implemented, CRTC registers O-IF may also be addressed using index ranges 20-3F, 4O-5F, 60-7F, 80-9F, AO-BF, CO-DF, and EO-FF. This, however, is not recommended, as higher index ranges are resrved for future use and this may not be true in fuure chip revisions.
The same index register is used for access to both CRTC registers (VGAJEGA mode) and 6845 registers (CMGA modes).
Revision A, 5/89 7-2 VGAIEGA CRT Controller Registers
Cirrus Logic 610/620 Technical Reference Manual
7.2 CRTC Horizontal Total Register: CRO
va
Port ft ddress: 3?5 Index: Of.Protecti' ,its: WRC[O]
Ili1.1t DescriptjoD
7. (msb) Horizontal Total Bit-7 6 Horizontal Total Bit-6 5 timing. All horizontal and vertical timings are based upon the contents of this register.
The value in the register = Total Number of Characters - 2.
Note: This register is effective only in EGNVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
A-CR6 (V Total)
I-Horizontal Retrace (Sync) J-Display Blanked
K-Left Border
Revision A, 5/89
A B C D
Figure 7-1: CRTC Timing Registers
CRO (H T 0 tal)
""""""""'~~,~~~~,~~~~"""""""""""'"'"
". ~,....
, , 'T~ Border
7 - 3 VGAIEGA CRT Controller Registers
Cirrus Logic 610/620 Technical Reference Manual
7.3 CRTC Horizontal Display End Register: CRt
I/O Port Address: 3?S Index: 01
Protection Bits: WRC[ 1]
Ili1.! Description ~ Rest By Reset State
7 (msb) HOOzontal Display End Bit-7 R/W 6 Horizontal Display End Bit-6 R/W S Horizontal Display End Bit-S R/W 4 Horizontal Display End Bit-4 R/W 3 Horizontal Display End Bit-3 R/W 2 Horizontal Display End Bit-2 R/W 1 Horizontal Display End Bit-l R/W
o (Isb) Hmzontal Display End Bit-O R/W
The Horizontal Display Enable End register defines the total number of displayed charac-ters in a horizontal line.
The value in ~e register
=
Total Number of Characters - 1.Refer to Figure 6-1 (see register CRO) for a summary ofCRTC timing registers.
Note: This register is effective only in EGAlVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
Revision A, 5/89 7-4 VGAIEGA CRT Controller Registers
Cirrus Logic 610/620 Technical Reference Manual
7.4 CRTC Horizontal Blanking Start Register: CRl
va
Port Address: 3'?S Index: 02Protection Bits: WRC[O]
Jli1it Description MwI Reset By Reset State
, (msb) Horizontal Blanking Start Bit-' R/W 6 Horizontal Blanking Start Bit-6 RJW S Horizontal Blanking Start Bit-S RJW 4 Horizontal Blanking Start Bit-4 RIW 3 Horizontal Blanking Start Bit-3 RIW 2 Horizontal Blanking Start Bit-2 RJW 1 Horizontal Blanking Start Bit-l RJW
o (Isb) Horizontal Blanking Stan Bit-O RJW
The contents of this register defme the time when the horizontal blanking will start. The register is defmed in tenns of the number of horizontal character clocks assuming character positions are ~umbered O-n where position 0 is the frrst displayed character position at the left side of the screen. The horizontal blanking signal becomes active when the horizontal character count is equal to the contents of this register.
The underline scan line decode output is multiplexed on the cursor output during the blank-ing period. The underline signal is valid for one character count beyond the end of the blanking signal.
Refer to Figure 6-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGAlVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter StateJ Register).
Revision A, 5/89 7-5 VGAlEGA CRT Controller Registers
Cirrus Logic 610/620 Technical Reference Manual
7.5 CRTC Horizontal Blanking End Register: CRJ
110 Port Address: 315 Index: 03
Protection Bits: WRC[O]
Bi11t Description ~ Reset By Reset State
7 (msb) UGHTPEN compatibility readback RJW
6 Display Enable Skew Control RJW
S Display Enable Skew Control RJW
4 Horizontal Blanking End Bit-4 RJW
3 Horizontal Blanking End Bit-3 RJW
2 Horizontal Blanking End Bit-2 RJW
1 Horizontal Blanking End Bit-l RJW·
o
(Is b) Horizontal Blanking End Bit-O RJWThe contents of this register defme the time when the horizontal blanking will end. The register is defmed in tenns of the number of horizontal character clocks assuming character positions are nu~bered O-n where position 0 is the fJISt displayed character position at the left side of the screen.
The underline scan line decode output is multiplexed on the cursor output during the blank-ing period. The underline signal is valid for one character count beyond the end of the blanking signal.
Bit Descriptions
Bit 6-S Display Enable Skew Control
Prior to displaying data on the screen, the CRT controller has to access the
~is skew. The skew can be programmed from 0-3 character clocks as follows:
12§
JH
Skew in character clockso
0 0o
1 1 <-typical setting1 0 2
1 . 1 3
Bit 4-0 End Horizontal Blanking
The horizontal blanking signal width is detennined as follows:
Value in Start Blanking Register (R2) + Width of Blanking Signal W = 5-bit value to be programmed into the End Horizontal Blanking register.
The least five significant bits of the horizontal character counter are compared with the contents of this register. When a match occurs, the horizontal blanking pulse becomes inactive. Note that the five bits of this register limit the length of the blanking pulse to 31 character clocks. Note also that if the blanking interval extends beyond the end of the line, erratic behavior will result since the horizontal character counter gets cleared after the number of character times programmed in the horizontal total register.
Refer to Figure 6-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGAJVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
Revision A, 5/89 7-6 VGAIEGA CRT Controller Registers
-.
Cirrus Logic 610/620 Technical Reference Manual
7.6 CRTC Horizontal Retrace Start Register: CR4
I/O Port Address: 3?S Index: 04
Protection Bits: WRC[O]
lli1.1t Deseri plioo Reset By Reset State 7 (msb) Haizontal Retrace Start Bit-7
6 Horizontal Retrace Start Bit-6 5 Horizontal Retrace Start Bit-S 4
3 2
Horizontal Retrace Start Bit-4 Hcriz.on tal Retrace Start Bit -3 Horizontal Retnce Start Bit-2
RJW RJW RIW RJW RJW 1 Horizontal Retrace Start Bit-l RJW
o
(Isb) Horizontal Retrace Start Bit-O RJWThis register defmes the character position at which the Horizontal Retrace Pulse becomes active assuming character positions are numbered O-n where position 0 is the flI'St dis-played character position at the left side of the screen. This register centers the monitor screen horizontally. The value in the register is the character count at which the Horizontal Retrace Pulse becomes active.
Refer to Figure 6-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGA/VGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
Revision A, 5/89 7-7 VGAIEGA CRT Controller Registers
Cirrus Logic 610/620 Technical Reference Manual
7.7 CRTC Horizontal Retrace End Register: CRS
]/0 Port Address: 315 Index: 05
Protection Bits: WRC[O]
Ilil! DacriptioQ Awa Reset By Reset State
7 (msb) Hcxizontal Retrace End Bit-7 RJW
6 Horizontal Retrace End Bit-6 RJW
S 4 3 2
Horizontal Retrace End Bit~S
Horizontal Retrace End Bit-4
This register defines the character position at which the Horizontal Retrace Pulse becomes inactive assuming character positions are numbered O-n where position 0 is the fll"St dis-played character position at the left side of the screen.
Bit Descriptions
Bit 7 Start Odd Memory Address: This bit determines the CRT memory address after a horizontal retrace. 0 selects an even address, and 1 selects an odd address. In most cases this bit should be set to O. This bit is useful-in applications where hor-izontal pixel panning is required.
Bit 6-S Horizontal Retrace Delay: The skew of the horizontal retrace signal is controlled signal is detennined as follows:
Value in Retrace Start Register (CR4) + Width of Retrace Signal W = 5-bit value to be programmed into the Horizontal Retrace End register.
The five Isbs of the horizontal character counter are compared to the contents of this register. When a match occurs, the horizontal retrace pulse becomes inac-tive. Note that the five bits of this register limit the length of the retrace signal to 31 character clocks. Note also that if the retrace interval extends beyond the end of the line, erratic behavior will result since the horizontal character counter gets cleared after the number of character times programmed in ·the horizontal total reg-ister.
Refer to Figure 6-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGAJVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
Revision A, 5/89 7-8 VGAlEGA CRT Controller Registers
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Cirrus Logic 610/620 Technical Reference Manual
7.8 CRTC Vertical Total Register: CR6
I/O Port Address: 315Index: 06
Protection Bits: WRC[O]
B.iU Description 7 (msb) Vertical Total Bit-7 6 Vertical Total Bit-6 S
4 3 2
Vertical Total Bit-S Vertical Total Bit-4 Vertical Total Bit-3 Vertical Total Bit-2
Ailla RJW RJW RJW RJW RJW RJW
1 Vertical Total Bit-l RJW
o
(Isb) Vertical Total Bit-O RJWRest By Rest State
The Vertical Total register defmes the number of horizontal raster scans on the CRT screen, including the vertical retrace. The Vertical Total register contains the low order 8 bits of a 9-bit register. The ninth bit is located in the CRT Cont;roller Overflow register (CR 7 bit-O).
Refer to Figure 6-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGAJVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
Revision A, 5/89 7-9 VGAIEGA CRT Controller Registers
Cirrus Logic 610/620 Technical Reference Manual
7.9 CRTC Overflow Register: CR7
I/O Port Address: 315 Index: 07
Protection Bits: WRC[ 1 :0]
B.l1.! DaqiptioD
7 (nub) -un
used-6
-unused-5
-unused-Protected By Awa Reset By Reset State
4 Bit-8 of Line Compare Reg (CRIB) WRC[1] RJW
3 Bit-8 of Vertical Blanking Start Reg (CR 15) WRC[O] RJW 2 Bit-8 of Vertical Retrace Reg (CRIO) WRC[O] RJW I Bit-8 of Vertical Display End Reg (CRI2) WRC[1] RlW
o (Isb) Bit-8 of Vertical Total Reg (CR6) WRC[O] RlW
The CRT Controller Overflow register is used in conjunction with other control registers and contains the ninth bit (D8) of these registers.
The bits of this register are write protected by ones in bits 0 and 1 of the Extensions Write Control (WRC) Register (extensions index 84). .
Note: This register is effective only in EGAlVGA mode (see the description of 610/620 VGA extension register ER2F, the 'Active Adapter State' Register).
Revision A, 5/89 7 - 10 VGAIEGA CRT Controller Registers
7.10
Cirrus Logic 610/620 Technical Reference Manual