I/O Port Address: 3C5 Index: 8E
!ill..! Description M£.m Reset By Reset State 7 (msb) G/A Chip Revision Bit-7 R
6 G/A Chip Revision Bit-6 R
S G/A Chip Revision Bit-S R
4 G/A Chip Revision Bit-4 R
3 G/A Chip Revision Bit-3 R
2 G/A Chip Revision Bit-2 R
1 G/A Chip Revision Bit-1 R
o
(lsb) G/A Chip Revision Bit-O RThe G/A chip revision is detennined by reading back this register.
The value returned will be flXed for each revision of the chip.
The value retuq1ed is OAFb for chip revision 'A'.
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10.16 Extensions SIC Chip Revision Register: SCREV
I/O Pon Address: 3C5Index: 8F
!!il.! Description Attm Reset By Reset State 7 (msb) SIC Chip Revision Bil-7 R
6 SIC Chip Revision Bil-6 R
S SIC Chip Revision Bil-S R
4 SIC Chip Revision Bil-4 R
3 SIC Chip Revision Bil-3 R
2 SIC Chip Revision Bil-2 R
1 SIC Chip Revision Bil-l R
o
(lsb) SIC Chip Revision Bil-O RThe SIC chip revision is detennined by reading back this register.
The value returned will be fixed for each revision of the chip.
The value returned is OAFh for chip revision 'A'.
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Cirrus Logic 610/620 Technical Reference Manual
10.17 Vertical Retrace Start: CRIO
110 Port Address: 3C5 Index: 90
ID1J Description
1 (msb) Vertical Retrace Start Bit-1 6 Vertical Retrace Start Bit-6 S Vertical Retrace Start Bit-S 4 Vertical Retrace Start Bit-4 3 Vertical Retrace Start Bit-3 2 Vertical Retrace Start Bit-2 1 Vertical Retrace Start Bit-l
J?~ Ace§! J~~ AcceSi
W RIW
W R/W
W R/W
W RJW
W RJW
W RJW
W R/W
o (Isb) Vertical Retrace Start Bit-O W R/W
RfSi B! R~Sl Stat$
The Vertical Retrace Start register is a 9-bit address which defines the position of the ver-tical retrace start signal in terms of horizontal scan lines assuming the scan lines are num-bered starting from 0 at the top of the screen. The low order 8 bits are programmed through this register, while the high order ninth bit is programmed through the CRTC Overflow reg-ister (CR7 bit-2).
This register is normally accessed at CRTC index 10 as a write-only register (read-back at this index returns the Light Pen High Address Register). The Eagle VGA also allows read/write access at extensions index 90 for state save and restore.
Refer to Figure 7-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGA/VGA mode (see the description of Eagle VGA extension register ER2F, the 'Active Adapter State' Register).
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Cirrus Logic 61 0/620 Technical Reference Manual
10.18 Vertical Retrace End: CRll
I/O Pon Address: 3C5 Index: 91
lUl! Desrfption ~1~A"m 3C5 Acqss Rmt By Reset State
7 (msb) Q.Normal. l=Test W R/W
6 O=Normal. l=Test W R/W
5 O=Enable Venical Interrupt W R/W Reset 1
4 O=Clear Vertical Interrupt W R/W Reset 0
3 Vertical Retrace End Bit-3 W R/W
2 Vertical Retrace End Bit-2 W R/W
1 Vertical Retrace End Bit-I W R/W
o
(Isb) Vertical Retrace End Bit-O W R/WThis register is nonnally accessed at CRTC index 11 as a write-only register (read-back at this index returns the Light Pen Low Address Register). The EEGANGA also allows read/write access at extensions index 91 for state save and restore~
Bit Descriptions Bit 7 Test
For nonna! operation this bit must be set to "0". This bit is ignored by the Eagle VGA.
Bit 6 Test
For normal operation this bit must be set to "0" .Setting this· bit to I causes line counter bits 7-8 to be forced to 1 '5 ('684S-compatibility' mode). This capability is never used.
Bit S A "0" will enable the vertical interrupt of the CRT Controller. (See Input Status Register 0 bit-7 at pan address 3C2).
Bit 4 Oear Vertical Interrupt
This bit clears the vertical interrupt generated on the CRTINT output of the CRT controller. A "0" will clear the interrupt
Bit 3-0 Vertical Retrace End
These 4 bits specify the horizontal scan line count at which the vertical retrace output pulse becomes inactive assuming the scan lines are numbered starting from 0 at the top of the screen. The four bits are compared with the four least sig-nificant bits of the vertical scan line counter. When the four counter bits are equal to the contents in this register, the vertical retrace is terminated. The Width W of the vertical retrace pulse can be detennined from the following algorithm:
Value of Stan Vertical Retrace register (CRIO) + W = 4-bit value to be
pro-IJ'III11DCd
into the Vertical Retrace End register.Noce that the four least significant bits of the algorithm result are to be pro-grammed into this register. Thus the maximum retrace pulse width can only be 15 scan lines. Note also that if the blanking interval extends beyond the end of the screen, erratic behavior will result since the vertical scan line counter gets cleared after the number of scan lines programmed in the vertical total register.
Refer to Figure 7-1 (see register CRO) for a summary of CRTC timing registers.
Note: This register is effective only in EGANGA mode (see the description of Eagle VGA extension register ER2F, the 'Active Adapter State' Register).
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Cirrus Logic 610/620 Technical Reference Manual
10.19 Light Pen High: LPENH
UO Pon Address: 3CS Index: 92
!liU Description 315 Access 3C5 Access Rest By Reset State
7 (msb) Light Pen Address Bit-IS R R/W
6 Light Pen Address Bit-14 R R/W
5 Light Pen Address Bit-13 R RNI
4 Light Pen Address Bit-12 R R/W
3 Light Pen Address Bit-II R RNI
2 Light Pen Address Bit-IO R RNI
I Light Pen Address Bit-9 R RJW
o (Isb) Light Pen Address Bit-8 R RJW
The Light Pen High register contains the 8 high-order bits of the memory address at the time the light pen flip flop is set. The low order 8 bits are stored in the Light Pen Low reg-ister (LPENL at CRTC index 11). The LPENH and LPENL regreg-isters are nonnally read-only at CRTC index 10 and 11. However, the Eagle VGA also allows these registers to be accessed R/W at extension index 92 and 93 for state save and restore.
Refer to SLPEN and CLPEN for further information on loading the LPENH and LPENL
reg-isters.
.
This register is used in both CMGA and EGANGA modes (the two msbs are always loaded with 0 when the 6845 is active since the 6845 memory address register is only 14 bits wide).
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Cirrus Logic 610/620 Technical Reference Manual