3 Device Pins
MCB_CLKR
MM: MUX1
McBSP Receive Clock I/O MCA[1]
MCA[1]_AXR[3]/ IPD PINCNTL38
N6 I/O
MCB_CLKR DVDD DSIS: PIN
MM: MUX0 MCA[0], MCB
MCA[0]_AXR[8]/ IPD PINCNTL29
MCB_FSX/ L1 I/O
DVDD DSIS: PIN
MCB_FSR MM: MUX1
McBSP Receive Frame Sync I/O MCA[1], MCB
MCA[1]_AXR[2]/ R3 I/O IPD PINCNTL37
MCB_FSR DVDD DSIS: PIN
MM: MUX0 MCA[0]
MCA[0]_AXR[6]/ IPD
M4 I/O PINCNTL27 McBSP Receive Data Input
MCB_DR DVDD DSIS: PIN
MCA[0]_AXR[9]/ MCA[0], MCB
MCB_CLKX/ M6 I/O IPD PINCNTL30 McBSP Transmit Clock I/O
MCB_CLKR DVDD DSIS: PIN
MCA[0]_AXR[8]/ MCA[0], MCB
MCB_FSX/ L1 I/O DVDDIPD PINCNTL29 McBSP Transmit Frame Sync I/O
MCB_FSR DSIS: PIN
MCA[0]
MCA[0]_AXR[7]/ L2 I/O IPD PINCNTL28 McBSP Transmit Data Output
MCB_DX DVDD
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
SIGNAL
TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
PCIE_TXP0 AD2 O PCIE Transmit Data Lane 0.
–
When the PCIe SERDES are powered down, these pins should be VDDA_PCIE_1P8
PCIE_TXN0 AD1 O
left unconnected.
PCIE_RXP0 AC2 I PCIE Receive Data Lane 0.
–
When the PCIe SERDES are powered down, these pins should be VDDA_PCIE_1P8
PCIE_RXN0 AC1 I
left unconnected.
– PCIE Serdes Reference Clock Inputs and optional SATA
SERDES_CLKP AF1 I SERDES_CLK LDO
Reference Clock Inputs.
(internal)
Shared between PCI Express and Serial ATA. When PCI Express – is not used, and these pins are not used as optional SATA SERDES_CLKN AF2 I SERDES_CLK LDO Reference Clock Inputs, these pins can be left unconnected.
(internal)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
3.2.14 Reset, Interrupts, and JTAG Interface
Table 3-25. RESET, Interrupts, and JTAG Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
RESET
IPU –
RESET J5 I Device Reset input
DVDD PINCNTL260
POR F1 I – – Power-On Reset input
DVDD
Reset output (RSTOUT) or watchdog out (WD_OUT)
DIS –
RSTOUT_WD_OUT K6 O DVDD PINCNTL262 For more detailed information on RSTOUT_WD_OUT pin behavior, seeSection 7.3.14, RSTOUT_WD_OUT Pin.
INTERRUPTS
IPU –
NMI H7 I Non-Maskable Interrupt input
DVDD PINCNTL261
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP0[31:0] I/O
Table 3-10 NOTE Table 3-10 SeeTable 3-10, GP0 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP1[31:0] I/O
Table 3-11 NOTE Table 3-11 SeeTable 3-11, GP1 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP2[31:0] Table 3-12 I/O NOTE Table 3-12 SeeTable 3-12, GP2 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP3[31:0] I/O
Table 3-13 NOTE Table 3-13 SeeTable 3-13, GP3 Terminal Functions table for muxing and internal pullup/pulldown/disable details.
JTAG
TCLK W7 I DVDDIPU – JTAG test clock input
JTAG return clock output
IPU/DIS The internal pullup (IPU) is enabled for this pin when the
RTCK AD4 O –
DVDD device is in reset and the IPU is disabled (DIS) when reset is released.
TDI Y7 I IPU – JTAG test data input
DVDD
TDO AC5 O IPU – JTAG test port data output
DVDD
IPU JTAG test port mode select input. For proper operation, do
TMS AA7 I DVDD – not oppose the IPU on this pin.
TRST AA4 I IPD – JTAG test port reset input
DVDD
VOUT[0], VOUT[0]_R_CR[2]/
IPD GP2
EMU4/ AD9 I/O Emulator pin 4
DVDD PINCNTL196 GP2[26]
DSIS: PIN VOUT[0],
VOUT[0]_G_Y_YC[2]/ IPD GP2
EMU3/ AH7 I/O Emulator pin 3
DVDD PINCNTL188
GP2[24] DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
NAME NO.
VOUT[0],
VOUT[0]_B_CB_C[2]/ IPD GP0
EMU2/ AG7 I/O Emulator pin 2
DVDD PINCNTL180
GP2[22] DSIS: PIN
EMU1 AE11 I/O IPU – Emulator pin 1
DVDD
EMU0 AG8 I/O IPU – Emulator pin 0
DVDD
3.2.15 Serial ATA (SATA) Signals
Table 3-26. Serial ATA (SATA) Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3) MUXED DESCRIPTION
NAME NO.
– Serial ATA Data Transmit.
SATA_TXN0 AB1 O –
VDDA_SATA_1P8
When the SATA SERDES are powered down, these
SATA_TXP0 AB2 O VDDA_SATA_1P8– – pins should be left unconnected.
– Serial ATA Data Receive.
SATA_RXN0 AA2 I –
VDDA_SATA_1P8
When the SATA SERDES are powered down, these
SATA_RXP0 AA1 I VDDA_SATA_1P8– – pins should be left unconnected.
SPI[0]_SCS[1]/ SPI[0], SD1,
SD1_SDCD/
EDMA, TIMER 4,
SATA_ACT0_LED/ AE5 O IPU GP1 Serial ATA disk 0 Activity LED output
EDMA_EVT1/ DVDD
PINCNTL80
TIM4_IO/ DSIS: N/A
GP1[6]
– PCIE Serdes Reference Clock Inputs and optional
SERDES_CLKP AF1 I SERDES_CLK – SATA Reference Clock Inputs.
LDO (internal) Shared between PCI Express and Serial ATA. When PCI Express is not used, and these pins are not used – as optional SATA Reference Clock Inputs, these pins
SERDES_CLKN AF2 I SERDES_CLK –
should be left unconnected.
LDO (internal)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal