3 Cortex-M3 Peripherals
Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value
Description Reset
Type Name
Bit/Field
Divide-by-Zero Usage Fault Description Value
No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled.
0
The processor has executed anSDIVorUDIVinstruction with a divisor of 0.
1
When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting theDIV0bit in the Configuration and Control (CFGCTRL) register (see page 150).
This bit is cleared by writing a 1 to it.
0 R/W1C
DIV0 25
Unaligned Access Usage Fault Description
Value
No unaligned access fault has occurred, or unaligned access trapping is not enabled.
0
The processor has made an unaligned memory access.
1
UnalignedLDM,STM,LDRD, andSTRDinstructions always fault regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting theUNALIGNEDbit in the CFGCTRL register (see page 150).
This bit is cleared by writing a 1 to it.
0 R/W1C
UNALIGN 24
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
0x00 RO
reserved 23:20
No Coprocessor Usage Fault Description
Value
A usage fault has not been caused by attempting to access a coprocessor.
0
The processor has attempted to access a coprocessor.
1
This bit is cleared by writing a 1 to it.
0 R/W1C
NOCP 19
Invalid PC Load Usage Fault Description
Value
A usage fault has not been caused by attempting to load an invalid PC value.
0
The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value.
1
When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
0 R/W1C
INVPC 18
Description Reset
Type Name
Bit/Field
Invalid State Usage Fault Description Value
A usage fault has not been caused by an invalid state.
0
The processor has attempted to execute an instruction that makes illegal use of the EPSR register.
1
When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
INVSTAT 17
Undefined Instruction Usage Fault Description
Value
A usage fault has not been caused by an undefined instruction.
0
The processor has attempted to execute an undefined instruction.
1
When this bit is set, the PC value stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
This bit is cleared by writing a 1 to it.
0 R/W1C
UNDEF 16
Bus Fault Address Register Valid Description
Value
The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address.
0
The FAULTADDR register is holding a valid fault address.
1
This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
0 R/W1C
BFARV 15
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
0 RO
reserved 14:13
Description Reset
Type Name
Bit/Field
Stack Bus Fault Description Value
No bus fault has occurred on stacking for exception entry.
0
Stacking for an exception entry has caused one or more bus faults.
1
When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
BSTKE 12
Unstack Bus Fault Description Value
No bus fault has occurred on unstacking for a return from exception.
0
Unstacking for a return from exception has caused one or more bus faults.
1
This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
BUSTKE 11
Imprecise Data Bus Error Description Value
An imprecise data bus error has not occurred.
0
A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.
1
When this bit is set, a fault address is not written to the FAULTADDR register.
This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both theIMPREbit is set and one of the precise fault status bits is set.
This bit is cleared by writing a 1 to it.
0 R/W1C
IMPRE 10
Precise Data Bus Error Description Value
A precise data bus error has not occurred.
0
A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.
1
When this bit is set, the fault address is written to the FAULTADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
PRECISE 9
Description Reset
Type Name
Bit/Field
Instruction Bus Error Description Value
An instruction bus error has not occurred.
0
An instruction bus error has occurred.
1
The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction.
When this bit is set, a fault address is not written to the FAULTADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
IBUS 8
Memory Management Fault Address Register Valid Description
Value
The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address.
0
The MMADDR register is holding a valid fault address.
1
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
0 R/W1C
MMARV 7
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
0 RO
reserved 6:5
Stack Access Violation Description Value
No memory management fault has occurred on stacking for exception entry.
0
Stacking for an exception entry has caused one or more access violations.
1
When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
MSTKE 4
Description Reset
Type Name
Bit/Field
Unstack Access Violation Description Value
No memory management fault has occurred on unstacking for a return from exception.
0
Unstacking for a return from exception has caused one or more access violations.
1
This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
MUSTKE 3
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
0 RO
reserved 2
Data Access Violation Description Value
A data access violation has not occurred.
0
The processor attempted a load or store at a location that does not permit the operation.
1
When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
DERR 1
Instruction Access Violation Description Value
An instruction access violation has not occurred.
0
The processor attempted an instruction fetch from a location that does not permit execution.
1
This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0 R/W1C
IERR 0