ac-cessing the MICROWIRE registers. There are five such reg-isters:
— MICROWIRE Data Register (MWDAT)
— MICROWIRE Control Register (MWCTL)
— MICROWIRE Status Register (MWSTAT)
17.5.1 MICROWIRE Data Register (MWDAT)
The MWDAT register is a word-wide, read/write register used to transmit and receive data through the MDODI and MDIDO pins. Figure31 shows the hardware structure of the register.
Figure 29. Alternate Mode, MIDL Bit = 1
End of Transfer
Sample Point Shift Out
Data Out
Data In
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
MSKn
Figure 30. MWSPI Interrupts
Interrupt MWSPI MOVR = 1
MRBF = 1
MBSY = 0
MEIW MEIR MEIO
17.5.2 MICROWIRE Control Register (MWCTL)
Upon reset, all non-reserved bits are cleared to 0. The regis-ter format is shown below.
MEN MICROWIRE Enable. This bit enables (1) or disables (0) the MICROWIRE interface mod-ule. Clearing this bit disables the module, clears the status bits in the MICROWIRE status register (the MBSY, MRBF, and MOVR flags in MWSTAT), and places the MICROWIRE inter-face pins in the states described in Table18.
MMNS MICROWIRE Master/Slave Select. When cleared to 0, the device operates as a slave.
When set to 1, the device operates as the mas-ter.
MMOD MICROWIRE Mode Select (8- or 16-bit). When set to 0, the device operates in 8-bit mode.
When set to 1, the device operates in 16-bit mode. This bit should only be changed when the module is disabled or the MICROWIRE in-terface is idle (MWSTAT.MBSY=0).
MECH MICROWIRE Echo Back. This bit enables (1) or disables (0) the echo back function in slave mode. This bit should be written only when the MICROWIRE interface is idle (MWSTAT.MB-SY=0). The MECH bit is ignored in master mode. The MWDAT register is valid from the time the register has been written until the end of the transfer.
In the echo back mode, MDODI is transmitted (echoed back) on MDIDO if MWDAT does not contain any valid data. With the echo back function disabled, the data held in the MWDAT register is transmitted on MDIDO, whether or not the data is valid.
MEIO MICROWIRE Enable Interrupt on Overrun.
This bit enables or disables the overrun error interrupt. When set to 1, an interrupt is gener-ated when the Receive Overrun Error flag (MWSTAT.MOVR) is set. Otherwise, no inter-rupt is generated when an overrun error oc-curs. This bit should only be enabled in master mode.
MEIR MICROWIRE Enable Interrupt for Read. When set to 1, an interrupt is generated when the Read Buffer Full flag (MWSTAT.MRBF) is set.
Otherwise, no interrupt is generated when the read buffer is full.
MEIW MICROWIRE Enable Interrupt for Write. When set to 1, an interrupt is generated when the Busy bit (MWSTAT.MBSY) is cleared, which in-dicates that a data transfer sequence has been completed and the read buffer is ready to re-ceive the new data. Otherwise, no interrupt is generated when the Busy bit is cleared.
MSKM MICROWIRE Clocking Mode. When cleared to 0, the device uses the normal clocking mode.
When set to 1, the device uses the alternate Figure 31. MWDAT Register Structure
Shift Register
Read Buffer
Low-Byte High-Byte
write
(store)
1 0
MWMOD DIN DOUT
read
(store & MWMOD)
Low-Byte High-Byte
MWDAT
1 5 9 8 7 6 5 4 3 2 1 0
MCDV [6:0]
MIDL MSKM MEIW MEIR MEIO MECH MMOD MMNS MEN
Table 18 Pin Values with MICROWIRE Disabled
MSK Master: MnIDL Bit
Slave: input
MCS Input
MDIDO Master: input Slave: TRI-STATE MDODI Master: known Value
Slave: input
clocking mode. In the normal mode, the output data is clocked out on the falling edge of MSK and the input data is sampled on the rising edge of MSK. In the alternate mode, the output data is clocked out on the rising edge of MSK and the input data is sampled on the falling edge of MSK.
MIDL MICROWIRE Idle. This bit sets the value of the MSK output when the MICROWIRE interface is idle: 0 for low or 1 for high. This bit should be changed only when the MICROWIRE interface module is disabled (MEN=0) or when no bus transaction is in progress (MWSTAT.MBSY=0).
MCDV MICROWIRE Clock Divider Value. This 7-bit field specifies the divide-by factor used for gen-erating the MSK shift clock from the system clock. The divide-by factor is 2*(MCDV[6:0]+1).
This allows selection of a divide-by ratio from 2 to 256. This field is ignored in slave mode (MWCTL1.MMNS=0).
17.5.3 MICROWIRE Status Register (MWSTAT) The MICROWIRE Status Register is a word-wide, read-only register that shows the current status of the MICROWIRE in-terface module. Upon reset, all non-reserved bits are cleared to 0. The register format is shown below.
MBSY MICROWIRE Busy. This bit, when set to 1, in-dicates that the MICROWIRE shifter is busy.
In master mode, MBSY is set to 1 when the MWDAT register is written. In slave mode, this bit is set to 1 on the first leading edge of MSK when MCS is asserted or when the MWDAT register is written, whatever occurs first.
In both master and slave modes, this bit is cleared to 0 when the MICROWIRE data trans-fer sequence is completed and the read buftrans-fer is ready to receive the new data; in other words, when the previous data held in the read buffer has already been read.
If the previous data in the read buffer has not been read and a new data has been received into the shift register, the MBSY will not be cleared, as the transfer could not be complet-ed. This is because the contents of the shift register could not be copied into the read buff-er.
MRBF MICROWIRE Read Buffer Full. This bit, when set to 1, indicates that the MICROWIRE read buffer is full and ready to be read by the soft-ware. It is set to 1 when the shifter loads the read buffer, which occurs upon completion of a transfer sequence if the read buffer is empty.
The MRBF bit is updated when the MWDAT register is read. At that time, the MRBF bit is
cleared to 0 if the shifter does not contain any new data (in other words, the shifter is not re-ceiving data or has not yet received a full byte of data). The MRBF bit remains set to 1 if the shifter already holds new data at the time that MWDAT is read. In that case, MWDAT is imme-diately reloaded with the new data and is ready to be read by the software.
MOVR MICROWIRE Receive Overrun Error. This bit, when set to 1 in master mode, indicates that a receive overrun error has occurred. This error occurs when the read buffer is full, the 8-bit shifter is full, and a new data transfer sequence starts. This bit is undefined in slave mode.
The MOVR bit, once set, remains set until cleared by the software. The software clears this bit by writing a 1 to its bit position. Writing a 0 to this bit position has no effect. No other bits in the MWSTAT register are affected by a write operation to the register.
15 3 2 1 0
Reserved MOVR MRBF MBSY
18.0 USART
The USART module is a full-duplex Universal Synchronous/
Asynchronous Receiver/Transmitter that supports a wide range of software-programmable baud rates and data for-mats. It handles automatic parity generation and several er-ror detection schemes. There are one or two independent USART modules in each device, depending on the package type.
Each USART module offers the following features:
— Full-duplex double-buffered receiver/transmitter
— Synchronous or asynchronous operation
— programmable baud rate from SYS_CLK/
[2*(1+2^11)*16] up to SYSCLK/2 for USART config-ured to run in synchronous mode
— programmable baud rate from SYS_CLK/
[16*(1+2^11)*16] up to SYSCLK/16 for USART config-ured to run in asynchronous mode
— Programmable framing formats: seven, eight, or nine data bits; one or two stop bits; and odd, even, mark, space, or no parity
— Hardware parity generation for data transmission and parity check for data reception
— Interrupts on “transmit ready” and “receive ready” con-ditions, separately enabled
— Software-controlled break transmission and detection
— Internal diagnostic capability
— Automatic detection of parity, framing, and overrun er-rors