ECS Journal of Solid State Science and Technology, 1 (4) P175-P178 (2012) P175 2162-8769/2012/1(4)/P175/4/$28.00©The Electrochemical Society
Fast Etching of Molding Compound by an Ar/O2/CF4
Plasma and
Process Improvements for Semiconductor Package Decapsulation
J. Tang,a,b,zD. Gruber,cJ. B. J. Schelen,dH.-J. Funke,cand C. I. M. BeenakkerbaMaterials Innovation Institute (M2i), 2628 CD Delft, The Netherlands
bLaboratory of Electronic Components, Technology and Materials (ECTM), Delft Institute of Microsystems
and Nanoelectronics (Dimes), Delft University of Technology, 2628 CT Delft, The Netherlands
cNXP Semiconductors, 22529 Hamburg, Germany
dElectronic and Mechanical Support Division (DEMO), Delft University of Technology, 2600 GB Delft,
The Netherlands
Decapsulation of a SOT23 semiconductor package with 23 um copper wire bonds is conducted with an especially designed microwave induced plasma system. It is found that a 30%-60% CF4addition in the O2/CF4etchant gas results in high molding compound etching rate. Si3N4overetching which is encountered in plasma decapsulation is solved by an improved etching process. Critical processing parameters are investigated and 350 um thick molding compound on top of the die is removed selectively by pure plasma etching for 6 minutes, which is at least 10 times faster than conventional plasma etchers.
© 2012 The Electrochemical Society. [DOI:10.1149/2.019204jss] All rights reserved.
Manuscript submitted June 19, 2012; revised manuscript received July 20, 2012. Published August 24, 2012.
Semiconductor devices are routinely decapsulated for failure anal-ysis and quality control. For plastic semiconductor packages, molding compound has to be removed selectively in a reasonable processing time (see Fig.1a;1b). The compositions in molding compound are epoxy (10–30%Wt), silica fillers (70–90%Wt), and small amounts of coupling agents, hardener, releasing agents, flame retardants, etc. It is crucial that all the metal bond wires, aluminum bond pads, and silicon die remain undamaged so that further analysis like Optical Microscopy, Scanning Electron Microscopy (SEM), Photo Emission Microscopy, etc. can be performed. If the decapsulation process causes damage to any of the above mentioned parts in the package, possi-ble failure sites will be removed and important information will be lost.
Conventional decapsulation technique is to use hot nitric and sul-furic acid to etch away the molding compound. Acid etching is fast (several minutes for a semiconductor package) and works fine with gold wire bonded packages. However, the switching to copper wire bonding in industry1–3 due to cost concerns has raised a problem
for acid decapsulation because copper wires are more susceptible to be corroded and damaged by the acid. Optimizing the recipes can improve the process,4 but the new epoxy materials used in molding
compounds are becoming more and more resistant to acid attacks. Laser can be used to ablate the molding compound,5,6but it cannot
be used to expose the silicon die because of the high risk of caus-ing catastrophic damage to the structures on the die. Conventional plasma etchers that use a vacuum chamber and a radio frequency (RF) power source are capable of etching silicon containing materials so they can also be used for decapsulation. But the extremely low etching rate compared7,8to acid etching (several hours or even days
for one package) and high potential of electrical damage due to the charging effects in the chamber make plasma decapsulation not a good solution.
It has been reported before that a microwave induced plasma sys-tem is a unique approach to decapsulate copper wire bonded semicon-ductor packages.9,10Molding compound can be removed selectively
at a high etching rate (100 um/min) leaving the copper wire bonds and aluminum bond pads undamaged.10The only problem is unwanted
overetching of Si3N4passivation layer on top of the Si die. Optimiz-ing plasma recipes help to reduce overetchOptimiz-ing of structures on the die but due to the nature of plasma chemistry, the Si3N4 passivation is always removed. In this paper, we report improvements with focus on preventing damage to the Si3N4passivation layer by an improved plasma etching process.
zE-mail:j.tang@tudelft.nl
Experimental setup
The plasma system basically consists of a microwave genera-tor (Sairem solid-state, f= 2450+−20 MHz, P = 0 ∼ 180 W), a Beenakker type microwave resonant cavity,11 an alumina gas
dis-charge tube (6 mm outer diameter, 1.2 mm inner diameter, 10 cm length), a programmable XYZ-stage, and a CCD camera (see Fig.2a). The cavity has a hollow structure and is designed to resonate in the TM010mode at 2450 MHz. Microwave power is coupled from the coaxial cable into the cavity by an antenna loop. Modification on the original antenna is made in order to improve the microwave cou-pling of the system when sustaining argon plasma. Power reflection is maintained below 5% throughout the etching experiments.
The system operates under atmospheric pressure thus a vacuum system is not needed. Argon is used as the plasma carrier gas. Oxy-gen and carbontetrafluoride gas are added into the plasma as etchants. The semiconductor package samples are placed at about 2 cm below the plasma source. A picture of an argon plasma generated by this system is shown in Fig.2b. When etchant gas is added into the argon plasma, energy is lost to dissociate oxygen and carbontetrafluoride into atomic oxygen and fluorine respectively. As a result, the length of the plasma filament will decrease when etchant gas is added. Dur-ing decapsulation experiments, the plasma filament remains inside the cavity and the microwave stray field is only measurable when the microwave leakage detector (Sairem IFP) is placed at less than 7 cm to the plasma filament. The low stray field (<2 mW/cm2 at 5 cm from plasma) ensures no electrical damage to the semiconduc-tor chip during decapsulation due to the RF field. The effluent of the plasma, that carries the radicals, flows downwards to the surface of the semiconductor package sample where etching takes place.
Plasma etching leaves a spherical cap dent with a diameter around 4 mm. The depth of the dent depends on the plasma recipe and etch-ing duration. When uniform etchetch-ing on a larger area is needed, the semiconductor package is scanned under the plasma effluent by using the programmable XYZ-stage. The scan route and speed can be spec-ified and programmed so that precise localization control and high reproducibility can be achieved. The CCD camera provides real time imaging of the semiconductor package surface under plasma etching (see Fig.2c). This adds value for failure analysis as inspection dur-ing layer by layer decapsulation is possible. The image from the CCD camera is used as feedback to the etching process control and it clearly shows the bond wires and die exposed during plasma etching.
Experimental
The two major components in molding compound used in plas-tic semiconductor packages are epoxy (10–30%Wt) and silica fillers (70–90%Wt). Oxygen radicals in the plasma effluent react with epoxy
P176 ECS Journal of Solid State Science and Technology, 1 (4) P175-P178 (2012)
Figure 1. Schematic representation of the semiconductor package structure
(a) Before decapsulation; (b) After decapsulation.
while fluorine radicals react with silica filler. Oxygen plasma etching leaves a layer of silica agglomerate residue that cannot be easily re-moved. This silica layer blocks further etching of molding compound by the plasma effluent. Carbontetrafluoride plasma only etches the sil-ica filler thus molding compound etching rate is extremely low. Only when both oxygen and carbontetrafluoride are added into the plasma can a high molding compound etching rate be achieved. The epoxy in molding compound is completely etched. At the same time, the silica filler is etched at a low rate so that the filler agglomerate structure become loose. The gas flow from the plasma effluent blows off the etched silica filler efficiently. Plastic encapsulated SOT23 packages with 350 um molding compound on top of the die is used for the etching rate measurement. Due to the small size of the sample, the molding compound etching rate is measured indirectly. The etching time needed to expose the die is measured and the etching rate is cal-culated by dividing the thickness of molding compound by the etching time in order to get reliable values.
Maximum molding compound etching rate is found to be between 30–60% CF4 addition (see Fig.3). A higher or lower CF4 addition from this optimal range results in lower etching rate. A low CF4 addition favors epoxy etching while a high CF4addition favors silica etching. As the molding compound is a mixture material, both epoxy and silica filler have to be etched simultaneously to achieve a high combined etching rate. When adding O2into a CF4plasma, reactions between CF3and O2 increases the concentration of free F atoms.12 The effect that the addition of CF4into O2 plasmas increases epoxy etching rate13–15and the addition of O
2 into CF4 plasmas increases silicon dioxide12etching rate also facilitates the molding compound
etching by the Ar/O2/CF4mixture plasma.
Comparing to the etching rate values obtained from conventional plasma etchers, the molding compound etching rate of this plasma etching system is at least 10 times faster. One major reason of this
Figure 3. Molding compound etching rate versus ratio of CF4 in O2/CF4 etchant gas. Argon gas flow: 1400 sccm, O2/CF4 total gas flow: 21 sccm, absorbed microwave power: 60 W.
difference is in volume power density and reactant flux. For conven-tional plasma etchers that use a vacuum chamber, the plasma fills in a large part of the chamber and the power density is low (typical plasma radius: 16 cm, height: 5 cm, volume: 1000 cm3, power: 0–500 W). For our plasma system the space where plasma is generated is very con-fined thus the power density is much higher (plasma filament radius: 1.2 mm, height: 20 mm, volume: 23 mm3, power: 0–100 W). A much higher power density ensures a much higher radical reactant flux and plasma etching rate. For decapsulation applications where normally an area of 1 cm2needs to be etched, using a confined plasma to scan across the semiconductor package is more suitable than using a large chamber of plasma and a mask to define a small area that is intended to etch.
Plasma decapsulation with the non-improved process (Overetch-ing of Si3N4 passivation and die structures).— Decapsulation of a
SOT23 package (see Fig.4a;4b) with two 23 um copper wire bonds are performed by using a Ar/O2/CF4mixture plasma with 45 W input microwave power. 70% of O2and 30% of CF4in the etchant gas mix-ture is used to achieve a high molding compound etching rate. Higher input power results in a higher etching rate but also causes oxidization damage on the copper wire bonds. Semiconductor package is etched continuously for 5 minutes by this recipe until the wire bonds and die are all exposed as viewed through the CCD camera. The same type of package is decapsulated by acid as a reference. Comparing Fig.4c with Fig.4d, the copper bond wire after plasma etching is obviously more reddish in color. Detailed SEM analysis showed no loss in wire diameter or surface features by plasma etching as opposed to acid etching. Loss in wire diameter using acid etching strongly depends on overetch time and temperature control. Thus, samples after acid decapsulation show quite some variation. For a well-designed hot acid etching process measurements show that a 23 um copper wire diame-ter may reduce up to 2 um while also the surface roughness increased. This indicates the copper wire bonds after plasma etching is in much better condition than after acid etching. However, the surface of the
Figure 2. (a) Schematic representation of the plasma system; (b) An argon plasma generated by the system; (c) Picture from the integrated CCD camera showing
ECS Journal of Solid State Science and Technology, 1 (4) P175-P178 (2012) P177
Figure 4. (a) SOT23 semiconductor package before decapsulation; (b)
Schematic representation of the circuit inside the package; (c) Optical pic-ture of semiconductor package after plasma decapsulation; (d) Semiconductor package after acid decapsulation; (e) SEM picture of the die after plasma etching; (f) SEM picture of the die after acid etching.
die after plasma etching appears to be more rough and unclean. Fur-ther analysis under SEM showed the Si3N4 passivation layer on top of the die is completely removed and overetching on the silicon die left rough porous structures after plasma etching (see Fig.4e). SEM picture on acid etching result showed the Si3N4passivation and silicon die are in good condition but the copper wire bond suffered shrinkage in size due to acid etching (see Fig.4f). Although optimization of recipes helps to reduce damage in both deprocessing methods, etch-ing of Si3N4passivation by plasma decapsulation16–18and etching of copper wires by acid decapsulation seems inevitable.
Improved plasma decapsulation process (Optimized recipe: un-damaged Si3N4passivation).— To prevent etching of the Si3N4 pas-sivation layer at all, an improved plasma decapsulation process is developed. In the first step, Ar/O2/CF4 mixture plasma is used to quickly remove thick molding compound (about 300 um) on top of the die in 4 minutes. The bond wires are exposed after this etching step but the ball bond and die are not exposed. The remaining 50 um molding compound act as a protection layer to the underlying Si3N4 passivation layer to plasma etching. In the second step, Ar/O2mixture plasma is used to selectively etch away the epoxy in the remaining molding compound in 2 minutes. Because no fluorine containing gas is used, Si3N4and SiO2are not etched resulting in a remaining filler layer on top of the die. The silica filler residues, left after that the epoxy is removed from the molding compound, do not appear as a powder. Instead they form a layer of agglomerate that cannot be easily removed by gas blowing. The third step is a safe and clean way to remove the remaining layer of silica agglomerate by ultrasonic clean-ing in water for 10 seconds. The cavitations generated in water are capable to dissociate the silica agglomerate into powder efficiently, leaving a clean surface of die and bond wires.
The silicon die, Si3N4passivation layer, and copper bond wires are undamaged at all after decapsulation and are in excellent condition for further failure analysis (see Fig.5a). The surface of the copper wires after the improved plasma etching process is smooth and the ball bonds are less attacked compared to the acid etched counterparts (see. Fig.5b, Fig.4f). Electrical measurements (forward voltage at certain
Figure 5. (a) Semiconductor package decapsulated by the improved process;
(b) SEM picture of the semiconductor package.
current) of the two bipolar diode devices in this package before and after plasma decapsulation showed no change in value. More than 20 samples are tested and all are undamaged indicating this process is safe for maintaining functionality of the device.
Improved plasma decapsulation process (Not optimized recipe: partial removal of Si3N4 passivation).— The thickness of the
block-ing layer of moldblock-ing compound after the first Ar/O2/CF4 etching step must be more than 30 um. Otherwise the fluorine radicals will penetrate through the molding compound layer and reach the under-lying Si3N4 passivation. During Ar/O2/CF4 plasma etching, the top layer of the molding compound is porous as epoxy is partly removed by oxygen radicals while the silica fillers are slower to remove and are left on the surface. The fluorine radicals diffuse through these pores and cause overetching of Si3N4even though a layer of loose-structured molding compound is still left on top of the die (see Fig.6a). Fig.6bis a SEM picture showing the etching process where the Si3N4 is completely removed in the lower area and partly removed in the upper area. Because the plasma recipe is developed to give a high molding compound etching rate, direct exposure of the die under the plasma for 10 seconds will cause complete removal of the Si3N4 pas-sivation. A further exposure under CF4containing plasma will cause overetching of the silicon on the die as seen in Fig.4e.
Conclusions
Etching of molding compound by using a microwave induced at-mospheric pressure Ar/O2/CF4 plasma is investigated. 30–60% CF4 addition in the O2/CF4etchant mixture gives high molding compound etching rate and selectivity. The critical thickness of molding com-pound blocking layer is found to be 30 um and below this value Ar/O2/CF4plasma overetching of Si3N4passivation on top of the die takes place. An improved plasma etching process by adding an O2 plasma etching followed by an ultrasonic cleaning step successfully avoids overetching of Si3N4and Si. After 6 minutes plasma etching,
P178 ECS Journal of Solid State Science and Technology, 1 (4) P175-P178 (2012)
Figure 6. (a) Si3N4 passivation partly removed due to a not thick enough blocking layer of molding compound less than 30 um thick; (b) SEM picture showing the partly removed Si3N4layer.
the Si3N4passivation, Si die, 23 um copper wire bonds, and aluminum bond pads are cleanly exposed without damage. Devices 100% retain electrical functionality. The high molding compound etching rate and selectivity, low stray field, good localization control, and real time imaging ability makes the system efficient for decapsulation of copper wire bonded semiconductor packages for failure analysis and quality control.
Acknowledgments
This research was carried out under project number M21.9.SE2Ab in the framework of the research program of the Materials innovation institute (M2i) and co-funded by ENIAC Joint Undertaking. The au-thors thank Dimes colleagues A. Akhnoukh, A. van den Bogaard, C. C. G. Visser, and R. P. van Viersen for their help on experiments.
References
1. B. K. Appelt, A. Tseng, C. H. Chen, and Y. S. Lai,Microelectronics Reliability, 51, 13 (2011).
2. S. Murali, N. Srikanth, Y. M. Wong, and C. J. Vath III,Journal of Materials Science, 42, 615 (2007).
3. S. Kaimori, T. Nonaka, and A. Mizoguchi,IEEE Transactions on Advanced Packag-ing, 29, 227 (2006).
4. S. Murali and N. Srikanth,IEEE Transactions on Electronics Packaging Manufac-turing, 29, 179 (2006).
5. H. Qiu, H. Y. Zheng, X. C. Wang, and G. C. Lim,Materials Science in Semiconductor Processing, 8, 502 (2005).
6. M. Kr¨uger, J. Krinke, K. Ritter, B. Zierle, and M. Weber,Microelectronics Reliability, 43, 1827 (2003).
7. J. Thomas, J. Baer, P. Westby, K. Mattson, F. Haring, G. Strommen, J. Jacobson, S. S. Ahmad, and A. Reinholz, in Proceedings of the IEEE 59thElectronic
Compo-nents and Technology Conference., p. 2011–2015, IEEE, San Diego (2009). 8. S. Dzioba, G. Este, and H. M. Naguib,J Electrochem Soc, 129, 2537 (1982). 9. L. Qian, C. I. M. Beenakker, and C. J. Vath III, In Proceedings of the IEEE 7th
International Conference on Electronic Packaging Technology and High Density Packaging., IEEE, Shanghai (2006).
10. J. Tang, J. B. J. Schelen, and C. I. M. Beenakker, In Proceedings of the IEEE 11th
International Conference on Electronic Packaging Technology and High Density Packaging., p. 1034–1038, IEEE, Xi’an (2010).
11. C. I. M. Beenakker,Spectrochimica Acta Part B: Atomic Spectroscopy, 31, 483 (1976).
12. C. J. Mogab, A. C. Adams, and D. L. Flamm,Journal of Applied Physics, 49, 3796 (1978).
13. B. Lamontagne, A. M. Wrobel, G. Jalbert, and M. R. Wertheimer,Journal of Physics D: Applied Physics, 20, 844 (1987).
14. F. Emmi, F. D. Egitto, and L. J. Matienzo,Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 9, 786 (1991).
15. F. D. Egitto, F. Emmi, R. S. Horwath, and V. Vukanovic,Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 3, 893 (1985). 16. Y. Zhang, G. S. Oehrlein, and F. H. Bell,Journal of Vacuum Science and Technology
A: Vacuum, Surfaces and Films, 14, 2127 (1996).
17. G. H. Kim, S. B. Kim, and C. I. Kim, Microelectronic Engineering, 83, 2504 (2006).
18. M. Schaepkens, T. E. F. M. Standaert, N. R. Rueger, P. G. M. Sebel, G. S. Oehrlein, and J. M. Cook,Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films, 17, 26 (1999).
