Substrate Crosstalk Suppression Using Wafer-Level Packaging: Metalized Through-Substrate Trench Approach

Substrate Crosstalk Suppression Using

Wafer-Level Packaging:

Metalized Through-Substrate Trench Approach

Substrate Crosstalk Suppression Using

Wafer-Level Packaging Technique:

Metalized Through-Substrate Trench Approach

PROEFSCHRIFT

ter verkrijging van de graad van doctor

aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus Prof. ir. K. Ch. A. M. Luyben,

voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op woensdag 6 oktober 2010 om 10.00 uur

door

Saoer Maniur SINAGA

Master of Science in Communication Engineering,

Universit¨at Kassel,

Prof. dr. J. N. Burghartz

Samenstelling promotiecommissie: Rector Magnificus, voorzitter

Prof. dr. J. N. Burghartz, Technische Universiteit Delft, promotor Dr. M. Bartek, Technische Universiteit Delft, co-promotor Prof. dr. P. M. Sarro, Technische Universiteit Delft

Prof. dr. P. J. French, Technische Universiteit Delft Prof. dr. E. Charbon, Technische Universiteit Delft Prof. dr. ir. M. K. Smit, Technische Universiteit Eindhoven

Dr. S. Wane, NXP Semiconductors

Prof. dr. K. A. A. Makinwa, Technische Universiteit Delft, reservelid

Copyright c° 2010 by S.M. Sinaga

All rights reserved. No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without the prior permission of the author.

ISBN 978-90-8570-600-7

Surely goodness and mercy shall follow me all the days of my life; and I will dwell in the house of the Lord forever (Psalm 23:6).

Summary

The demand for miniaturization technology has been increasing over the last decades. Consumer electronics end-users often, if not always, go for more func-tionality and practicality. This is translated into systems that are more complex and yet smaller in size such as smart cellular phones and portable audio/video systems. System on Chip (SoC) is still a solution preferred by many. The SoC comprises of many different circuit blocks that fall into two categories namely analog/RF and digital. The integration of the analog/RF circuitry and digital circuitry on the same silicon substrate has yet another challenge to cope with. The noise generated from the switching activity of the digital circuitry is injected into the silicon substrate, which then can propagate to the sensitive analog/RF circuitry. Such substrate noise can significantly degrade the functionality of the analog/RF circuitry, thus deteriorating the performance of the entire electronic system. In this thesis, a method to isolate the noise generating circuit block from the noise sensitive circuit block is proposed and demonstrated.

The proposed method is based on through-substrate trench isolation scheme to suppress the substrate noise. The idea behind this isolation scheme is to create a full through-substrate trench that physically separates the noise agressor from the victim. This idea is very simple and effective. The through-substrate trench is achieved by means of wafer-level packaging (WLP) technology and consists of only a few additional fabrication steps that can readily be incorporated in the WLP processing flow. In a few words, it can be described as follows: the silicon substrate is first bonded to a spacer substrate, e.g. AF-45 glass or High-Resistivity Polycrystalline Silicon (HRPS). Then, the bonded wafer stack is turned upside down before being thinned down. The next step is to create the through-substrate trench by means of KOH etching. At this stage, we now have an air-filled through-substrate trench. This isolation scheme can be further improved by metalizing

the trench resulting in a backside metal plane. The backside metal can then be connected to ground to drain the substrate noise. This is called grounded-metalized through-substrate trench.

In this work, we have successfully fabricated and measured several devices, i.e. control device (without isolation), air-filled trench device, and metalized trench device. At 50 MHz air-filed trench provides around 55 dB isolation with respect to control device, whereas the metalized-trench provides additional isolation of 7 dB. At 10 GHz air-filled trench provides around 10 dB isolation with respect to control device, whereas the metalized-trench provides additional isolation of 23 dB. At 40 GHz air-filled trench provides around 2 dB isolation with respect to control device, whereas the metalized-trench provides additional isolation of 20 dB.

Samenvatting

De vraag naar miniaturisatie technologie is over de laatste decaden continu blijven groeien. Gebruikers van consumenten elektronica gaan vaak, bijna altijd, voor hogere functionaliteit en praktisch gebruik. Dit vertaalt zich in complexere syste-men die toch steeds weer kleiner van afmetingen zijn, zoals intelligente mobieltjes, and draagbare audio/video systemen. System on Chip (SoC) is de voorkeurstech-nologie van de Chip fabrikanten om deze miniaturisatie te realiseren. De System on Chip bestaat uit vele verschillende bouwstenen van meer of minder complexe schakelingen die in twee categorien kunnen worden onderverdeeld: analoge/rf en digitale schakelingen. De integratie van analoge/rf schakelingen en digitale schake-lingen op het zelfde silicium substraat is een speciale uitdaging. De stoorsignalen, die worden gegenereerd door de schakelactiviteiten in de digitale schakelingen, komen in het silicium substraat terecht en kunnen via deze weg doorgegeven wor-den aan de gevoelige analoge/rf schakelingen. Deze substraatstoring kan op een significante wijze de functionaliteit van de analoge/rf circuits negatief benvloe-den, waardoor de prestaties, op elektronisch systeemniveau, onbevredigend kun-nen zijn. In deze thesis wordt een methode om demping aan te brengen tussen de storende schakeling en de storingsgevoelige schakeling, voorgesteld en het de werking aangetoond.

De voorgestelde methode om de substraatstoring te reduceren, is gebaseerd op een het toevoegen van isolatie op basis van een kanaal dat over de volledige dikte van het silicium substraat wordt gemaakt through-substrate trench isolation in het vervolg in deze samenvatting kanaal genoemd. Het concept achter deze iso-latie aanpak is om een volledig kanaal te maken, die een fysieke barrire opwerpt tussen de bron en het mogelijk gestoorde schakeling. Deze aanpak is erg een-voudig en zeer effectief. Het kanaal wordt gemaakt met Wafer Level Packaging technologie en bestaat uit slechts een paar extra productie stappen, die direct in

bestaande Wafer Level Packaging productie processen kan worden toegepast. Op hoofdlijnen kan het proces als volgt worden beschreven: Het silicium substraat wordt eerst verbonden met het spacer substraat. bijvoorbeeld op basis van AF-45 glas of High-Resistivity Polycrystalline Silicon (HRPS). Vervolgens wordt de ge-realiseerde wafer stack omgedraaid en op de juiste dikte gebracht thinned down. De volgende stap is om een kanaal te maken via een ets proces op KOH basis. In deze fase hebben we een op lucht gebaseerde through-substrate trench. De iso-latie kan vervolgens worden verbeterd door het metalliseren van het kanaal en zijn omgeving in het silicium substraat. Dit leidt tot een gemetalliseerde back-plane. Deze gemetalliseerde backplane kan vervolgens aan de aarde verbonden worden om de substraat storing af te voeren. Dit wordt een grounded-metalized through-substrate trench genoemd.

In deze studie hebben we, met succes, meerdere test devices geproduceerd en gemeten. Het zijn een controle device (zonder isolatie), een lucht gesoleerd through-substrate trench device en een grounded-metalized through-substrate trench device. De resultaten van de metingen leverden de volgende isolatie verbeteringen op. Op 50 MHz gaf lucht isolatie een extra isolatie van 55 dB ten opzichte van het controle device. De metallisering leverde een extra winst van 7 dB. Op 10 GHz gaf lucht isolatie een extra isolatie van 10 dB ten opzichte van een controle device. De metallisering leverde een extra winst van 23 dB. Op 40 GHz gaf lucht isolatie een extra isolatie van 2 dB ten opzichte van het controle device. De metallisering leverde een extra winst van 20 dB op.

Acknowledgements

After many years of working and typing on the train, this adventure has finally come to an end. The journey was definitely not without ups and downs, nor could I cross the finish line without the support and help from many people.

I wish to express my gratitude to my promotor Prof. Dr.-Ing. Joachim N Burghartz for his guidance and encouragement during the course of my doctoral study, particularly for the time he spent to carefully review this thesis. I am forever grateful to my co-promotor Dr. Marian Bartek for his full support during my PhD study and after.

I am also indebted to Dr. Behzad Rejaei and Gabriel Macias for many valuable discussions.

Special thanks go to my project partner Alexander Polyakov for his excellent work in the clean room. Without him, I would not have had the device to measure. I would also like to thank scientific members of DIMES Lab. for their help and support in the clean room.

My first two years in Delft were cherished by my fellow PhD students Andrey Sachko and Harish Pillai. Italian pizza, gyros and beer colored our days in Delft. Dude, wherever you are, it was great time we had.

My skill in playing pool seemed to improve a little thanks to Jason Tian, Huang Cong, Han Yan and Sebastian Sosin. I would also like to mention Marco Spirito, Koen Buisman, Edmund Neo, Huseyin Sagkol, Theodoros Zoumpoulidis and Hsien Chang Wu for the corridor and lunch discussions.

I would also like to acknowledge Hok Yap of Philips Applied Technologies for his support in providing the dutch translation of the summary and propositions.

I am grateful to my siblings for their support and encouragement. I am in-debted to my parents for their prayers and immeasurable love. Last but not least, I am grateful to my wife, Patricia Astrid, for her loving kindness and endless support. Without her, this thesis would not have come to a completion.

This work was supported by Philips (PACD B1 project) and by EC (Blue Whale project IST-2000-10036).

Delft, Saoer Maniur Sinaga

Contents

Summary

i

Samenvatting

iii

Acknowledgements

v

1 Introduction

1 1.1 Trends in Microelectronics . . . 1

1.2 Crosstalk in Integrated Circuits . . . 2

1.3 Solutions by Wafer-Level Packaging Technology . . . 4

1.3.1 Packaging roadmap . . . 4

1.3.2 Background and history of wafer-level packaging . . . 4

1.3.3 Crosstalk suppression by wafer-level packaging . . . 6

1.4 Work Objective . . . 8

1.5 Thesis Organization . . . 8

2 Substrate Crosstalk in Integrated Circuits: Mechanisms and Suppression

Techniques

11 2.1 Crosstalk Mechanisms . . . 11

2.1.1 Radiative coupling . . . 12

2.1.2 Circuit coupling . . . 15

2.1.3 Substrate coupling . . . 17

2.2 Substrate Noise and Its Coupling Mechanisms . . . 18

2.2.1 Substrate noise injection . . . 18

2.2.2 Substrate noise transmission . . . 21

2.2.3 Substrate noise reception . . . 25

2.3 Impact of Substrate Noise on Circuits’ Performance: Some Examples 26 2.4 State-of-the-art Substrate Noise Suppression Techniques . . . 27

2.5 Summary . . . 30

3 Substrate Crosstalk Modeling in Wafer-Level Packaged Integrated Circuits

35 3.1 Problem Description . . . 36

3.2 Substrate Crosstalk Between Two Ohmic Contacts . . . 36

3.2.1 Substrate thickness impact on isolation . . . 36

3.2.2 Distance impact on isolation . . . 38

3.2.3 Substrate resistivity impact on isolation . . . 38

3.2.4 Interconnect parasitic impact on isolation . . . 41

3.3 Through-Substrate Trench as Substrate Noise Suppression Technique 41 3.4 Synthesis of Equivalent Circuit Model . . . 45

3.5 Summary . . . 49

4 High-Frequency Substrate Characterization

51 4.1 Substrate Parameters . . . 52

4.1.1 Dielectric permittivity . . . 52

4.1.2 Substrate loss . . . 53

4.2 Coplanar Waveguide (CPW) . . . 54

4.3 Test Structures Design and Measurement Results . . . 57

CONTENTS ix

4.3.2 CPW utilization for substrate characterization . . . 59

4.3.3 Measurement and results . . . 60

4.4 Summary . . . 60

5 Metalized Through-Substrate Trench Approach

67 5.1 Design Objective and Considerations . . . 67

5.2 Test Structures Design and Simulations . . . 70

5.2.1 Control device . . . 71

5.2.2 Backside-plane isolation . . . 74

5.2.3 Air-filled through-substrate trench isolation . . . 74

5.2.4 Metalized through-substrate trench isolation . . . 74

5.3 Fabrication Flow . . . 79

5.4 Measurement Setup and Procedures . . . 83

5.4.1 Measurement setup and calibration techniques . . . 83

5.4.2 De-embedding techniques . . . 83

5.5 Experimental Verification . . . 91

5.6 Lumped Model Development and Analysis . . . 96

5.6.1 Control device . . . 101

5.6.2 Backside-plane isolation . . . 110

5.6.3 Air-filled through-substrate trench isolation . . . 117

5.6.4 Metalized through-substrate trench isolation . . . 120

5.7 Summary . . . 127

6 Conclusions, Recommendations and Future Works

129 6.1 Conclusions . . . 129

6.2 Recommendations and Future Works . . . 132

A Boundary Conditions in HFSS

133 A.1 Symmetry Boundaries . . . 133

A.2 Radiation Boundaries . . . 133

A.3 Finite Conductivity Boundaries . . . 134

A.4 Perfect Electric Boundaries . . . 135

A.5 Infinite Ground Planes Boundaries . . . 135

B Boundary Conditions Implementation

137 B.1 Device #1 . . . 138 B.2 Device #2 . . . 139 B.3 Device #3 . . . 140 B.4 Device #4 . . . 141 B.5 Device #5 . . . 142 B.6 Device #6 . . . 143 B.7 Device #7 . . . 144 B.8 Device #8 . . . 145

List of Publications

147

Bibliography

151

Curriculum Vitae

159

Chapter

1

Introduction

1.1 Trends in Microelectronics

In 1965, Intel co-founder Gordon Moore predicted the future of microelectronics. His prediction, now known as Moore’s law, states that the number of transistors on a chip doubles about every two years. Processing power, measured in millions of

transistors 10.000.000.000 1.000.000.000 100.000.000 10.000.000 1.000.000 100.000 10.000 1.000 1970 1975 1980 1985 1990 1995 2000 2005 2010 MOORE´S LAW 8008 4004 8080 8086 286 Intel386TM_Processor Intel486TM_Processor

Intel* Pentium* Processor Intel* Pentium* II Processor

Intel* Pentium* III Processor Intel* Pentium* 4 Processor

Intel* Itanium* Processor Intel* Itanium* 2 Processor Dual-Core Intel* Itanium* 2 Processor

Figure 1.1: Evolution of Intel’s processor following the Moore’s law [Cor08].

instructions per second (MIPS), has steadily risen because of both, increased oper-1

ating frequencies and increased transistor counts. This continuous miniaturization technology characterized by an ever-increasing level of integration complexity is driven primarily by cost-constrained applications such as cellular phones, home computing, and consumer multimedia devices [Gie03]. In the past, complete sys-tem occupied one or more circuit boards. Today, they are integrated on a few chips or even on one single chip known as System-on-Chip (SoC). SoCs can be found in many applications such as single-chip cameras and new generations of integrated telecommunication systems that include digital, analog, and eventually radio-frequency (RF) blocks. As the technical demands continuously grow, mod-ern SoC designs are, therefore, becoming more and more mixed-signal. This is even becoming more prevalent when we move towards intelligent applications such as cars interacting with their environment or smart homes where variety of home electronics and appliances are able to communicate with each other performing synchronized tasks and to adapt their behavior to their inhabitants.

Unfortunately, the higher functionality and lower cost offered with the inte-gration of both analog/RF and digital circuits onto one single die do not come without any drawback, particularly in deep-submicron CMOS technologies. The analog circuits do not only remain difficult to design, but when integrated with the digital circuits on the same chip, they require costly fabrication processes, and are very prone to noise or crosstalk signals generated by, e.g. digital circuits. The higher levels of integration with ever increasing clock frequencies make the mixed-signal chip suffer from signal integrity problem even more. This is why crosstalk is becoming a serious delimiter in Integrated Circuit (IC) design.

1.2 Crosstalk in Integrated Circuits

Crosstalk is often defined as the penetration of an unwanted signal from one circuit to another. One may also describe this unwanted signal as noise. This noise can propagate by various coupling mechanisms, i.e. radiative coupling, circuit coupling, and substrate coupling. The radiative coupling usually takes place in the form of a propagating electromagnetic field, whereas circuit coupling propagates via a conductive path, which is commonly shared, e.g. signal interconnects and power lines. The substrate coupling uses the commonly shared substrate, such as a silicon substrate, as the propagation medium. Considering any of these mechanisms, noise generated by noisy circuitry propagates to sensitive analog circuitry. Already a small amount of noise, particularly, if reaching a high-gain circuitry, can cause failure of a circuit block, hence, a total failure of the whole system-on-chip. Substrate noise, in particular, has been receiving a lot of attention from the design and technology communities. Substrate noise is generally caused by coupling of switching or noise signals to the substrate. In digital CMOS circuits this noise is caused by three mechanisms: (1) coupling from the digital power supply, (2) coupling from switching source-drain nodes, and (3) impact ionization

1.2 CROSSTALK IN INTEGRATED CIRCUITS 3 LNA_in Vcc_analog LNA_out Asub_gnd Vgnd_analog Vcc_dig dig_out dig_in Vgnd_dig Dsub_gnd

Figure 1.2: A schematic illustration of a silicon-based SoC. Substrate noise injected

into the substrate by the aggressive digital circuit disturbs the sensitive analog/RF cir-cuit [Zei03].

in the MOSFET channel [Don03]. Noise in the power supply domain is generally caused by the parasitic inductance introduced by the interconnection to and from the chip, e.g. bondwires. The parasitic inductance and fast switching time cause the potential to fluctuate according to the following formula:

Vdrop= Ri + Ldi

dt (1.1)

where R and L are the interconnect parasitics. The voltage fluctuation gets worse when the switching becomes faster. Additionally, the resonance between power and ground will also cause ringing of the power supply voltage. These effects are also called ground bounce or simultaneous switching noise [Sam00], [Gab88], [Sen91]. The second source of the substrate noise is capacitive coupling from switching source and drain nodes of the MOSFETs. Voltage fluctuation at the source or drain can couple to the bulk silicon through the source/bulk and drain/bulk junc-tion capacitances [Bri00]. The third source of the substrate noise is an impact-ionization current. For an NMOS transistor, the holes created by impact ioniza-tion are injected into the substrate, such that the transistor has current flowing out of its bulk node and entering the substrate [Bri99]. Figure 1.2 gives an illus-tration where the silicon substrate of a SoC is commonly shared by the analog/RF circuitry and the digital circuitry.

Having briefly described the increasing importance of crosstalk in modern ICs, it becomes clear that a proper design strategy needs to be adopted in the IC design process to manage the crosstalk issues. Such strategy would include: (1) simulations based on accurate crosstalk models, and (2) application of crosstalk-suppression techniques. The latter can include variety of measures that are rather straightforward such as modifications in layout or circuit scheme, but also more

radical requiring modifications in the fabrication process or electronic packaging scheme used.

1.3 Solutions by Wafer-Level Packaging Technology

1.3.1 Packaging roadmap

ICs tend to be very sensitive to environmental hazards, which include electrical, mechanical and thermal effects. Although an IC may be directly attached to a PCB (Printed Circuit Board) and then glob-topped with epoxy for protection, the IC is usually supplied in a package. The IC package ensures the protection to the IC die from external influences. Additionally, the package provides me-chanical interfacing for testing, burn-in, and electrical interconnection to the next level of packaging [Coh05]. The package, hence, must meet all device perfor-mance requirements, such as electrical (inductance, capacitance, and crosstalk), thermal (power dissipation, junction temperature), quality, reliability, and cost objectives [Coh05].

Similar to ICs, the electronic packages have also been evolving through the years. In the early days, packages like DIL (Dual in-Line) package, QFP (Quad Flat Pack) package, PLCC (Plastic Leaded Chip Carrier) package depicted in Figure 1.3a, were able to support many applications; even today they are still widely used. However, those packages are also known to introduce 1-20 nH lead inductances, which are considerably high particularly for speed and high-frequency ICs.

That is why such packages are no longer suitable for present days’ applica-tions. There is, thus, demand for more complex and higher integration level SoCs, at acceptable cost levels. The wafer-level package as shown in Figure 1.3b can be considered as one of the solutions. WLP offers many advantages over the conventional packages and will be explained later in the following sections.

1.3.2 Background and history of wafer-level packaging

Wafer-Level Packaging (WLP) is a term used to describe packaging technology of an integrated circuit at wafer level, instead of traditional process assembly after wafer dicing. The history of WLP technology started with bumping technologies used for tape automated bonding (TAB) and flip chip solder bumping, where IBM was the first to use them for its mainframe system in 1964 and later Delco for automotive electronics [Bal05]. The need for more input/output pins (I/O) as a result of the demand for higher densities on chip, and also the demand for product miniaturization for handheld and portable application were the driving

1.3 SOLUTIONS BY WAFER-LEVEL PACKAGING TECHNOLOGY 5

DIL (Dual In Line) package

QFP (Quater Flat Pack) package

PLCC (Plastic Leaded Chip Carrier) package (a) Traditional packages

(b) Wafer-level package

Figure 1.3: IC package evolution: (a) traditional packages add extra dimension to

die size that increases the component size; (b) wafer-level packaging technology yields component with the same size as the die.

forces behind the research and development of wafer-level packaging technology. WLP has emerged as a packaging technology of high interest within the elec-tronics manufacturing community. WLP provides a 1:1 area ratio of package to die providing chip-size packages (CSP). As mentioned earlier, WLPs are fabri-cated prior to the dicing step, resulting in a package footprint that is the same as that of the IC chip. This also means that the device electrical interconnects as well as device physical protection processes are also done at wafer level. Addition-ally, the WLP approach also includes wafer-level test and burn-in, which provides potentially cost savings when compared to the traditional test and burn-in for each individual package [Bal05].

On the other side, WLP also brings new challenges and potential disadvan-tages. The intrinsicly chip-size package requires fine-pitch solder bump arrays when high I/O count ICs are packaged. These fine-pitch solder arrays require high-density PCBs that tend to be higher in cost [Bal05]. Additionally, since all ICs are packaged jointly on the wafer, fault ICs are packaged together with the good ICs. Yet another potential disadvantage is that the dicing and singula-tion of the packages from the wafer can damage the package interconnect, i.e. a redistribution layer.

Nevertheless, WLP is today the fastest-growing packaging technology and is widely used for components like flash memories, DRAMs, microcontrollers, inte-grated passive components, and linear devices [And09].

1.3.3 Crosstalk suppression by wafer-level packaging

In the recent years many different approaches towards realization of WLPs have been investigated and implemented into practice. Because majority of the package processing steps takes place at a wafer level using advanced processing equipment, a rather limited modification of the packaging process flow can allow implementa-tion of addiimplementa-tional, high-accuracy structures, e.g. embedded passive components, in a highly effective way. Similarly, WLP technology offers new opportunities for packaging of Micro-Electro-Mechanical Systems (MEMS). This can be seen as the main added value of WLP technology and is also utilized in this thesis for substrate crosstalk supression.

Figure 1.4 depicts some examples of WLP as well as the WLP concept pro-posed in this thesis. The WLP concept is quite similar to the ShellOP package (developed by ShellCase). It utilizes a low-loss substrate, i.e. glass as a spacer substrate, to ensure mechanical strength of the overall package. In this concept, passive devices that often consume the largest area on the SoC die are placed onto the low-loss substrate. Having the passive devices located on the spacer substrate will reduce lateral area consumed by the SoC. Moreover, high-Q factor passive devices can be achieved when these are realized on a low-loss substrate.

1.3 SOLUTIONS BY WAFER-LEVEL PACKAGING TECHNOLOGY 7 Contact pad Metal traces Passivation layer Solder ball Silicon die Compliant layer (a) Tessera WLP

(b) Fraunhofer IZM WLP (c) China WLCSP ShellOP

Large inductor

Spacer substrate

Integrated patch antenna

Adhesive layer

Isolation trench Through-wafer via

Large inductor

Spacer substrate

Integrated patch antenna

Adhesive layer

Isolation trench Through-wafer via

Large inductor

Spacer substrate

Integrated patch antenna

Adhesive layer

Through-wafer via Isolation trench

Wafer-to-wafer bonding

(d) Proposed WLP concept

Figure 1.4: WLP examples: (a) Tessera WLP utilizes compliant layer; (b) Fraunhofer

IZM WLP wth integrate inductor and capacitor; (c) ShellOP utilizes glass-silicon-glass sandwich; (d) Proposed WLP concept utilizes through-substrate trench for crosstalk iso-lation.

Another very important feature offered by the proposed WLP concept is the possibility to form through-substrate trenches to suppress the substrate crosstalk without jeopardizing the substrate mechanical integrity. The through-substrate trench is instrumental in blocking the substrate crosstalk and drain it when low impedance path to ground is provided. This is discussed later in this thesis.

1.4 Work Objective

As mentioned in the above sections, substrate noise in a mixed-signal IC can deteriorate its performance, and can eventually lead to overall system failure. The objective of this work is an investigation of novel opportunities offered by WLP technology for substrate crosstalk supression in high-frequency applications. This thesis proposes a novel, WLP-based substrate noise suppressing technique to create a grounded metalized through-substrate trench in the lossy substrate, i.e. silicon, to block the noise propagating in it. The through-substrate trench divides the silicon substrate into silicon islands, thus insulating the sensitive circuitry from the noisy circuitry. To maintain the mechanical reliability due to the through-substrate trench, a spacer through-substrate is employed.

The WLP concept employed in this thesis not only utilizes the low-loss sub-strate to suppress potential noise propagation through the spacer subsub-strate itself, but also to realize high-Q passive devices. As shown in Figure 1.4d, the passive components are integrated onto the low-loss spacer substrate above the silicon islands thus reducing the required die area. The low-loss spacer substrate is an important part of the proposed WLP concept. Therefore, this thesis also discusses high-frequency substrate characterization. Comparison between high-resistivity polycrystalline silicon (HRPS) substrate and AF-45 glass is presented.

Since the grounded metalized through-substrate trench relies on draining the substrate noise to the ground, its effectiveness strongly depends on the ground interconnect’s impedance. Therefore, interconnect characterization is also inves-tigated in this thesis.

1.5 Thesis Organization

Chapter 1 (this chapter) gives a short motivation for the work presented in this thesis. It explains why substrate crosstalk is becoming a serious challenge in IC design. Furthermore, the thesis objective and outline are described.

1.5 THESIS ORGANIZATION 9 crosstalk in System-on-Chip (SoC) ICs is described. The three main sources of substrate crosstalk, i.e. injection mechanisms, transmission mechanisms, and reception mechanisms, are discussed. State-of-the-art substrate crosstalk sion techniques are systematically described. A novel substrate-crosstalk suppres-sion technique based on a through-substrate trench with or without metalization realized using wafer-level packaging technology is proposed.

Chapter 3 presents various substrate crosstalk modeling techniques applied to wafer-level packaged ICs. The modeling work employs 2D and 3D device simu-lators, as well as 3D electromagnetic simulator, i.e. Medici, Taurus, and Ansoft HFSS, respectively. In this chapter, influence of parameters, such as distance, contact sizes, substrate thickness, and substrate resistivity on crosstalk isolation level are evaluated.

Chapter 4 describes characterization of selected high-frequency substrates that are or can potentially be used in WLP technology. The characterization algorithm utilized is based on the quasi-TEM mode and zero thickness metal assumption, applied to coplanar waveguide (CPW). A CPW was chosen as the prefered struc-ture because it supports quasi-TEM mode and is easy to fabricate. As a result, electrical properties, i.e. dielectric constant and loss tangent of HRPS and AF-45 glass are presented.

Chapter 5 presents the design, fabrication and characterization of the test structures intended to demonstrate efficiency of the WLP techniques for strate crosstalk suppression. Test structures were designed to verify the sub-strate crosstalk theory and to demonsub-strate that sufficient level of isolation can be achieved by implementing the proposed metalized through-substrate trench method. In the fabrication section, the fabrication flow is described in detail. The measurement results are used to verify the three-dimensional EM simulation data. Furthermore, based on the measured data, lumped models were developed for each of the isolation structures tested.

Finally, in Chapter 6 the main conclusions resulting from this thesis work are reviewed and the recommendations for future work are given.

Appendix A briefly describes the boundary conditions available in HFSS and the underlying theory, while Appendix B shows how those boundary conditions are implemented in the simulation work.

Chapter

2

Substrate Crosstalk in Integrated

Circuits: Mechanisms and

Suppression Techniques

Today, a single-chip transceiver realised in CMOS technology wherein radio-frequency (RF) analog circuits are integrated with baseband digital circuit, known as System-on-Chip (SoC), can be found on the market. Nevertheless, the design of an SoC itself remains challenging. One particular challenge is to minimize the noise (unwanted signal) coupling between circuit blocks on the same chip. The noise generated by noisy circuit blocks can propagate and couple to sensitive cir-cuit blocks through several mechanisms, i.e. radiative coupling, circir-cuit coupling, and substrate coupling. In this chapter, these mechanisms are discussed in detail. In particular, substrate noise coupling mechanisms and state-of-the-art substrate noise suppression techniques are described. Several examples on how substrate noise affects the circuit performance, as well as how the circuit performance im-proves by suppressing the substrate noise, are also presented.

2.1 Crosstalk Mechanisms

While radiative and circuit coupling commonly exists at both the package and chip levels, the substrate coupling occurs at chip-level only. Circuit coupling usually occurs via mutual capacitances and inductances. It generally scales inversely with the distance between the conductors and, to a lesser degree, it depends on

their geometry. Radiative coupling arises due to unbalanced conductor currents and it is carried by propagating electromagnetic (EM) waves, especially at high frequencies.

2.1.1 Radiative coupling

Radiative coupling usually takes place in the form of propagating electromagnetic fields. In contrast to the free-space propagation, EM wave propagation within IC package occurs under complex near-field conditions, where free-space distance scaling does not apply [Woo]. By means of its transmission, radiative coupling itself is divided into three categories:

• Capacitive coupling; • Inductive coupling; • Electromagnetic coupling.

Capacitive coupling

Capacitive coupling mechanism is illustrated in Figure 2.1, where the load ZL is

connected to the amplifier output by a metal trace, which passes close to another trace that is connected to the input of amplifier A1. The coupling capacitance

between these two traces is distributed (Figure 2.1a); however, for simplicity it is represented in Figure 2.1b as a capacitor denoted Cp.

The flow of current IL through ZL charges the left circuit of Cp and as a

consequence, the same amount of electric charge (but of opposite sign) will be induced in the right circuit. This is equivalent to a parasitic voltage Vpappearing

at the input of amplifier A2, such that:

Vp= CpdVL

dt (2.1)

where Zin represents the input impedance of A2 and Rg is the resistance of the

signal generator Vg. Of course, reducing Cp(by increasing the separation between

traces) can help to reduce Vp, but the unexpected conclusion from Eq. 2.1 is that

a low input impedance of the victim circuit increases immunity to perturbations transmitted via capacitive coupling.

If either of the grounds M1 or M2 is floating, the only difference is that the

stray capacitance between the point in question and ground will be seen in series with Cp. Finally, the best solutions to reduce this type of interference are:

• Decrease the coupling capacitance Cpby increasing the separation of traces

2.1 CROSSTALK MECHANISMS 13 ∼∼∼∼ M₁ A₁ A₂ M₂ Z_L R_g V_L I_L V_g Z_in

(a) Capacitive coupling between two traces.

C

_p

V

_L

_Z

_in

_||R

_g

V

p

(b) Equivalent circuit.

Figure 2.1: Schematic representation of capacitive coupling (adapted from [Vas05]): (a)

capacitive coupling between two traces or more; (b) the aggressor circuit is modeled as a voltage source, while the victim circuit is modeled as a resistive load. The aggressor and the victim is connected through capacitor, which models the capacitive coupling between traces.

• Reduce the input impedance of the victim circuit (when possible).

Inductive coupling

Inductive coupling, also called magnetic coupling, is illustrated in Figure 2.2, where the current flowing through the output loop of amplifier A1 produces a

magnetic field whose lines intersect the input loop of amplifier A2.

Consequently, an induced parasitic voltage Vpappears in the input loop which

can be evaluated as [Vas05]:

Vp= −MdIL

dt (2.2)

M being the mutual inductance between the loops (which depends on both loops areas, their orientation, and their separation). In the equivalent circuit, the

∼∼∼∼

M

₁

A

₁

A

₂

M

₂

Z

_L

R

_g

V

_L

I

_L

V

_g

Z

_in

(a) Inductive coupling

V

_g

Z

_in

∼∼∼∼

V

_p

R

_g

(b) Equivalent circuit

Figure 2.2: Schematic representation of inductive coupling (adapted from [Vas05]): (a)

magnetic field generated by the loop areas of the two circuits couple to each other; (b) the inductive coupling is modeled by a voltage source, which is proportional to mutual inductance.

perturbing voltage Vp is in series with the signal generator Vg, hence the noise

added to the useful signal. Note, that Vp is unaffected by whether or not M1

and M2 are floating or connected to ground. To decrease the noise induced by

inductive/magnetic coupling, three solutions may be considered [Vas05]: • Limiting the area of the victim loop by properly designing the layout; • Reducing the magnetic field by shielding or by decreasing the output current

in the aggressor circuit;

2.1 CROSSTALK MECHANISMS 15 perpendicular.

Electromagnetic coupling

Traditionally, this term refers to coupling between an electromagnetic plane wave and a transmission line (recall that a plane wave has both fields perpendicular to the direction of propagation and perpendicular to each other). In the present case, the electromagnetic coupling appears between intentionally emitted waves (i.e. antenna, radar, etc.) and each trace of the circuit, which acts like a receiving antenna [Vas05].

2.1.2 Circuit coupling

The circuit coupling often also called conducted coupling happens due to interfer-ing signals that propagate from noise source to victim via a conductive path that is commonly shared. Perhaps the most obvious way to couple noise into or out of an integrated circuit is via the package leads or pins [Dhi06]. As described further in detail, there are two common conductive paths where the circuit coupling can take place [Vas05]: AC power lines and Common ground impedance.

AC power lines

Figure 2.3a illustrates a typical situation in which two different circuitries share one common AC power supply line. In this figure, let us define circuit 2 be the source of the noise and circuit 1 the victim. The equivalent circuit of the com-mon AC power line problem is shown in Figure 2.3b, where Zi1 and Zi2 are the

impedances of the AC power line sections. Zt is the impedance seen in the

sec-ondary winding of the transformer and Vp2 represents the perturbation (noise)

generated by the noise source, i.e. circuit 2. By applying a simple voltage divider formula, the perturbing voltage that reaches the victim, i.e. circuit 1, is:

Vp1= Vp2 2Zi1+ Zt

2 (Zi1+ Zi2) + Zt (2.3)

From Eq. 2.3, one can also see that Vp1 increases when Zi2 is reduced which is

the case when the distance between the two circuitries decreases. However, when Zi2 ¿ Zi1 then Vp1 ∼= Vp2 and there is no attenuation of perturbation reaching

the victim [Vas05]. To fix this, one might insert filters at the AC terminals of circuit 1 [Vas05], or use separate AC power supply for each circuit.

Z_i1 Circuitry 1 Circuitry 2 Z_i2 Z_i1 Z_i2 220 V 50 Hz

(a) Common AC power line

Z_i1 Circuitry 1 Z_i2 Z_i1 Z_i2 Z_t V_p2 Circuitry 2 (b) Equivalent circuit

Figure 2.3: Circuit coupling via common AC power supply (adapted from [Vas05]): (a)

noise occurs in circuit 1 is also seen by circuit 2 due to common AC power line; (b) the noise generator, circuit 2, is represented by Vp2

A₁ A₂

M₂

M₁

C_p1 L C_p2

R

Figure 2.4: Circuit coupling via common ground impedance(adapted from [Vas05]).

Ground reference of one circuit is no longer ideal due to ground bounce caused by another circuit. The ground bounce effect becomes significant as the frequency goes higher.

2.2 CROSSTALK MECHANISMS 17

Common ground impedance

One path that is commonly shared in an electronic system is the ground path. Figure 2.4 illustrates two amplifiers that share one common ground return path. Considering the short length of the interconnect to the ground, at low frequency, it acts like a short circuit. At higher frequencies, however, the impedance becomes larger, and is no longer negligible. Hence, a voltage drop between M1 and M2

appears on the series combination of L and R, which is also known as ground bounce, and is given by:

Vdrop= Ri + L

di

dt (2.4)

The first terms denotes the resistive voltage drop that is proportional to the switching current. The second term denotes the inductive voltage drop that is proportional to the first derivative of the switching current, and it is also known as inductive noise, delta-I noise, and L(di/dt) noise. As far as A1 is concerned,

its ground potential is modulated by ground current of A2flowing in the common

ground impedance. Despite the low value of L, the second term of Eq. 2.4 be-comes dominant, especially when fast switching currents are flowing. This voltage transient is picked up by A1 through the stray capacitance Cp1 and vice versa

to A2. The ground bounce can also propagate into the substrate through ohmic

contacts and parasitic junction capacitances. These ways of noise propagation are called substrate noise; and will be described in the next section.

2.1.3 Substrate coupling

Substrate coupling in integrated circuits (ICs) is the process whereby a parasitic current flow in the substrate electrically couples devices in different parts of the circuit, or circuits in different parts of the system due to the presence of conduc-tive and capaciconduc-tive path in the silicon substrate [Gha95]. This is illustrated in Figure 2.5. In mixed-signal ICs, the main noise generator are the digital circuits due to their fast switching events. This digital switching noise is injected directly into the substrate through ohmic contacts and/or junction capacitances and then couples to sensitive analog/RF circuits through commonly shared substrate. It has been reported in [Kia98] that the substrate acts as a feedback path where it affects the amplifier small-signal gain, bandwidth, and stability. Not only can the substrate noise degrade the performance of analog/RF circuits, but the digital circuits can be affected as well. It was reported in [Cha99] that the propagation delay of sensitive digital blocks also increases. The ever increasing complexity of the ICs and the decreasing feature size of CMOS technology, which enables devices to operate at a very high speed, makes the effects of substrate coupling becoming even more severe.

N-Well

Digital circuitry Analog/RF circuitry

P-substrate Dig.Gnd Ana.Gnd Subs Subs Subs S _D G In Dig. VDD Out VDD Out In C_well Gnd G D S

Figure 2.5: Substrate coupling via commonly shared substrate [Ver98]). A fast switching

digital circuit injects noise into the substrate. This substrate noise can travel, which is then picked up by the sensitive analog/RF circuit.

2.2 Substrate Noise and Its Coupling Mechanisms

As described earlier, noise is generally defined as unwanted signal that degrades the performance of a system. In mixed-signal ICs, the noise itself is divided into two major categories: random noise and deterministic noise. Random noise is originated from active as well as passive devices. Random noise includes thermal noise, flicker noise, and shot noise. These random noises are quantified using the noise figure (NF) and signal-to-noise ratio (SNR) parameters [AK06]. De-terministic noise includes digital switching noise, and RF circuit noise. These deterministic noises can be quantified both in frequency domain and time do-main. The digital switching noise is often the dominant source of deterministic noise in mixed-signal ICs [Ver98].

The mechanisms for substrate noise injection, transmission, and reception are discussed in the following sections.

2.2.1 Substrate noise injection

A mixed-signal integrated circuit typically consists of active and passive devices. Active devices include bipolar junction transistors, MOS transistors, and diodes. Passive devices typically include resistors, inductors, capacitors, and intercon-nects. This section describes different substrate noise injection mechanisms.

2.2 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 19

Resistive injection into the substrate

Impact ionization current Figure 2.6 illustrates the cross-section of PMOS and

NMOS devices. When a MOS transistor is biased in the saturation regime, a high electric field develops in the depletion region of the channel near the drain. Due to this high electric field, some fraction of the carriers in this region will gain enough energy to become ”hot”. When these hot carriers scatter, they can dissipate excess energy by generating electron-hole pairs [Bri99]. This process is known as impact ionization. Thus, some of the resulting holes (for NMOS case) flow into the substrate resistively creating a substrate current [Gra01]. The con-tribution of impact ionization is included in the noise current models employed by SPICE [AK06]. One example of these models expresses the hot-electron-induced substrate current in semi-analytical form as [Hu81]:

Isub= C1(Vds− Vdsat)Idexp

Ã

C2t1/3ox · x1/2j

Vds− Vdsat

!

(2.5)

where C1and C2are process-related empirically determined parameters, toxis the

oxide thickness, xj is the junction depth, Vds is the drain-to-source voltage, and

Vdsat is the saturation voltage. The empirical coefficients, C1 and C2, can be

de-termined by means of device simulation or measurement and then be incorporated for circuit simulation. Experimental result in [Mer] suggests that hot-electron in-duced substrate current is the dominant cause of substrate noise in NMOSFETs up to at least 100 MHz.

Hot-electron induced current in PMOS devices were also observed [Bri99]. However, in PMOS devices with locally grounded well (with comparable size of NMOS devices) the amount of the hot-electron induced current is considerably smaller due to a lower hole ionization coefficient. Thus, PMOS devices cause lower substrate bounce than comparably sized NMOS devices [Gha95]. It has also been reported in [Bri00] that the relative impact ionization current in their PMOS is about an order of magnitude less than in the NMOS. This makes the contribution of PMOS to hot-electron induced current in the common substrate negligible.

Ohmic guarding In a p-type silicon substrate, p-type diffusions are often used

as substrate taps or guard rings for circuit protection. The p-type diffusions are connected to a certain potential to ensure that the substrate is at a desired potential. If this is not designed properly, however, these diffusion regions can inject a very high level of noise into the substrate. Any voltage bounce on these p-type regions will be distributed throughout the substrate [Gha95]. The p-type diffusion taps on a p-type silicon substrate are illustrated in Figure 2.7.

S

D

Hole injection

p-substrate

G

(a) NMOS transistor

n-well

p-substrate

p

+

_p

+

S

_G

D

(b) PMOS transistor

Figure 2.6: MOS transistors (adapted from [Gha95]). The noise is injected into the

substrate through the junction capacitance: (a) NMOS transistor; (b) PMOS transistor.

Capacitive injection into the substrate

Another mechanism, by which parasitic currents can be injected into the sub-strate, is the capacitive coupling. Figure 2.8a illustrates the cross-section of a bipolar NPN transistor. A bipolar NPN transistor interacts with the substrate through the collector-to-bulk pn-junction capacitance (Cjs). This capacitance

2.2 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 21

p-type substrate p-diffusion (guard ring)

Figure 2.7: P-type diffusion used as guard ring on a p-type silicon substrate [Gha95].

gives a path for the current to propagate into the substrate capacitively. The value of (Cjs) depends on the substrate and collector doping levels, as well as the

bias level of the collector with respect to the substrate [Gha95]. The capacitance formula for abrupt pn junction can be expressed as:

Cjs= s qε 2 (ψbi+ Vcs) µ NCNS NC+ NS ¶ (2.6) where NC and NSare the collector and the substrate doping levels, respectively;

ψbi is the built-in potential of the junction; and Vcs is the collector-to-substrate

bias voltage [Gha95]. Lateral pnp transistors injects the noise through the base-to-substrate capacitance (Figure 2.8b) [Gha95].

The capacitive injections can also be caused by MOS transistors as illustrated in Figure 2.6. Voltage fluctuations on the source or drain can couple to the substrate through the source-to-substrate and drain-to-substrate junction capaci-tances. The gate also contributes in injecting the noise into the substrate through gate oxide and channel capacitances [Bri00].

2.2.2 Substrate noise transmission

After having discussed the mechanisms of noise injection into the substrate, it is essential to know how the noise propagates from one device to another or from one circuit to another. Therefore, it is important to understand the physics of the substrate in order to be able to model the substrate. The distributed form of Ohm’s law shown below holds for a lossy dielectric, i.e. silicon [Gha95]:

~

p-substrate

n

+

_-type

C

_js

C(n) B(p)

E(n

+

₎

(a) NPN transistor

p-substrate

C

_bs

C(p

+

₎

B(n)

E(p

+

₎

(b) Lateral PNP transistor

Figure 2.8: Bipolar transistor capacitive coupling to the substrate (adapted from

[Gha95]): (a) in NPN transistor the noise is injected through the pn junction; (b) in lateral PNP transistor the noise in injected through the base-to-substrate capacitance.

where J is the current density in the substrate (A/cm2_{), ~E is the electric field}

strength (V/cm), σ is the conductivity and ε is the dielectric permittivity of the silicon. The Ohm’s law consists of real part and imaginary part, namely conductive behavior and capacitive behavior, respectively.

2.2 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 23

Resistive effect

The conductivity σ inside a doped semiconductor depends on the carrier concen-tration and the mobility as given by:

σ = q(pµp+ nµn) (2.8)

where q is the electron charge, µpand µn represent the mobility of the n-carriers

and p-carriers, and p and n stand for the respective carrier densities. The µpand

µnare functions of total semiconductor doping and temperature [Dut93], [Ver95].

Capacitive effect

Imaginary part of Eq. 2.7 expresses the capacitive behavior of the silicon. Silicon has a relative dielectric constant εrSi = 11.7 which gives the absolute dielectric

constant: εSi= εrSiε0= 1.035 · pF cm ¸ (2.9) Silicon substrate can be modeled as an RC network, which behaves conductively and capacitively as depicted in Figure 2.9. However, for homogeneous silicon substrate, the capacitive behavior starts to occurs at relatively high frequencies. The admittance Ys of the RC network shown in Figure 2.9a can be expressed in

frequency domain by:

Ys= 1 + sRsCs

Rs

=1 + jωTs Rs

(2.10) Therefore, Eq. 2.8 and Eq. 2.9 lead to a substrate time constant, Tsgiven by the

expression below: Ts= RsCs= ρsdl dA · εsdA dl = εrSiε0 q(pµp+ nµn) (2.11)

which is now independent of the piece dimensions. Figure 2.9b suggests that for low frequencies the substrate resistance Rs is more dominant and, therefore, the

associated capacitance Cscan be neglected. As the frequency increases (ω = 2πf ),

the capacitive effect rises to become equal to the resistive effect at the cut-off fre-quency, fT, defined by [Pfo]:

1 Rs = ωTCs= 2πfTCs⇒ fT= 1 2πTs = q(pµp+ nµn) 2πεrSiε0 (2.12) The minimum fTis achieved for a lightly-doped p-type substrate, because

dl

dA

≡

R

_S

=

C

_S

(a) RC model of silicon

106 108 1010 1012 0 5 10 15 Frequency (GHz) 10log(|Y s |R s ) (dB) +3 dB

(b) Conductive and capacitive behavior of a 3.5 Ω-cm silicon

Figure 2.9: Model and behavior of a piece of homogeneous silicon: (a) silicon is modeled

by an RC network; (b) at low frequencies, the silicon substrate behaves conductively, thus modeled by resistance. At high frequencies, the silicon substrate behaves capacitively, thus modeled by capacitance.

2.3 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 25

2.2.3 Substrate noise reception

The noise reception of many devices such as bipolar transistors, capacitors, re-sistors, and interconnect lines, is mainly by means of capacitive sensing. The junction with the substrate in lateral PNP devices is formed by n-type base re-gion. That is why, if the PNP device is used in a gain stage, the base of the device must be carefully shielded or connected to a low impedance node. Otherwise the substrate noise will be amplified by the gain of the circuit [Gha95].

Body-to-Drain Gain ~ G_mbV_bs~cG_mVbs G S Cgs V_b G_mV_gs G_mbV_{bs D V} body Zsub S V_b Csb GmbVbs _D R_d R_d

Figure 2.10: Body effect in MOSFETs [Ver98].

In addition to capacitive reception, there is another noise reception mechanism in MOS devices due to the body effect. The threshold voltage of an MOS transis-tor is a function with strong dependency on the substrate potential, which for a uniform surface impurity concentration NAis given by [Gra01]:

Vt= Vt0+ √ 2qεNA Cox ³p 2φf+ VSB− p 2φf ´ (2.13) where Vtis the threshold voltage, ε is the silicon dielectric permittivity, Coxis the

oxide capacitance per unit area, 2φf is the surface inversion potential and VSBis

the source-to-body potential. It is explained in [Gra01] that the body effect can be represented by a linearized model parameter gmbin the small-signal device model.

By shorting the gate and the source of the MOS transistors (see Figure 2.10), a gain stage is created between the substrate S and the drain D [Gha95]. A suitable approximation in [Gra01] shows that:

gmb gm = √ 2qεNA 2Cox √ 2φf+ Vsb (2.14) where gm is the small-signal transconductance of the device. The parameter gm

relates the drain current to the gate-to-source voltage.

While capacitive reception of the noise is significant at high frequencies, the body effect can be an issue at low frequencies [Gha95].

2.3 Impact of Substrate Noise on Circuits’ Performance: Some

Examples

Analog/RF circuits are known to be prone to substrate noise. However, it is worth mentioning that digital circuits are not immune from substrate noise either. The noise is often generated from logic gates switching activities and glitch transients. This noise is then injected into the substrate through capacitive coupling and impact ionization. Further, this noise propagates through the substrate and is subsequently received by active devices through capacitive coupling and the body effect. This creates delay effect which can be seen in an increasing datapath, thus possibly exceeding the pre-defined clock period [Cha99].

Measured results on the effects caused by logical control pulses on the behavior of OPAMPs are reported in [Cat95]. Heavy distortion was observed at the output of an on-chip OPAMP caused by a differentiation of the interfering substrate noise. Another important effect observed was the phase shift of the analog signal. Phase-locked loops (PLLs) are essential circuit blocks in RF and mixed-signal integrated circuits. Not only are they used as on-chip clock generators to synthe-size and de-skew a higher internal frequency from the external lower frequency, but also as clock recovery systems [Raz03]. The presence of partially-correlated substrate noise poses a new challenge to predicting PLL jitter [Cha04]. Sub-strate noise mostly arises due to impulsive charge injection during gate switching [Cha04]. Much research work has been conducted and results produced on how to reduce substrate noise or how to protect sensitive circuits. However, without detailed coupling information, a designer tends to over-design the safety-measures resulting in an extensive use of guard rings that consume a lot of space. Therefore, a cyclostationary noise model that describes the substrate noise-to-jitter transfer characteristic for CMOS ring oscillator-based PLLs on epitaxial substrate was proposed in [Cha04].

Noise coupling from a digital noise-generating circuit through the power sup-ply/substrate into an analog phase-locked loop (PLL) is analyzed for different power supply schemes in [Lar01], where the PLLs were built in a standard low-resistivity substrate process. The first scheme is to have the digital circuit and the analog PLL to share both Vddand Vss. The result shows that the main jitter

source is the supply coupling into the VCO. The second scheme is to have separate Vdd and Vss for the digital circuit and the analog PLL. This configuration causes

substrate noise to couple into the loop filter node due to the parasitic resistances in the epi layer below the MOS transistor used as a filter capacitor. The third scheme is to have a separate Vdd for the analog PLL but still shares the same Vss

with the digital circuit. This configuration exhibits far less jitter than the other two configurations. The main cause of jitter in this case are delay variations in the feedback divider that mix the PLL reference frequency into a low-frequency

2.4 STATE-OF-THE-ART SUBSTRATE NOISE SUPPRESSION TECHNIQUES 27 beat note. If this beat note frequency is lower than the PLL bandwidth, the PLL tracks the beat note. This occurs only when a harmonic of the clock of the noise generating digital circuit is close to the reference clock driving the PLL.

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver was investigated analytically and ex-perimentally in [Xu01]. In this work, substrate noise caused by a single digital transition and received capacitively by a sensor is first studied. The experimental results suggest that the substrate noise is linear function of the coupling capaci-tance when the trise/fallis constant. With knowledge of the substrate noise caused

by a single digital transition, the total substrate noise induced by a digital circuit emulator can be calculated as the sum of noise components resulting from each of the digital transitions. When the digital circuit emulator is inactive, the LNA output spectrum has a single -44 dBm tone at 1.575 GHz. However, when the digital circuit emulator is turned on, the LNA output spectrum shows -60 dBm at 1.575 GHz.

2.4 State-of-the-art Substrate Noise Suppression Techniques

It was described earlier that substrate noise can really degrade the overall system-on-chip performance. Therefore, the substrate noise generated by the noisy circuit has to be suppressed or blocked so that it does not disturb the sensitive circuit. Many substrate noise suppression techniques exist at research level as well as industrial level. In this section, state-of-the-art substrate noise suppression tech-niques are thoroughly discussed.

Guard ring In [Wel98], an industrial frequency multiplier PLL for clock generation

is used as test circuit. A large noise generator consisting of 5 output buffers in series was placed next to the PLL. It was built in a 0.72 micron epitaxial process with approximately 1800 transistors. In this work, simplifications were made to investigate the effect of substrate noise from the noise generator onto the VCO jitter. The sensitive analog circuits are protected by both ohmic and well guard rings. Six different guarding structures were chosen to evaluate guarding techniques which include: no guard, no guard with backplane contact, p+ _guard

ring, p+ _{guard ring with a backplane contact, ohmic guarding in the VCO, and}

both ohmic guarding and p+_{guard ring in the VCO. The p}+_{guard ring and ohmic}

guarding are both ohmic guard structures but the p+ _{guard ring is a single ring}

placed around the entire section of the analog devices while the ohmic guarding is formed by many ohmic guard bands placed as close as possible to all sensitive devices not in well regions. When no pin parasitics are considered, protection with backplane only provides the best jitter performance followed by p+ _guard

VCO, ohmic guarding in the VCO, and lastly the p+ _{guard ring. However, when}

the pin parasitics, especially inductance, are considered, the power supply value deteriorates due to the switching current flowing through the pin. Not only did the pin parasitics increase the amount of jitter for each guarding structure, but the effectiveness of each configuration also changed. In this case, configuration that includes both ohmic guarding and p+ _{guard ring shows the worst jitter,}

even worse than without applying any protection. The reason for this is that the p+ _{guard ring was biased through the analog ground line. Although the bulk}

fluctuation remained low, the substrate current is captured by the low-ohmic guard ring and flows through the analog ground node causing ground bounce to the sensitive devices. Biasing the p+ _{guard ring to the digital ground node causes}

less analog ground bounce but increases the fluctuation on the bulk substrate since the ground bounce on the digital ground line is greater due to the switching current activities. A solution to this problem is to hook the p+ _{guard ring to}

separate power supply.

Silicon-on-Insulator (SOI) technology was used by many for substrate crosstalk sup-pression as described in [Ank05], [Ham00], [Kum01], [Mae01], [Ras97], [Ste04], [Hir01], and [Viv95]. In [Ank05], it has been proven that the use of very-low-resistivity (LR) silicon (6 -10 mΩ-cm) forming an LR-SOI structure can lower the crosstalk significantly for all frequencies when compared to both medium-resistivity (9 -15 Ω-cm) and high-medium-resistivity silicon (800 -1400 Ω-cm). The fabri-cation scheme used field oxide isolation followed by standard RCA cleaning and growth of a thinner oxide, which represents the isolating layer in SOI. The low crosstalk for the LR-SOI is the result of effective shunting of the signal to ground through the low-resistive substrate. Draining the signal to the backside ground is also proven effective as explained in the previous example [Wel98]. An additional advantage of the low-resistivity substrate is that the crosstalk is insensitive to re-laxation capacitive effects, due to the high doping level as confirmed by Eq. 2.12. This experiment also shows that an effective substrate ground is crucial. The measurement on dedicated test structures show an improvement in the range of 20-40 dB for low resistivity SOI substrate compared to high resistivity SOI sub-strate.

Buried layer and deep trench isolation are used for isolation in a BiCMOS

technol-ogy [Bla]. Figure 2.11a shows isolation scheme that includes buried layer, sinkers, and deep trench in a BiCMOS technology. Firstly, the channel stop region which is three orders of magnitude less resistive than the substrate will increase the isolation. Secondly, the buried layers and the sinker are roughly four orders of magnitude more conductive than the bulk substrate. The buried layers and the sinker will guide and drain out carriers when connected to a low impedance AC ground. However, buried layers may also provide a low impedance path for

sub-2.4 STATE-OF-THE-ART SUBSTRATE NOISE SUPPRESSION TECHNIQUES 29 strate noise to travel into a sensitive area. In this case, the buried layer must be broken to increase the isolation. It has been proven in [Tak] that the break in buried layer combined with the addition of a double guard ring provided a 20x improvement in the isolation.

p+ p +si n k e r p+ p-

silicon (~12

_ΩΩΩΩ

-cm)

p

p

(~ 0.2 ΩΩΩΩ -cm)

n-well

(~10

ΩΩΩΩ

-cm)

n

+ buried layer (~ 0.005 ΩΩΩΩ-cm) _dee p t re n c h contact

(a) Deep trench in addition to buried-layer and sinker isolations.

N+ _N+ p-_{silicon (~12} ΩΩΩΩ_-cm) p+_{buried layer} (~0.005 ΩΩΩΩ-cm) n+_{buried layer (~0.005} ΩΩΩΩ_-cm) n +s in k e r n +s in k e r p epitaxial layer (~1 ΩΩΩΩ-cm)

(b) NMOS with triple-well isolation.

Figure 2.11: BiCMOS cross-section with relative resistivities [Bla]: (a) deep trench

provides physical noise blockage in addition to buried layer and sinker isolations; (b) triple-well isolation.

Triple-well isolation shown in Figure 2.11b is now commonly used in most CMOS

processes at 0.18 nm and below [Bla]. The triple-well provides a means to isolation of n-type devices that normally exist in the p-type substrate. Redmond in [Red]

presented a result of using triple-well isolation. It provided ∼20 dB better isolation when compared to p+ _{guard ring at 100 MHz. But no improvement at 10 GHz.}

Therefore, the effectiveness of triple-well isolation strongly depends on the signal frequency and many other aspects such as doping levels, grounding scheme, and package parasitics.

Faraday cage is one of the most common isolation structures used at radio

fre-quencies. Some works on faraday cage can be found in [Wu01], [Ste04], and [Cho05]. In [Wu01], the faraday cage scheme for crosstalk suppression was formed by means of through-wafer via technology. The faraday cage structure consists of a ring of grounded vias encircling sensitive or noise portions of a chip. The via technology features aspect ratio as high as 14 [Wu00], through-wafer holes filled with electroplated Cu and lined with a silicon nitride barrier layer as illustrated in Figure 2.12a. As shown in Figure 2.12b, when a 77-µm substrate and 10-µm diameter vias with an aspect ratio close to 8 were used, and the noise transmitter and the noise receiver are separated by 100 µm, the faraday cage reduced the crosstalk by 40 dB at 1 GHz and 36 dB at 5 GHz.

Porous Si trench has been used to provide radio frequency isolation in Si because

of its semi-insulating property [Kim02]. Heavily doped p-type Si substrates with resistivity less than 0.01 Ω-cm. Localized porous silicon (PS) trench was formed between the noise generator and the noise sensor. Afterwards, wafer lapping by mechanical polishing was performed to remove the conductive silicon below PS trench, enabling a through-wafer PS trench (see Figure 2.13). The standard thickness of the Si chip is approximately 250 µm. Reduction of crosstalk by 70 dB at 2 GHz and 45 dB at 8 GHz was demonstrated between Al pads with 800 µm separation on p+ _Si.

2.5 Summary

Crosstalk may take place through several coupling mechanisms, i.e. radiative coupling, circuit coupling, and substrate coupling. Radiative coupling itself is divided into three subcategories: capacitive coupling, which usually refers to cou-pling within one system due to electric field; magnetic coucou-pling, which also usually refers to coupling within one system due to magnetic field; and electromagnetic coupling, which usually refers to coupling between different system due to electric field, magnetic field, or both.

Circuit coupling takes place through the interconnects such as power supply and ground connections which are shared by different circuit blocks, e.g. digital