Wafer-level packaging technology for RF applications based on a rigid low-loss spacer substrate

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Wafer-Level Packaging Technology for RF

Applications Based on a Rigid Low-Loss Spacer

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Wafer-Level Packaging Technology

for RF Applications

Based on a Rigid Low-Loss Spacer Substrate

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof. dr. ir. J. T. Fokkema, voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op maandag 16 oktober 2006 om 12:30 uur

door

Alexander POLYAKOV

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Dit proefschrift is goedgekeurd door de promotor: Prof. Dr.-Ing. J.N. Burghartz

Samestelling promotiecommissie:

Rector Magnificus, voorzitter

Prof. Dr.-Ing. J.N. Burghartz, Technische Universiteit Delft, promotor Dr. M. Bartek, Technische Universiteit Delft

Prof. Dr. P.M. Sarro, Technische Universiteit Delft Prof. Dr. P. French, Technische Universiteit Delft Prof. Dr.-Ing. G.Q. Zhang, Technische Universiteit Delft Dr. N.J.A. van Veen, Koninklijke Philips Electronics N.V. Prof. Dr.-Ing. H. Sandmaier, Universität Stuttgart

The work described in this thesis was supported by Koninklijke Philips Electronics N.V.

Alexander Polyakov

Ph.D. thesis, Delft University of Technology

ISBN-10: 90-9021110-1 ISBN-13: 978-90-9021110-7

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Chapter 1. Introduction

1.1. Emergence of wireless communications

The first reported case of wireless communication may be dated back to 1200 BC, when Homer talked about the signal fires of Iliad. It took another 3000 years for the mankind to unravel the mystery of electromagnetic waves. The exceptional ability of the electromagnetic waves for wireless communication has been immediately recognized, so it then took only 42 years from first theoretical prediction by J.C. Maxwell in 1854, to the fist radio demonstration in 1896.

The first radio already highlighted the influence of passive components in overall system design. Remarkably, only one active component (the coherer in the first design, later replaced by the Fleming valve, i.e. vacuum diode), but several passive components were already required to built the first radio wave receiver (Fig. 1.1). Despite indisputable progress in electronic design and fabrication technology, the ratio of passives to active components has only increased, reaching in average 25:1 in a modern handset. Unlike the first radios, modern wireless systems tend to be unobtrusive and embedded. This includes novel technologies for passive component ‘unobtrusive’ integration, which are still contributing significant part of radio design.

Morse printer Choke coils

Coherer

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1.2. Silicon RF ICs and wireless revolution

The first wide-scale adoption of wireless personal communications was in citizen band (CB) radio in the late 1960s [2]. Despite the lack of traffic management and services, it was a clear indication that consumers wanted inexpensive and portable means of communication. The existing technology was not capable to provide portable systems, though. The ‘second wave’ of wireless revolution came with the progress of silicon technology, providing the potential for low-cost, high-volume manufacturing technologies.

Portable electronics, led primary by wireless handheld products, is undergoing an enormous growth in worldwide usage. The RF front-end module is the foundation of these systems, and its integration poses great challenges. In early days GaAs substrates were mainly considered for RF integration, as they are ‘faster’ than silicon-based discrete components and integrated circuits, because of higher electron mobility and three orders of magnitude intrinsic resistivity than silicon (Table 1.1). However, arsenide lacks the silicon's ability to use its oxide form as an ideal insulator, which increases the complexity of its fabrication process, resulting in higher manufacturing costs. Moreover, the thermal conductivity of silicon is three times larger than that of gallium arsenide, thus, the amount of power that a GaAs integrated circuit can handle is severely limited in comparison. As a result, the packaging densities achievable with GaAs are far smaller than those with silicon circuits. Finally, GaAs is more rare and difficult to obtain than silicon, which is the most abundant electropositive element in Earth’s crust.

Table 1.1. Comparison of silicon and GaAs physical properties (at 300K)

Properties Silicon GaAs

Density (g/cm3_{) 2.3}_5.32

Dielectric constant 11.9 13.1

Energy gap (eV) 1.12 1.42

Intrinsic Carrier Concentration (cm-3₎ _{1.45 x 10}10 _{1.79 x 10}6

Intrinsic Debye Length (µm) 24 2250

Intrinsic Resistivity (Ω-cm) 2.3 x 105₁₀8 Mobility (Drift) (cm2_{/V-s) µ} n electrons 1500 8500 Mobility (Drift) (cm2_{/V-s) µ} p holes 475 400 Thermal Conductivity (W/cm - ºC) 1.5 0.46

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the RF/analog domain heterojunction bipolar transistors (HBTs) have been historically favored over CMOS owing to their advantages in higher transconductance, lower 1/f noise, better device matching and power management [3]. With recent achievements in SiGe technology, silicon HBTs have outperformed other semiconductors in speed. The best performance of SiGe HBTs so far has been demonstrated with ft of 350 GHz [4]. Consequently, silicon continue to be the dominant material for semiconductor industry while the market for gallium arsenide circuits remained relatively small.

1.3. Role of passive components in RF ICs

Many advances have been made in silicon integration of active devices, while the progress in passive component integration has lagged far behind. Integration of RF/analog circuitry has not advanced so rapidly as that of digital circuitry. For the silicon RF integrated circuit applications, the realization of high quality factor passive components is an important task to be solved imperatively. The integrated passive components own several incontestable advantages to discrete devices. Firstly, obvious, is size reduction, and, what might be more important, increased reliability, because of elimination of solder interconnects. Secondly, for RF networks integrated passive allow easier impedance matching, and minimize interconnect parasitics. But this is confronted with the challenge of microwave performance degradation on conventional silicon substrate, due to its higher substrate losses than that of GaAs. There were many methods attempted towards low loss passive networks, so that silicon can be used as a microwave substrate. This includes technologies, based on oxide layers (9 µm-thick [5] or even 25 µm-thick [6] oxide layers on a silicon substrate), use of thick polymer layers (e.g. 6 µm-thick BCB [7]), and others (Table 1.2). Other approaches were based on micromachining techniques, where passive components, mostly inductors, were suspended over cavities or lifted off the wafer plane [8]. Other techniques are based on high resistivity (HR) silicon substrates [9], that, however, are prone to surface channel effects [10]. Drawbacks of these techniques may be a substantial increase of manufacturing costs and limited compatibility with other fabrication processes. In addition, these passive components consume valuable real estate. They may occupy more than 50 % of the silicon area. Table 1.2. Insertion losses of CPW using different technologies

Substrate Dielectric Metal _{[dB/mm @ 4 GHz]}Insertion loss HR – Si (4 kΩ-cm) 0.9 µm SiO2 1 µm Al 0.17 [9]

Si ( 20 Ω-cm) 10 µm polyamide 1 µm Al 0.19 [11]

AF45 glass - 3 µm Al 0.05 [12]

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Moreover, for RF circuits, operating in the microvolt range or mixed signal circuitry, substrate coupling caused by the finite resistivity of the silicon substrate, is a major concern. Integration of dissimilar signals requires large isolation between them. Though solutions have been proposed by using high resistivity silicon or N-well trenches, the isolation levels achieved are insufficient. For multiple voltage levels, distributing power to the digital and RF circuits while simultaneously maintaining isolation and low EMI can be a major challenge. Silicon-on-sapphire (SOS), provides excellent crosstalk isolation and thermal conductivity as well, but still owes prove of large-scale manufacturability [13].

To meet these challenges and fully realize the benefits of emerging device technologies and develop competitive products for new applications, new enabling packaging technologies may be considered.

1.4. Wafer-level packaging for RF applications

The shift from discrete to integrated devices and the pace for increased functionality, which resulted in the need for novel components (such as MEMS and integrated antennas), requires new enabling technologies. However, the extremely high production volume in communications technology today makes the chip manufacturers very cautious in modifying their fabrication processes. Moreover, ability of integration on silicon is limited by its physical properties. Thus, it is believed that a new packaging technology may best address these problems, by providing some of the functionality needed. The packaging process may be considered as a post-process module, which may extend functionality of the chip without the need to modify the core IC process.

The very common approach widely investigated these days is system-in-package (SiP) (Fig. 1.2). Essentially, SiP technology combines multiple ICs, discrete and passives components into a single package. This provides a complete functional system in one module that can be processed much like a standard component during board assembly. In contrast with system-on-chip (SoC), where a single die is used, SiP offers merge of different technologies/substrates in a single package.

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the limiting factor, causing lower IC performance. The difficulty with driving interconnects at low supply voltages makes that problem even worse. For continued improvement in off-chip performance, packaging technology must scale with IC scaling. With the increased impact of packaging on electronic products, the industry tends to adopt a more integrated approach to semiconductor packaging and systems design. As the result, wafer-level packaging (WLP) technologies are now considered.

WLP refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. Wafer-level packaging basically consists of extending the wafer fab processes to include device interconnection and device protection processes. Moreover, packaging at wafer level allows a high degree of process integration, due to the use of fab type processing, such as thin film deposition and photolithography, which decreases cost.

However, for a compete integration of chip functionality, especially RF constituents, new means of passive components integration must be identified. Moreover, combination of RF and digital circuitry on the same chip, may require novel on-chip isolation techniques. New technology concept to meet these requirements is proposed in this thesis.

silicon die

stack of diesembedded components

Carrier Figure 1.2: SoC (left) and SiP (right) approaches.

Figure 1.3: New packaging approach investigated within this thesis.

Low-loss material RF BiCMOS wafer RF passive devices

Through-wafer interconnects

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1.5. Wafer-level packaging technology based on a rigid low-loss

spacer substrate

The wafer-level packaging approach (Fig. 1.3) is based on technology modules, where low loss substrates with high-Q passive networks are combined with conventional IC process wafer, with electrical interconnects formed between them. The fully processed IC wafers are bonded with low-loss material on which passive networks could be fabricated. The subsequent realization of through-wafer electrical interconnects provides redistribution of signal for next step bumping and package to board interconnects.

Different aspects of this approach are examined within this thesis.

1.6. Organization of the thesis

This thesis describes the development of technologies required for on-wafer high-quality passive devices integration (Fig. 1.4).

Chapter 2 provides an overview of existing passive device technologies

including discrete, embedded and integrated devices. Figures of merit and state-of-the-art technologies for integrated passives are presented.

In Chapter 3 a novel approach based on stacked 0-level (wafer-level) packaging for integration of passive devices is presented. Several aspects and potential benefits of such a package are described.

Chapter 4 focuses on low-loss materials for the proposed wafer-level

packaging concept. Several existing candidates, such as glass substrates are analyzed, and novel high-resistivity polysilicon material is presented.

Chapter 5 discusses the limitation of substrate structuring. The influence

of uniform wafer thinning, bulk-micromachining and through-wafer interconnects fabrication on mechanical reliability of a silicon wafer is presented.

Chapter 6 explains the necessary process modules to fabricate composite

wafer-level packages. Techniques for substrate structuring, wafer-level bonding and through-wafer interconnect fabrication are characterized

Examples of potential applications are given in Chapter 7, followed by conclusions and outlook in Chapter 8.

Appendixes A, B, C contain the flowchart for fabrication of composite

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Figure 1.4: Organization of this thesis.

Introduction

Overview of packaging technologies

Wafer-level packaging concept

Spacer substrates

Applications

Conclusions and overview

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References

[1] S. Leinwoll, “From Spark to Satellite: A History of Radio Communication,” ISBN: 068416048X, Scribner 1979.

[2] T.S. Rappaport, “The wireless revolution,” IEEE Communications Magazine, vol. 29, 11, 1991, pp. 52, 61 - 71.

[3] J. Tang, G. Niu, J. Zhenrong, J.D. Cressler, S. Zhang, A.J. Joseph, D.L. Harame, “Modeling and characterization of SiGe HBT low-frequency noise figures-of-merit for RFIC applications,” Trans. on MTT, vol. 50, 11, 2002, pp. 2467 - 2473.

[4] J.-S. Rieh, B. Jagannathan, K.T. Schonenberg, et.al. “SiGe HBTs with cut-off frequency of 350 GHz,” Proc. IEDM 2002, pp. 771 - 774. [5] H. Sakai, “A new millimetre-wave IP-chip on silicon substrate,” Proc.

Asia pacific microwave conference 1995, pp. 291-294.

[6] I.H. Jeong, et. al., “High quality RF passive integration using thick oxide manufacturing technology,” Proc. ECTC 2002, pp. 1007 - 1011. [7] X. Huo, “Silicon-based high-Q inductors incorporating electroplated

copper and low-K BCB dielectric,” IEEE EDL, vol. 23, 9, 2002, pp. 520 - 522.

[8] X.-N. Wang, Y. Zhou, B.-C. Cai, “Fabrication and performance of a novel suspended RF spiral inductor,” IEEE TED, vol. 51, 5, 2004, pp. 814 - 816.

[9] A.C. Reyes, “Silicon as Microwave Substrate,” Proc. IEDM 1995, pp. 1759 - 1762.

[10] B. Rong, L.K. Nanver, J.N. Burghartz, A.B.M. Jansman, A.G.R. Evans, B. Rejaei, “C-V Characterization of MOS Capacitors on High Resistivity Silicon Substrate,” Proc. ESSDERC 2003, pp. 489 - 492.

[11] G.E. Ponchak, A. Margomenos, L.P.B. Katehi, “Low-loss CPW on low-resistivity Si substrates with a micromachined polyimide interface layer for RFIC interconnects,” Trans. on MTT, vol. 49, 5, 2001, pp. 866 - 870.

[12] P.M. Mendes, J. H. Correia, M. Bartek, J.N. Burghartz, “Design and Analysis of a 6 GHz Chip Antenna on Glass Substrates for Integration with RF/Wireless Microsystems,” 2003 IEEE AP-S, vol. 2, 2003, pp. 667 - 670.

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Chapter 2. RF packaging and

integration of passive devices

2.1. Introduction

The ever expanding wireless consumer market presents great challenges for the product designer in terms of performance, size and cost. More functionality is being added with each generation, yet the product’s size continues to shrink. With such a trend packaging starts to play an increasingly important role in the overall system design. Furthermore, the integration of passive components, such as capacitors, inductors, resistors is of extreme importance, as they outnumber the active devices in RF front-end systems and are comparably large and thus costly. As passive components are integrated, however, the quality factors achievable tend to be rather low, thus affecting the system performance. In this chapter it is illustrated how wafer-level chip scale packaging can be instrumental in providing both a low-cost and small-form-factor package as well as a solution to the integration of high-quality passive components.

2.2. Packaging roadmap

The term ‘electronic packaging’ refers to a variety of techniques for encasing electronic components, including integrated circuits (IC’s), so that they could readily and reliably be implemented in electronic end-products. The package is thus a bridge between the IC and the system, providing,

• physical isolation of an IC from harmful environment, • mechanical support,

• integrity and distribution of signals, • heat dissipation and management.

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Issues relating to the integrity and distribution of signals are the coupling of dc, RF, and in some cases control or logic signals into and out of an integrated circuit or system. This should ideally be accomplished without any degradation in the performance of the electronic components contained within the package.

The package must also provide thermal management and heat sinking for the internal active devices to maintain a stable and sufficiently low operating temperature so that optimum performance and maximum lifetime is ensured.

2.2.1. Classification of IC packaging

The packaging flow can be divided into four levels: • 0-level: device encapsulation;

• 1st_{-level: device-to-package interconnection;} • 2nd_{-level: package-to-board interconnection;} • 3rd_{-level: board to backplane interconnection.}

These levels describe how the ICs are protected and interconnected. They may or may not be relevant, depending on the application. For example, 3rd -level packaging is rarely present in hand-held systems, which typically contain only one single board.

0-level packaging

The problem of device encapsulation at wafer-level (0-level) is of particular importance when dealing with MEMS structures (Fig. 2.1). In contrast to silicon IC’s, where encapsulation of pn-junctions is inherited in the fabrication process, MEMS systems typically contain fragile and mechanically sensitive parts. Die separation and hermetic encapsulation are therefore indispensable. The conventional die separation method is based on cutting by using a diamond blade. The wafer and the blade are cooled by a strong water beam, while the blade rotates at some 45000 RPM. For the standard IC wafers this is not a problem, but MEMS structures exposed to a water beam and debris may break or collapse. Hence, a protection prior to the die separation is required.

The capping of MEMS structures is a commonly used solution, but the lack of a suitable mass-manufacturable packaging technology appears to be one of the main obstacles to the rapid commercialisation of MEMS technology.

1st_{–level packaging}

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frequencies (RF). The parasitic inductance of an isolated bond wire amounts to ~1 nH/mm. While at several millimeter length bond wires thus lead to considerable parasitic inductances that make the design of modern packaged RF systems extremely difficult, it has been proposed to exploit that self-inductance of bond wires for the integration of inductors. In volume production, however, wire bonding is costly since it is a serial rather than a batch process. Also the control of the wire length and loop shape is a very difficult task. Nevertheless, wire bonding has established itself as a very robust and inexpensive chip-to-package interconnect process that continues to be prominent in IC packaging technology (Fig. 2.3).

Carrier wafer MEMS structure Cap

Figure 2.1: Schematic view of 0-level packaging.

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Figure 2.3: Fine-pitch multi-layer wire bonding technology [2].

Urgent needs for an improved chip-to-package interconnect technology come from microprocessors and RF ICs. Processor chips are increasing in size with each new generation, due to the added functionality, so that the input/output (I/O) count becomes reduced relatively to the chip area. In RF applications, with integrated automotive sensor technologies operating at 24-90 GHz at the horizon, wire bonding needs to be replaced by an interconnect technology that adds far less parastics, i.e. flip-chip interconnects.

Flip-chip attachment is an attractive alternative to wire bonding. The conductive path between chip and package can be shortened by forming a metal bump that is placed onto the die surface. The bumped die is then flipped over and face down directly attached to the circuit board. The flip chip connection may be formed by either using solder or using conductive adhesive. By far the most commonly used flip-chip interconnects are solder, in either eutectic (63 % Sn, 37 % Pb) or high Pb (97 % Pb, 3 % Sn) compositions. Nowadays, the industry is seeking to remove lead from packages because of legislation in Europe driving towards more environmentally friendly products (green packages). The eutectic (or near eutectic) Sn-Ag-Cu alloys are under considerations. The flip-chip technology, often requires under-fill materials to control mechanical stresses that come from the difference in thermal expansion coefficients of silicon and the carrier material. The under-filling uses expensive material, which also has a negative impact on throughput. Moreover, additional space is needed at the periphery of the chip to unsure a complete underfill of the die. The amount of space required can be larger that occupied by the wire bond attachment. From an RF point of view, however, the solder balls have less than 10 % inductance compared to a wire bond and are thus attractive for RF applications. Unfortunately, at present time, they come at the price of lower throughput and possible larger board space required. Flip-chip packaging is currently about 2-3 times more costly than conventional wire bonding on a per-pin basis.

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1000) and a finer pitch (down to 100 µm) are achievable compared to wire bonding. Parasitics are about two times lower than those with bond wiring. Other advantages are the lower cost, and lighter weight and higher throughput. Disadvantages are, that each die requires its own tape, patterned for the particular bonding configuration and the capital expense of the TAB bonding equipment. For these reasons, TAB has typically been limited to high-volume production applications.

2nd_{–level packaging}

The 2nd_{-level assembly methods may be classified by the type of assembly:} insertion mount (e.g. Dual In-line Package (DIP)), socket mount (e.g. Pin Grid Array (PGA)) and surface mount (e.g. Quad-Flat-Pack (QFP)). Historically the first type (Fig. 2.4) was the insertion mount metal can, followed later by DIP packages. In the 1980s, with growing silicon integration levels, they were replaced by surface mount components (e.g. plastic QFP). In the late 1980s Ball Grid Array (BGA) arrived to be the first pinless package, shortly followed by Chip-Scale Packaging (CSP). As for portable and hand-held products surface mount components dominate due to their small form-factor. Among them, flip-chip BGA and CSPs are preferred for advanced RF performance. The QFPs, however, are more cost effective especially at low pin count (< 250).

DIP Metal Can 1970 1980 1990 2000 LQFP TSSOP BGA CSP

Figure 2.4: Package type evolution over time.

2.2.2. Chip-scale and wafer-level packaging

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The demand for higher density and enhanced functionality has promoted a new class of packages. The concept of chip-size packaging (CSP) evolved in the 1990s. CSPs are defined as being only 20 % larger than the original die size and directly surface mountable. In fact, CSPs can be assembled by using standard SMD pick-and-place systems. By definition, the package is only slightly larger than the silicon die. Again, long term reliability of solder joints, due to CTE mismatch, is the critical issue. There are two generic types of CSPs: designs that physically decouple the silicon from the solder joint attachment layer, and those that do not. Many approaches utilize a compliant layer to separate the die from the substrate, such as elastomeric layers. Other approaches focus on flexible substrates as the chip carrier. However, the name ‘Chip-Scale Package’ does not indicate how the package is constructed, but only gives information about its size. Therefore, four major classes of CSPs based on their structure are defined as (Fig. 2.5 – 2.8): • flex circuit interpose, which incorporates a flexible circuit

rerouting technique to connect the die bond pads to the solder bumps,

• rigid substrate interpose, which utilizes rigid substrates, such as ceramic or organic BGA type interposer,

• custom lead frame, which uses mold resin and support lead frames as package constructing materials,

• wafer-level assembly, which is manufactured in a wafer format. The ultimate level, to which CSPs can be brought in terms of size and cost, can be achieved by using wafer-level technologies (WLP). The wafer-level packaging assumes that all dies on the wafer are simultaneously processed throughout the entire packaging process flow, so that after die separation the package is ready for mounting. The obvious benefits of wafer-level packages are that they are fabricated and tested at wafer level. It is clear that the cost of the WLP goes down as the wafer size increases and as the die size is reduced (as for die fabrication), unlike other packaging techniques that are assembled after separation of the die from the wafers.

There are several competing kinds of the WLP technology including: • Redistribution technology, e.g. Flip Chip ultra CSP™ (Fig. 2.9), • Encapsulated technology, e.g. ShellCSP developed by

Shellcase (Fig. 2.10),

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die

die attach polyimide

bonding lead encapsulant

Figure 2.5: Flex-based CSP as an example of flex circuit interpose CSP.

Die

Ceramic substrate Via

Stud bump

Figure 2.6: Rigid substrate interpose CSP.

die

wire

_{die attach}

Cu leadframe exposed pad

Figure 2.7: Custom lead frame CSP.

die

polymer redistribution layer

Figure 2.8: Wafer-level assembly. BCB 2

UBM BCB 1 _solder

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Glass

Silicon

Solder bump

Figure 2.10: Shellcase ShellCSP.

Silicon

Flexible link Solder bump

Figure 2.11: Tessera’s WAVE™ WL CSP.

2.3. Properties of an RF package

An electronic package, in general, will always degrade the electrical performance of the components that it contains. The performance degradation stems from a number of fundamental physical effects:

• Input and output port rejection and insertion losses: These losses are related to the inability to precisely control impedance levels at the package terminals as well as the resistive losses associated with transitioning the RF signal through the package walls.

• Insertion and rejection losses associated with the interior of the

package: These losses are associated with transmission lines

within the package as well as signal reflection and insertion resulting from interconnecting active chips and other components within the package. Depending on the methods of assembly, the variability of these losses may be significant for chip and wire assembly. These effects become worse with increasing frequency. • Package-generated resonances and related effects: Resonances

may be excited by active circuit elements within the package and may be present within or outside of the desired bandwidth. In addition, package shielding effects, which are due both to higher order waveguide mode propagation and to the close proximity of the enclosing walls, can seriously perturb microstrip propagation and the effects of discontinuities within the package.

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form factor packaging technologies, which replace the traditional concepts and help to enable the integration and miniaturization of the system, are expected to do so at a very small (if any) cost premium once the product reaches high volume [3].

Table 2.1 summarizes key requirements for different components of RF front-end systems.

Table 2.1. Key requirements on different component for RF front-end systems.

Section Components Typical I/O Drivers

RF

PA

LNA, Mixer 10-50

Size, cost, thermal management

Size, passive device integration

IF Synthesizer, modulator, _baseband 20-100 Size, cost Digital DSP, RAM Up to ~500 Size

Wireless connectivity becomes a standard feature for a variety of devices, such as PDAs and notebooks. A trend toward modular approaches is thus emerging. For RF front-end passive components integration becomes a limiting factor.

2.4. Passive components in RF front-end systems

The primary challenge for RF radio systems development is that circuits must be optimized for performance as well as for power consumption. The overall power consumption of a wireless systems is now dominated by radio, rather than the digital circuitry. RF front-end design has thus a major impact on size and cost of the phone’s battery.

Table 2.2. Active and passive components for selected handheld products.

Product Number of passives Number of actives Passives to actives ratio Sony HandyCam 1329 43 31:1 Motorola StarTac 993 45 22:1 Nokia 2219 432 21 20:1 Ericsson 338 359 25 14:1

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transformers, baluns, transmission lines, antennas. It is estimated that in a single-mode telephone, passive components account for 90 % of the total device count, 80 % of the total volume, and 70 % of the cost. High-quality passive components are especially prevalent in the RF front-end and radio transceiver sections of the telephone and thus tend to increase proportionally as the number of operating modes (and thus frequency bands) increases. In 2004, 115 billion passive components were assembled into 380 million handsets at an average of 300 components per telephone. Among those, typically 100 to 150 are discrete passives in the front-end and radio transceiver sections [4].

For minimizing the total power consumption, the degree of dissipated power in these passive networks must be limited. Thus, the quality factor of the passive components is of extreme importance.

2.4.1. Quality factor of passive components

The quality factor (Q) of a passive component is defined as the ratio of the stored to the dissipated energy of the component.

cycle

n

oscillatio

one

in

loss

energy

stored

energy

Q

=

2 π

. (2.1)

From that definition it is clear that, in order to minimize the power consumption of the system, the Q-factor of the passive components must be maximized. The definition in (2.1) is fundamental in the sense that it does not specify what stores or dissipates the energy. The subtle distinction between an inductor and an LC tank lies in the intended form of energy storage. For an inductor, only the energy stored in the magnetic field is of interest. Any energy stored in the inductor’s electric field, because of some inevitable parasitic capacitances in a real inductor, is counterproductive. Hence, Q is proportional to the net magnetic energy stored, which is equal to the difference between the peak magnetic and electric energies. An inductor is at self-resonance when the peak magnetic and electric energies are equal. Therefore, Q drops to zero at the resonant frequency. Above the self-resonant frequency, no net magnetic energy is available from an inductor to any external circuit. In contrast, for an LC tank, the energy stored is the sum of the average magnetic and electric energies.

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Metal losses

Metal losses at RF, besides ohmic losses, are also due to the skin effect. At higher frequencies the current tends to concentrate at the outer edge of the conductor (Fig. 2.12), i.e. the current density is higher at the skin of the conductor than in its center. Mathematically the current density is expressed as:

J = e − δ / d_, _(2.2)

where the skin depth is defined as:

πσµω

δ

2 c

= . (2.3)

As a result, when the metal thickness approaches the skin depth, the resistance of the line starts to increase with the square root of frequency. Another effect to consider is current crowding. This effect appears, if two conductive strips are in close proximity so that their inherent magnetic fields cause an induced current in the respective adjacent conductor. The proximity effect of nearby conductors is most prominent for the inner turns of spiral inductor coil .

Figure 2.12: Current crowding.

Substrate losses

Substrate losses are caused by the conductivity of the substrate, which is a particularly crucial problem in silicon technology. First of all, RF potential difference between conductors and RF ground may lead to potential currents in a substrate. Mathematically this can be described as:

sub

p

=

σ

sub

= −

σ

sub

∇

ϕ

J

E

, (2.4)

where φ satisfies Laplace’s equation: 2

_ϕ

₀

∇

=

_. _(2.5)

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loss and a weakening of the apparent magnetic field. In a spiral inductor, e.g., this results in a reduced inductance value and a considerably lower Q:

sub

e

i

ωσ

sub

∇×

J

=

B

. (2.6)

Dominant loss mechanism is therefore defined by substrate resistivity (Fig. 2.13).

2.4.2. Packaging of passive components

The way passive components are designed and built into the systems directly relates to the packaging. Their integration can be accomplished either at the board level by using SMD components (discrete passives), at the package level (embedded passives), or at the device level (integrated passives) (Fig. 2.14). The decision for use of a discrete or an integrated/embedded solution depends on application, cost, performance or perhaps some other metric.

0 5 10 15

Q

_max Eddy Current Regime Resonator Mode Regime Inductor Mode Regime

Silicon resistivity

(O -cm)

0 1 2 3 4 5 6 L (Qmax ) (n H)

L

Q

ma x 0.001 0.1 10 1000 0 5 10 15

Q

_max Eddy Current Regime Resonator Mode Regime Inductor Mode Regime

Silicon resistivity

(O -cm)

0 1 2 3 4 5 6 L (Qmax ) (n H)

L

Q

ma x 0.001 0.1 10 1000

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Passive components

discrete

embedded

integrated

Inside the primary interconnection

substrate

On the surface of process wafer

Figure 2.14: Passive components classification.

Discrete passive components

Traditional passives like resistors, capacitors, and inductors are typically three-dimensional discrete components, which are soldered onto or through the printed or wiring circuit board. In RF circuits, passive components are typically surface mount devices (SMD) on PCBs, that statistically account for about 30 % of the solder joints, 40 % of the board area, and up to 90 % of the placement time. Thus, although discrete passive components demonstrate high quality factors, they consume a large fraction of the board area and the assembly time, and thus become a major limiting factor in the overall system miniaturization and the cost reduction. The electronics assembly industry has responded to that challenge by developing higher speed chip shooters and by producing smaller passive components. In spite of these efforts, the surrounding space for mounting/soldering purposes (‘footprint’) can barely be reduced further. Besides, these solder interconnects have negative impact on the total system reliability. An alternative solution to the growing need for passive components is the integration of multiple passives together within a single package.

Embedded passive components

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passive components. Low-temperature cofired ceramic (LTCC) is often used, because of the relatively low processing temperatures (900 ºC vs. 1500 ºC for HTCC), facilitating the use of low-resistivity metals, such as palladium, silver, copper or gold. In addition, it offers a CTE close to that of silicon and a low dielectric constant and a high resistivity. A 8-layer LTCC process utilizing standard 200 µm-thick Dupont tapes has been used in [6] to fabricate inductors, having maximum measured Q to be 83 for a 6.0 nH inductor. The tapes have a dielectric constant of 7.8 and a loss tangent (tan-δ) of 0.006 at 6 GHz [7]. Typical metal thickness used in this technology is 5-6 µm (gold or silver).

An excellent stability at elevated temperatures and low cost make polymer-based materials such as polyimide, polymer-ceramic, polyimide-glass, and epoxy-glasses (e.g. FR4) attractive for embedding passive components. In spite of their advantages, polymer substrates are likely to adsorb moisture, which can cause corrosion, electrical shorts, and delamination; polymers also have a high CTE (>10 ppm/K) compared to that of silicon (2.6 ppm/K), and a low glass transition temperature (120-300 ºC). When comparing to the dielectric materials used in LTCC and MCM-C technologies, epoxy-based laminates have a higher loss at RF. This technology, however, allows for implementing thick metal lines (17-25 µm), which leads to a reduced dc resistance of the lines and therefore compensates to some extend for the loss in the dielectric material.

Integrated passive components

Integrated passive components are similar to embedded ones, with the difference that they are built directly on the silicon substrate. This therefore allows to arrange impedance terminations and transitions next to the active devices where they are required. At high RF, at which very low inductance and capacitance values are needed for those purposes, it is even not possible to embed the passives due to the associated large parasitics. While thin film integrated passive devices on silicon now offer the desired quality, their size is still too large and thus their cost too high to invite for wide spread adoption. As the frequencies of operation become higher, the inductance and capacitance values required become lower and those size and cost issues tend to vanish. At very high RF, however, these values become so small that they cannot be realized anymore in the form of a discrete component. At this stage designers will need to switch from lumped to distributed elements [8]. The dimensions of those distributed passive components are typically defined by λ/4 and are thus considerably large. Passive components, such as inductors, capacitors or transmission lines, may thus occupy – again – excessive chip area so that the cost issue that was dominant at low RF re-appears.

For integrated resistors there are several technologies that either use

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‘normal’ interconnection lines; for larger values a meander structure is used. Tolerances are about 15 %, with laser tuning values below 1 % have been achieved [10]. As can be seen from Table 2.3, achieving a high Q for resistors is not a great challenge, so they may currently be considered as ‘ideal’ RF components.

Table 2.3. Electrical parameters of resistors available in SiGe and RF CMOS technologies.

Resistor Sheet resistance (Ω/⁯) Tolerance (%) TCR (ppm/°C) Parasitic capacitance (fF/µm2₎ p+ polysilicon 270 10–15 21 0.11 p polysilicon 1600 25 –1105 0.09 n+ diffusion 72 10 1751 1.00 n subcollector 8 15 1460 0.12 TaN metal 142 10 –728 0.03

Integrated capacitors are fabricated by depositing a metal sandwich

structure with a high-k material inbetween the metal plates. Metal-insulator-metal (MIM) capacitors with capacitance values up to 100 pF/mm2 (10 nF/cm2) can be realized. To increase the capacitance per unit area high-k dielectrics, e.g., BaXTiOY, are being introduced.. To face the problem of low capacitance per unit area (~1-3 nF/mm2 for MIM CAP), MOS ‘trench’ capacitors, that are fabricated from silicon containing arrays of dry-etched macropores with 1.5 µm typical diameter and up to 30 µm depth. A high-density capacitance of 25 nF/mm2_{is reported [11].}

Integrated inductors are the most challenging to integrate components.

Spiral inductors typically exhibit the lowest quality factors of the RF passives, since this component suffers considerable from both ohmic losses in metal and substrate losses due to limited conductivity of a substrate. With ohmic losses dominating at low frequencies and substrate losses prevailing at higher frequencies, Q develops a distinct maximum (Fig. 2.15).

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metal loss

substrate loss

ω

Q

Figure 2.15: Quality factor of an inductor as a function of frequency.

Transmission lines are preferably integrated as microstrips instead as

coplanar waveguides, since the microstrips can be built in the multilevel interconnect layers and thus are small and do not suffer from substrate losses. The knowledge in microstrip design is also further developed compared to coplanar wave guides because they were mostly used in the hybrid implementations on printed circuit board. The metal losses of microstrips, however, are comparably large on chip due to small thickness of CMOS/BiCMOS interconnect layers.

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An interesting alternate type of substrate, which combines full dielectric isolation through a silicon-on-insulator (SOI) structure with a FZ-silicon substrate, has been proposed several years ago [20]. Also, silicon-on-sapphire (SOS) substrates can be used for even lower RF losses, but their suitability for volume manufacturing is questionable [21].

Other techniques to maximize Q are focused on novel fabrication techniques. Since the degradation of Q at RF mainly occurs due to substrate currents, some approaches focus on elevating spiral coils above the wafer surface plane after fabrication [22, 23]. Measured Q values of 60 to 85 at 1 GHz have been reported for 5-10 nH integrated coils on unaltered low-resistance silicon. Another approach utilizes bulk-micromachining to remove silicon material under devices to reduce losses. These approaches include thick oxides layers derived from porous silicon formation [24] or bulk-micromachining techniques to suspend inductors over cavities. Although mechanical stability and packaging of such structures are currently questionable as far as mass production goes, a useful quality factors of 20 has been demonstrated for a 7 nH micromachined inductor at 7 GHz [25].

Another problem with integrated inductors, transformers and transmission lines on silicon, which has been mentioned several times now, is their excessive consumption of valuable silicon real estate. Typical passive components, such as inductors in average consume area of 10-100 active devices (transistors). There have been various attempts to address this problem. The concept of backside post-processing has been demonstrated in [26]. The inductors may be fabricated on the backside of silicon wafer, with through-wafer interconnects. Moreover, by using local wafer thinning and HRS substrates, micromaching can be used to integrate microstrips at somewhat larger vertical signal-ground spacing to allow for wider signal lines and thus lower metal loss. The high permittivity of silicon, on the other hand, allows to make the overall transmission line structure compact. The investment of the micromachining post-processing steps thus lead to a better tradeoff in quality and size. Also CPW lines can be reduced in their physical dimensions owing to the high permittivity of silicon. Other approaches focus on design techniques where stacked inductors [27] are used to reduce physical dimensions. Novel ferromagnetic, high-k, or even ferroelectric, and thus tuneable materials are also under investigation [28].

2.5. Wafer-level packaging opportunities

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estate. The alternative method would be to integrate passive components at the package level.

Another major challenge in IC design, especially for mixed-signal ICs, is substrate coupling. This parasitic effect can cause considerable performance degradation, may enforce undesirable design tradeoffs, or may prevent the designer from reaching the required system specifications. The problem lays particularly in the digital switching noise coming from the logic sections of the chip that is coupling to the RF front-end sections.. With the increasing complexity of mixed digital-analog designs, and with the decreasing feature size of current technologies, and taking into account the increasing operating frequency, the substrate coupling has become a key reason for inexplicable design failures and poor yield of mixed-signal ‘system-on-chip’ (SoC) design. Thus, means of isolation are need to be adopted in order to reach the required performance of mixed-signal ICs.

Traditional approaches to meet the above-mentioned challenges have been to use technologies such as multichip module (MCM) or system-in-package (SIP). MCM is a circuit comprised of two or more ICs mounted directly onto a substrate within a single component package that contains only wiring to interconnect ICs and requires two levels of packaging, including a motherboard. For interconnects the industry has categorized multichip modules under the three headings MCM-L, MCM-C, and MCM-D. MCM-L describes high-density, laminated printed circuit boards, MCM-C refers to ceramic substrates, either cofired or having low-dielectric constant. MCM-D covers modules with deposited wiring on silicon substrates or ceramic and metal substrates. The recent efforts have been focused on fabrication of passive devices within the package substrate. This is the so-called SIP approach, which can be seen as an evolution of MCM design. Numerous publications [29, 30] have dealt with the development of three-dimensional LTCC passive components that are critical building blocks in multilayer high-density architectures. Disadvantages of such approaches may be seen in test and burn-in procedures. Traditionally all parts are tested before assembly, while crucial parts are burned in under accelerated aging conditions to minimize the risk of subsequent system failure. Packaged dies should also be burned in because most failures occur in the packaging, and not inside the chip. Beside testing and burn-in issues, the miniaturization of the package is limited by first-level interconnects.

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technologies have been proposed utilizing 0-level packaging approaches for integration of passive components. As their Q-factor at radio frequencies are defined both by metal and substrate losses, techniques, like thick BCB layer [31], using thick Ni/Cu layer, are investigated. Another approach is developed in Tessera W.A.V.E.™ [32] (‘WAVE’ stands for ‘Wide Area Vertical Expansion’). The interconnections routing as well as passive components come in a form of a compliant polyimide-based copper circuit. The main idea behind these technologies is to vertically separate passive components from lossy silicon substrates. Nevertheless, these technologies do not focus on on-chip isolation for cross-talk suppression. In this thesis we propose a wafer-level packaging concept based on a rigid spacer technology that will address both the issue of high-Q passive device integration and of on-chip isolation.

References

[1] K. Toyozawa, K. Fujita, S. Minamide, T. Maeda, “Development of copper wire bonding application technology,” IEEE Trans. on Comp. Hybrids, Manufact. Techn., vol. 13, 4, 1990, pp. 667 - 672.

[2] ASE Group, http://www.aseglobal.com

[3] S. Voss, R. Rice, L. Smith , N. Karim, “IC packaging options for wireless portable applications,” white paper, Amkor Technology Inc., 2002.

[4] “Passive Integration Technology: Targeting Small, Accurate RF Parts,” http://rfdesign.com/images/archive/1102Pulsford40.pdf

[5] J.N. Burghartz, B. Rejaei, “On the Design of RF Spiral Inductors on Silicon,” IEEE TED, vol. 50, 3, 2003, pp. 718 - 729.

[6] M. Rytivaara, “Buried passive elements manufactured in LTCC,” IEE Seminar Packaging and Interconnects at Microwave and mm-Wave Frequencies, June 2000.

[7] L. Devlin, G. Pearson, J. Pittock, B. Hunt, “RF and Microwave Component Development in LTCC,” http://www.cmac.com.

[8] J.N. Burghartz, K.T. Ng, N.P. Pham, B. Rejaei, P. Sarro, “Integrated RF passive components - discrete vs. distributed,” Proc. Device Research Conference, 2001, pp. 113 - 114.

[9] T. Lenihan, L. Schaper, Y. Shi, J. Morcan, K. Fairchild, “Embedded thin-film resistors, capacitors and inductors in flexible polyimide films,” IEPS’96, 1996, pp. 196 - 202.

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[11] F. Roozeboom, R. Elfrink, T.G.S.M. Rijks, J. Verhoeven,

A. Kemmeren, J. van den Meerakker, “High-Density, Low-Loss MOS Capacitors for Integrated RF Decoupling,” Int. J. Microcircuits and Electronic Packaging, vol. 24, 3, 2001, pp. 182 - 196.

[12] R. Dekker, P.G.M. Baltus, H.G.R. Maas, “Substrate Transfer for RF Technologies,” IEEE TED, vol. 50, 3, 2003, pp. 747 - 757.

[13] N.P. Pham, “Silicon micromachining for RF technology,” PhD thesis, Delft University of Technology, 6 May 2003, ISBN 90-6734-235-1. [14] J.N. Burghartz, B. Rejaei, H. Schellevis, “Saddle add-on metallization

for RF-IC technology,” IEEE TED, vol. 51, 3, 2004, pp. 460 - 466. [15] J.M. Lopez-Villegas, J. Samitier, C. Cane, P. Losantos, J. Bausells,

“Improvement of the quality factor of RF integrated inductors by layout optimization,” IEEE Trans. on MTT, vol. 48, 1, 2000, pp. 76 - 83.

[16] S.R. Taub, S.A. Alterovitz, “Silicon Techologies adjust to RF Applications,” Microwaves&RF, vol. 33, 10, 2004, pp. 60 - 74.

[17] B. Rong, L.K. Nanver, J.N. Burghartz, A.B.M. Jansman, A.G.R. Evans, B. Rejaei, “C-V Characterization of MOS Capacitors on High Resistivity Silicon Substrate,” Proc. ESSDERC 2003, pp. 489 - 492. [18] B. Rejaei, D.C. van der Pol, J.L. Tauritz, “Analysis of circular spiral

inductors on CMOS substrates,” Proc. ESSDERC 1999, pp. 672 - 675. [19] M. Spirito, F.M. De Paola, L.K. Nanver, E. Valletta, B. Rong,

B. Rejaei, L.C.N. de Vreede, J.N. Burghartz, “Surface-Passivated High-Resistivity Silicon as a True Microwave Substrate,” IEEE Trans. on MTT, vol. 53, 7, 2005, pp. 2340 - 2347.

[20] A.K. Agrawal, M.C. Driver, M.H. Hanes, H.M. Hobgood, P.G. McMullin, H.C. Nathanson, T.W. O’Keefe, T. J. Smith, J. R. Szendon, R.N. Thomas, “MICROX - An Advanced Silicon Technology for Microwave Circuits up to X-Band,” Proc. IEDM 1991, pp. 687 - 690.

[21] J.N. Burghartz, M. Bartek, B. Rejaei, P.M. Sarro, A. Polyakov, N.P. Pham, E. Boullaard, K.T. Ng, “Substrate Options and Add-On Process Modules for Monolithic RF Silicon Technology,” Proc. The 2002 Bipolar/BiCMOS Circuits and Technology Meeting, 2002, pp. 17 - 23.

[22] J. Zou, J. Chen, C. Liu, J. E. Schutt-Ainé, “Plastic deformation magnetic assembly (PDMA) of out-of-plane microstructures: Technology and application,” JMEMS, vol. 10, 2001, pp. 302 - 309. [23] C.L. Chua, D.K. Fork, K. Van Schuylenbergh, Lu Jeng-Ping

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[24] K. Chong, Y.-H. Xie, K.-W. Yu, D. Huang, M.-C.F. Chang,

“High-performance inductors integrated on porous silicon,” IEEE EDL, vol. 26, 2, 2005, pp. 93 - 95.

[25] H. Lakdawala, X. Zhu, H. Luo, S. Santhanam, L.R. Carley, G.K. Fedder, “Micromachined high-Q inductors in a 0.18-µm copper interconnect low-k dielectric CMOS process,” IEEE J. of Solid-State Circuits, vol. 37, 3, 2002, pp. 394 - 403.

[26] N.P. Pham, P.M. Sarro, K.T. Ng, J.N. Burghartz, “IC-compatible two-level bulk micromachining process module for RF silicon technology,” IEEE TED, vol. 48, 8, 2001, pp. 1756 - 1764.

[27] R.B. Merrill, T.W. Lee, Hong You, R. Rasmussen, L.A. Moberly, “Optimization of high Q integrated inductors for multi-level metal CMOS,” Proc. IEDM 1995, pp. 983 - 986.

[28] Yan Zhuang, B. Rejaei, E. Boellaard, M. Vroubel, J.N. Burghartz, “Integrated solenoid inductors with patterned, sputter-deposited Cr/Fe10/Co90/Cr ferromagnetic cores,” IEEE EDL, vol. 24, 4, 2003, pp. 224 - 226.

[29] J. Lee, K. Lim, S. Pinel, G. DeJean, R. L. Li, C.-H. Lee, M. F. Davis, M. Tentzeris, J. Laskar, “Advanced system-on-package (SOP) multilayer architectures for RF/wireless systems up to millimeter-wave frequency bands,” Proc. Asia-Pacific Microwave Conf., 2003, p. FA5_01.

[30] R.L. Li, G. DeJean, M.M. Tentzeris, J. Laskar, J. Papapolymerou, “LTCC multilayer based CP patch antenna surrounded by a soft-andhard surface for GPS applications,” Proc. IEEE AP-S Symp., 2003, pp. II.651 - II.654.

[31] G. Carchon, S. Jenei, L. Carbonell, M. Van Hove, S. Decoutere, W. De Raedt, K. Maex, E. Beyne, “High-Q RF inductors on standard silicon realized using wafer-level packaging techniques,” 2003 IEEE MTT-S, vol. 2, 2003, pp. 1287 - 1290.

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Chapter 3. RF WLP technology

based on a rigid low-loss spacer

substrates

3.1. Introduction

As shown in Chapter 2, wafer-level packaging (WLP) has been widely accepted as a means to reduce packaging cost, time-to-market, and form factor. Besides, WLP allows for integrating high-Q passive components with minimum interconnect parasitics within the circuit, which is particularly important at very high RF. On-chip isolation for crosstalk suppression within a wafer-level package, however, has not been addressed to a large extend. In this chapter a packaging concept based on a low-loss spacer substrate is introduced. Theoretical analyses and fabrication aspects of the proposed WLP are discussed.

3.2. Concept of wafer-level package based on a low-loss spacer

substrate

In the previous chapter several approaches, in which 0-level packaging has been used to increase the quality factor of integrated passives, have been presented. The use of a spacer substrates to increase the quality factor while minimizing the area consumption is applied to several of those packaging concepts.

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42

from the lossy silicon ensures that the components will not suffer from silicon substrate losses. Besides, the use of an additional substrate allows for using different metallization schemes than in the core RF BiCMOS technology that is generally used for implementing the active RF circuitry. This thicker metal can be applied to reduce the metal loss in addition to reducing substrate losses, thus arriving at a maximum Q. As an additional advantage of the proposed concept 3D-integration can be achieved, allowing for the integration of novel components such as on-chip antennas, microstrip lines, and Faraday cages. The rigid spacer substrate also contributes to the mechanical support of the WLP, thus allowing to form trenches and partially remove the silicon.

RF CMOS/ BiCMOS Low-loss material EM shield Isolation trenches Integrated passive

Figure 3.1: Schematic view of the proposed wafer-level packaging concept.

3.3. Requirements for the spacer substrate

The requirements for the spacer substrate can be divided into several categories:

• Physical dimensions: substrate thickness (both spacer and silicon). • Electro/thermal parameters of the spacer substrate: dielectric

constant, losses, thermal conductivity, etc.

• Processing issues: compatibility with silicon IC fabrication. In this section we will discuss these issues in detail.

Substrate thickness: the selection of the spacer substrate thickness is

based on the properties of the lossy silicon substrate, as well as on the lateral dimensions of the passive components that are placed onto that spacer substrate. It should be mentioned that the application of the rigid spacer technology is meaningful only if spacers are thicker than 50 µm; thickness below 50 µm may be achived by using other techniques, such as spin-on dielectrics [1].

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separation from the silicon substrate would allow for minimizing the substrate losses. From the lumped-element model (Fig. 3.2) of a spiral inductor it can be seen that an increase of the inductors Q-factor with an increase of the spacers thickness will be mainly dominated by the decrease of the spacers capacitance (Csp).

The spacer’s capacitance (Csp) may be modeled by using a microstrip line approximation (Fig. 3.3), assuming silicon substrate as ground metal (provided that conductivity of silicon >> conductivity of the spacer). In this approximation the spacer capacitance is then defined by total area (= width * length) of inductor’s metal lines. As a rough approximation we assume that for a given inductor the other parameters such as interwire capacitance (Cp) are not changed with a change of the spacer thickness. Thus, for a given inductor, the Csp is defined by two parameters: metal line width and spacers thickness. From the microstrip theory the capacitance per unit length is defined by:

z

c

ε

C

ef sp

=

_⋅

, for d≥w, (3.1)

where c – speed of light, z – characteristic impedance, and εef – effective dielectric constant, defined by:

w d 12 1 1 2 1 2 1 _r r ef + ⋅ − + + =

ε

, (3.2) ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ₊ = 4d w w 8d ln ε 60 z ef . (3.3)

Figure 3.2: Lumped element model of a spiral inductor. Cp

L R

Csp Csp

Rsp Rsp

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44

Figure 3.3: Microstrip line model.

Fig. 3.4 shows the 3D plot of the capacitance per unit length as a function of the width of the metal line and the spacer thickness. It may be seen that for 10-100 µm-wide metal lines, the Csp capacitance does not change significantly if the spacer is thicker than 200 µm .

To validate this conclusion, we have performed modeling of different inductors using FEM models. The ADS Momentum simulator was used to extract the inductor’s quality factor and inductance as a function of spacer thickness. Furthermore, the ‘true 3D’ FEM Ansoft HFSS simulator was also used. Fig. 3.5 shows a typical geometry of a simulated inductors. The model parameters are shown in Table 3.1.

Figure 3.4: Microstrip capacitance as a function of line width and substrate thickness.

W

d substrate

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As can be seen from Fig. 3.6c, for high-ohmic silicon substrates (2 kΩ-cm), the application of the spacer technology is unreasonable, since this substrate already provides high quality factors. For a low-resistivity silicon substrate (5 Ω-cm) in Fig. 3.6a-b, however, a 200 µm-thick spacer is effective in reducing the substrate losses. For a more closely spaced inductor (10-150 µm) the quality factor is severely degraded due to capacitive currents through the silicon substrate.

However, the through-wafer interconnects must be also taken into account when an optimum spacer thickness is defined. Shorter through-wafer interconnects are obviously preferable to minimize their parasitics. This has been analyzed in [2], where optimum substrate thickness was shown to be a trade-off between interconnects length, via-hole dimesnions, and sufficient separation from the silicon substrate. It was shown that vertial interconnects in 200 µm-thick spacer substrate made of 5 µm-thick copper with cross-section up to 50 x 50 µm2_{metallization have only limited influence on the} inductor characterisitics. It should be mentioned that vias below 20 µm in diameter are difficult to fabricate (this is analyzed in detail in Chapter 6). However, achievable quality factor decreases by 25 % and 40 % for vias with cross-section of 100 x 100 µm2_{and 150 x 150 µm}2_{, respectively.} Positioning of the via-hole in respect to spiral center of an inductors may also influence the achiavalble quality factor.

Positioning of the via in the spiral center or close to it, degrades the achievable quality factor due to eddy currents induced into the via metal. This effect is, however, significant only for large vias ( >100x100 µm2_{); in} this case shifting the via away from the centre of the spiral coil can improve the inductor performance (by 50 % for 100 x 100 µm2 via shifted 70 µm away from the spiral centre). Influence of via positioning for via having relatively small cross sections (e.g. 20 x 20 µm2 ) is much less critical when compared to the larger diamter via-holes.

(a) (b)

Figure 3.5: Typical geometry of the simulated inductors: (a) 2 turn inductor geometry for ADS Momentum modelling; (b) HFSS 3D model.

substrate silicon

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46

Table 3.1. Spacer substrate material properties used in the simulation.

Material Properties Glass Loss tangent 0.0009 Permittivity 6.2

Thickness 10-500 µm Silicon Permittivity 11.9 Resistivity 5 or 2,000 Ω-cm

Thickness 200 µm Metal (aluminium) Thickness 2 µm Line width 12 / 24 µm

Conductivity 3.4x107_S/m

Inductors 200x200 µm – 2 turns 200x200 µm – 4 turns 400x400µm – 4 turns 0 5 10 15 20 0 5 10 15 20 25 Q Frequency (GHz) 10µm 20µm 50µm 100µm 150µm 200µm 500µm

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0 5 10 15 20 0 5 10 15 20 25 Q Frequency [GHz] 20µm 50µm 10µm 150µm 200µm 500µm Figure 3.6b: Quality factor of 2-turn 400x400 µm on top of spacer substrate having different spacer’s thickness. Silicon resistivity: 5 Ω-cm.

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48

Silicon Backside metalization

Spacer

Through-substrate trench

Figure 3.7: Schematical view of through-substrate trenched silicon substrate with backside metallization for crosstalk suppression [3].

Crosstalk supression by means of substrate thinning has to be arranged while keeping the mechanical stability of the substrate in mind. A minimization of the silicon substrate thickness is effective as far as substrate loss, crosstalk through the silicon, and power dissipation go [3]. For this design feature to be effective the silicon thickness needs to be far below 50 µm. Obviously, from a manufacturing point of view, such thin substrates will not provide sufficient mechanical self-support. The use of a rigid spacer material will therefore allow to provide mechanical stability besides the required spacing between the lossy silicon and the passive component. Crosstalk isolation can be achieved partially trenching the substrate, by adding a grounded backside metal, or by a combination of these techniques (Fig. 3.7).

Obviously, substrate trenching is only possible when a silicon substrate is permanently attached to a spacer substrate. A sufficient thickness and appropriate mechanical properties of the spacer substrate are therefore required. In general, glass/silicon wafers thicker than 150-250 µm (depending on the wafer diameter) already provide sufficient mechanical self-support.

Finally, the silicon/spacer thickness also depends on the required mechanical properties of the package.

Electrical/thermal parameters: the dielectric constant of the spacer

substrate determines the physical dimensions of the passive devices, such as antennas or transmission lines. Thus, substrates having a high permittivity are preferable. Secondly, wafer-level bonding requires substrates that have a CTE close to that of silicon in order to avoid stresses and excessive wafer warpage. Finally, a high thermal conductivity of spacer substrate is preferable, particularly for high-power applications. The proper selection of substrate materials will be discussed in Chapter 4.

Processability issues: the wafer-level packaging approach assumes that

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adhering to batch IC processes will allow for reduction of the overall processing costs.

The bottleneck in wafer-level packaging is the fabrication of through-wafer interconnects. If silicon material is considered as a spacer material, a variety of existing techniques may be applied. These include plasma etching, laser machining, powder blasting or wet anisotropic silicon etching as techniques to form high-aspect-ratio vias. Similarly, crosstalk isolation barriers can be formed by trenching the silicon substrate. Moreover, metallization of high-aspect ratio vias is not trivial.

Comparison and limitations of these techniques will be discussed in Chapter 6. For glass substrates the technology options are rather limited. As the glass substrates are hardly etched in plasma, only wet etching, powder blasting, or laser machining techniques may be considered.

3.4. Implementation issues and possible process flow

The proposed packaging concept may be accomplished in several ways. The first option (Fig. 3.8) assumes that silicon (i.e. the fully processed silicon IC wafer) and the spacer substrate are processed in parallel, so that, after bonding them together, only through wafer electrical interconnects are to be formed. In this case structuring of silicon and/or spacer substrate is performed with both partial substrates separated, which means that they are mechanically weak prior to the bonding. Detailed analyses of substrate structuring will be performed in Chapter 5 to provide the required insight in the mechanical stability of micromachined substrates. Besides, this also limits the freedom of chosing the interconnects via and isolation trench geometries. Moreover, aligned bonding is necessary to realize the packaging concept, which requires more sophisticated bonding equipment.

Wafer-level packaging technology for RF applications based on a rigid low-loss spacer substrate

Wafer-Level Packaging Technology for RF

Applications Based on a Rigid Low-Loss Spacer

Wafer-Level Packaging Technology

for RF Applications

Based on a Rigid Low-Loss Spacer Substrate

PROEFSCHRIFT

Table of contents

Chapter 1. Introduction

1.1. Emergence of wireless communications

1.2. Silicon RF ICs and wireless revolution

1.3. Role of passive components in RF ICs

1.4. Wafer-level packaging for RF applications

1.5. Wafer-level packaging technology based on a rigid low-loss

spacer substrate

1.6. Organization of the thesis

References

Chapter 2. RF packaging and

integration of passive devices

2.1. Introduction

2.2. Packaging roadmap

die

wire

die attach

Cu leadframe exposed pad

2.3. Properties of an RF package

2.4. Passive components in RF front-end systems

cycle

n

oscillatio

one

in

loss

energy

stored

energy

Q

=

2

π

πσµω

δ

=

σ

= −

σ

∇

ϕ

J

E

ϕ

0

∇

=

i

ωσ

∇×

J

=

B

Q

Silicon resistivity

(O -cm)

L

Q

Q

Silicon resistivity

(O -cm)

L

Q

ω

Q

2.5. Wafer-level packaging opportunities

References

Chapter 3. RF WLP technology

based on a rigid low-loss spacer

substrates

3.1. Introduction

3.2. Concept of wafer-level package based on a low-loss spacer

substrate

_{die attach}

_ϕ

₀

_⋅