ADS58H40

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1

FEATURES DESCRIPTION

The ADS58H40 is a high-linearity, quad-channel, 14-

2• Quad Channel

bit, 250-MSPS analog-to-digital converter (ADC). The

• Three Different Operating Modes: four ADC channels are separated into two blocks with – 11-Bit: 250 MSPS two ADCs each. Each block can be individually configured into three different operating modes. One – 11-Bit SNRBoost^3G+: 250 MSPS

operating mode includes the implementation of the – 14-Bit: 250 MSPS (Burst Mode)

SNRBoost^3G+signal processing technology to provide

• Maximum Sampling Data Rate: 250 MSPS high signal-to-noise ratio (SNR) in a band up to 90 MHz wide with only 11-bit resolution. Designed for

• Power Dissipation:

low power consumption and high spurious-free – 11-Bit Mode: 365 mW per Channel

dynamic range (SFDR), the ADC has low-noise

• SNRBoost^3G+Bandwidth: 2x 45 MHz or 90 MHz performance and outstanding SFDR over a large input frequency range.

• Spectral Performance at 170 MHz IF (typ):

– SNR: 70.5 dBFS in 90-MHz Band with SNRBoost^3G+

– SFDR: 85 dBc

• DDR LVDS Digital Output Interface

• 144-Pad BGA (10-mm × 10-mm)

APPLICATIONS

• Multi-Carrier GSM Cellular Infrastructure Base Stations

• Multi-Carrier Multi-Mode Cellular Infrastructure Base Stations

• Active Antenna Arrays for Wireless Infrastructures

• Communications Test Equipment

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susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE AND ORDERING INFORMATION⁽¹⁾

SPECIFIED LEAD AND

PACKAGE PACKAGE ORDERING

PACKAGE- TEMPERATURE BALL TRANSPORT

PRODUCT ECO PLAN⁽²⁾

LEAD DESIGNATOR MARKING NUMBER MEDIA

RANGE FINISH

ADS58H40IZCR Tray

GREEN (RoHS,

ADS58H40 BGA-144 ZCR –40°C to +85°C CuNiPdAu ADS58H40I

no SB or BR) ADS58H40IZCRR Tape and Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder atwww.ti.com.

(2) These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content can be accessed atwww.ti.com/leadfree.

GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight.

N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go towww.ti.com/leadfree.

Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

VALUE UNIT

AVDD33 –0.3 to +3.6 V

Supply voltage range AVDD –0.3 to +2.1 V

DRVDD –0.3 to +2.1 V

AVSS and DRVSS –0.3 to +0.3 V

AVDD and DRVDD –2.4 to +2.4 V

Voltage between

AVDD33 and DRVDD –2.4 to +3.9 V

AVDD33 and AVDD –2.4 to +3.9 V

XINP, XINM –0.3 to minimum (1.9, AVDD + 0.3) V

Voltage applied to input pins CLKP, CLKM⁽²⁾ –0.3 to minimum (1.9, AVDD + 0.3) V

RESET, SCLK, SDATA, SEN, SNRB, TRIG_EN, PDN –0.3 to +3.9 V

Operating free-air, TA –40 to +85 °C

Temperature Operating junction, T_J +150 °C

Storage, Tstg –65 to +150 °C

Electrostatic discharge (ESD)

Human body model (HBM) 2 kV

ratings

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKM is less than

| 0.3 V |). This recommendation prevents the ESD protection diodes at the clock input pins from turning on.

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144 PINS

θ_JA Junction-to-ambient thermal resistance 35.9

θJCtop Junction-to-case (top) thermal resistance 5.1

θJB Junction-to-board thermal resistance 12.6

ψ_JT Junction-to-top characterization parameter 0.1 °C/W

ψ_JB Junction-to-board characterization parameter 12.4

θ_JCbot Junction-to-case (bottom) thermal resistance N/A

SPACER

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

SUPPLIES

AVDD33 3.15 3.3 3.45 V

AVDD Supply voltage 1.8 1.9 2.0 V

DRVDD 1.7 1.8 2.0 V

ANALOG INPUTS

Differential input voltage range 2 VPP

Input common-mode voltage V_CM± 0.025 V

Analog input common-mode current (per input pin of each channel) 1.5 µA/MSPS

VCM current capability 5 mA

2-VPPinput amplitude⁽¹⁾ 400 MHz

Maximum analog input frequency

1.4-VPPinput amplitude 500 MHz

CLOCK INPUTS

Input clock sample rate 184⁽²⁾ 250 MSPS

Sine wave, ac-coupled 0.2 1.5 V_PP

LVPECL, ac-coupled 1.6 VPP

Input clock amplitude differential

(V_CLKP– V_CLKM) LVDS, ac-coupled 0.7 VPP

LVCMOS, single-ended, ac-coupled 1.8 V_PP

Input clock duty cycle 40% 50% 60%

DIGITAL OUTPUTS

Maximum external load capacitance from each output pin to DRVSS

CLOAD (default strength) 3.3 pF

R_LOAD Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω TEMPERATURE RANGE

TA Operating free-air temperature –40 +85 °C

Recommended +105 °C

T_J Operating junction temperature

Maximum rated⁽³⁾ +125 °C

(1) See theTheory of Operationsection.

(2) The minimum functional clock speed can be 10 MSPS after writing the following special modes: address 4Ah, value 01h; address 62h,

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(Hex) DATA (Hex) ZONE = 2 ZONE = 2 ZONE = 3 ZONE = 3 ZONE = 2 ZONE = 2

D4 80 √

D5 80 √

D6 80 √ √ √ √ √

D7 0C √ √ √ √ √

DB 30 √

F0 38 √ √

F1 20 √ √ √

F5 42 √

(1) R_Srefers to the source impedance. Zone refers to the Nyquist zone in which the signal band lies. Zone = 2 corresponds to the signal band that lies between fS/ 2 and fS. Zone = 3 corresponds to the signal band that lies between fSand 3 × fS/ 2.

(2) Best performance can be achieved by writing these modes depending upon source impedance, band of operation, and sampling speed.

ELECTRICAL CHARACTERISTICS

Typical values are at T_A= +25°C, full temperature range is T_MIN= –40°C to T_MAX= +85°C, ADC clock frequency = 250 MHz, 50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RESOLUTION

Default resolution 11 Bits

ANALOG INPUTS

Differential input full-scale 2 V_PP

VCM Common mode input voltage 1.15 V

RIN Input resistance, differential At 170-MHz input frequency 700 Ω

C_IN Input capacitance, differential At 170-MHz input frequency 3.3 pF

With a 50-Ωsource driving the ADC

Analog input bandwidth, 3 dB 500 MHz

analog inputs DYNAMIC ACCURACY

EO Offset error Specified across devices and channels –15 15 mV

As a result of internal

reference inaccuracy Specified across devices and channels –5 5 %FS

EG Gain error⁽¹⁾ alone

Of channel alone Specified across channels within a device ±0.2 %FS

Channel gain error temperature coefficient⁽¹⁾ 0.001 Δ%/°C

POWER SUPPLY⁽²⁾

IAVDD33 3.3-V analog supply 51 mA

IAVDD 1.9-V analog supply 350 mA

11-bit operation 340 mA

Supply current

I_DRVDD 1.8-V digital supply SNRBoost^3G+enabled (90 MHz) 400 mA

14-bit burst mode 355 mA

11-bit operation 1.45 1.6 W

PTOTAL Total SNRBoost^3G+enabled 1.55 1.8 W

Power dissipation 14-bit burst mode 1.47 W

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noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DYNAMIC AC CHARACTERISTICS^{(3) (4)}

fIN= 140 MHz, AIN= –1 dBFS 71 dBFS

11-bit SNRBoost^3G+, fIN= 170 MHz, AIN= –1 dBFS 69 70.5 dBFS

90-MHz BW

SNR Signal-to-noise ratio f_IN= 220 MHz, A_IN= –1 dBFS 70 dBFS

fIN= 307 MHz, AIN= –3 dBFS 71.7 dBFS

11-bit SNRBoost^3G+,

60-MHz BW fIN= 350 MHz, AIN= –3 dBFS 71.5 dBFS

f_IN= 140 MHz, A_IN= –1 dBFS 70.6 dBFS

fIN= 170 MHz, AIN= –1 dBFS 68 70.1 dBFS

90-MHz BW Signal-to-noise and

SINAD fIN= 220 MHz, AIN= –1 dBFS 69.5 dBFS

distortion ratio

fIN= 307 MHz, AIN= –3 dBFS 69.7 dBFS

60-MHz BW f_IN= 350 MHz, A_IN= –3 dBFS 69.2 dBFS

fIN= 140 MHz, AIN= –1 dBFS 85 dBc

fIN= 170 MHz, AIN= –1 dBFS 80 85 dBc

SFDR Spurious-free dynamic range f_IN= 220 MHz, A_IN= –1 dBFS 82 dBc

f_IN= 140 MHz, A_IN= –1 dBFS 82 dBc

THD Total harmonic distortion fIN= 220 MHz, AIN= –1 dBFS 80 dBc

HD2 Second-order harmonic distortion⁽⁵⁾ f_IN= 220 MHz, A_IN= –1 dBFS 82 dBc

HD3 Third-order harmonic distortion fIN= 220 MHz, AIN= –1 dBFS 85 dBc

Worst spur

(non HD2, HD3)

DNL Differential nonlinearity –0.95 ±0.5 1.6 LSBs

INL Integral nonlinearity ±1.5 ±5.25 LSBs

Recovery to within 1% (of final value) for Clock

Input overload recovery 1

6-dB output overload with sine-wave input cycle

With a full-scale, 220-MHz signal on

Crosstalk aggressor channel and no signal on victim 90 dB

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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS⁽¹⁾(RESET, SCLK, SDATA, SEN, PDN, SNRB, TRIG_EN)

All digital inputs support 1.8-V logic

V_IH High-level input voltage 1.25

levels. SPI supports 3.3-V logic levels.

V All digital inputs support 1.8-V logic

VIL Low-level input voltage 0.45

levels. SPI supports 3.3-V logic levels.

RESET, SCLK, PDN,

VHIGH= 1.8 V 10 µA

High-level input SNRB, TRIG_EN pins IIH current

SEN⁽²⁾pin VHIGH= 1.8 V 0 µA

RESET, SCLK, PDN,

V_LOW= 0 V 0 µA

Low-level input SNRB, TRIG_EN pins IIL current

SEN pin VLOW= 0 V 10 µA

DIGITAL OUTPUTS (SDOUT, HIRES, TRIG_RDY)

DRVDD –

V_OH High-level output voltage DRVDD V

0.1

VOL Low-level output voltage 0 0.1 V

DIGITAL OUTPUTS, LVDS INTERFACE

(DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM)

V_ODH Output differential High⁽³⁾ Standard-swing LVDS 270 350 465 mV

voltage

VODL Low Standard-swing LVDS –465 –350 –270 mV

VOCM Output common-mode voltage 1.05 V

(1) RESET, SDATA, SCLK, TRIG_EN, and SNRB have an internal 150-kΩpull-down resistor.

(2) SEN has an internal 150-kΩpull-up resistor to DRVDD.

(3) With an external 100-Ωtermination.

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Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t_A Aperture delay 0.7 1.2 1.6 ns

Aperture delay matching Between any two channels of the same device ±70 ps

Between two devices at the same temperature and

Variation of aperture delay ±150 ps

DRVDD supply

t_J Aperture jitter 140 fs rms

Time to valid data after coming out of global power

100 µs

Wake up time down

Time to valid data after coming out of channel power

10 µs

down

Output clock

Default latency in 11-bit mode 10

cycles Output clock

Digital gain enabled 13

cycles Output clock

Digital gain and offset correction enabled 14

cycles Output clock SNRBoost^3G+(90-MHz BW) enabled alone 13

ADC latency^{(4) (5)} cycles

Output clock SNRBoost^3G+(90-MHz BW), digital gain, and offset 17

cycles correction enabled

Output clock

SNRBoost^3G+(45-MHz BW) enabled alone 15 cycles

Output clock SNRBoost^3G+(45-MHz BW), digital gain, and offset 19

cycles correction enabled

OUTPUT TIMING⁽⁶⁾

tSU Data setup time(7) (8) (9) Data valid to CLKOUTxxP zero-crossing 0.6 0.85 ns

tH Data hold time(7) (8) (9) CLKOUTxxP zero-crossing to data becoming invalid 0.6 0.84 ns Differential clock duty cycle (CLKOUTxxP –

LVDS bit clock duty cycle 50%

CLKOUTxxM)

Input clock falling edge cross-over to output clock

tPDI Clock propagation delay⁽⁵⁾ falling edge cross-over, 184 MSPS≤sampling 0.25 × tS+ tdelay ns frequency≤250 MSPS

Input clock falling edge cross-over to output clock

tdelay Delay time falling edge cross-over, 184 MSPS≤sampling 6.9 8.65 10.5 ns

frequency≤250 MSPS tRISE,

Data rise and fall time Rise time measured from –100 mV to +100 mV 0.1 ns

tFALL

t_CLKRISE, Output clock rise and fall

Rise time measured from –100 mV to +100 mV 0.1 ns

t_CLKFALL time

(1) Timing parameters are ensured by design and characterization and are not tested in production.

(2) CLOADis the effective external single-ended load capacitance between each output pin and ground.

(3) R_LOADis the differential load resistance between the LVDS output pair.

(4) ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.

(5) Overall latency = ADC latency + t_PDI.

(6) Measurements are done with a transmission line of 100-Ωcharacteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(7) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(8) Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address ACh, value 60h. Refer to theSerial Interface Registerssection. By default after reset, minimum setup time and minimum hold times are 520 ps each.

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Ch B (Ch D) Input

Clock

CLKOUTABM (CLKOUTCDM) CLKOUTABP (CLKOUTCDP)

Output Data DABP, DABM (DCDP, DCDM) DDR

LVDS Input Signal

Sample N

N+1 N+2 N+3 N+4

tA

CLKINM

CLKINP

N+10

N+11 N+12

tPDI

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

Ch B (Ch D)

Ch A (Ch C)

DxnP

DxnM

GND

Logic 0 V_ODL

Logic 1 V_ODH

V_OCM

Figure 1shows a timing diagram of the LVDS output voltage levels.Figure 2shows the latency described in the Timing Requirementstable.

Figure 1. LVDS Output Voltage Levels

Figure 2. Latency Timing

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CLKOUTABP CLKOUTABM

DAB[13:0]P, DAB[13:0]M

DCD[13:0]P, DCD[13:0]M CLKOUTCDP CLKOUTCDM

Sample N Sample N + 1 Sample N + 2

DA[13:0]P, DA[13:0]M

DB[13:0]P, DB[13:0]M

DA[13:0]P, DA[13:0]M

DB[13:0]P, DB[13:0]M

DA[13:0]P, DA[13:0]M

DB[13:0]P, DB[13:0]M

DC[13:0]P, DC[13:0]M

DD[13:0]P, DD[13:0]M

DC[13:0]P, DC[13:0]M

DD[13:0]P, DD[13:0]M

DC[13:0]P, DC[13:0]M

DD[13:0]P, DD[13:0]M

output clock while channels B and D are output on the falling edge of the output clock.

Figure 3. LVDS Output Interface Timing

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A

B

C

D

E

F

G

H

J

1 2 3 4 5 6 7 8 9 10 11 12

K

L

M

CINP

AVDD AVDD CINM AVDD VCM VCM AVDD BINM AVDD AVDD

DINP AVSS AVDD AVDD AVSS AVDD33 AVDD33 AVSS AVDD AVDD AVSS AINM

DINM AVSS AVSS AVSS CLKINM CLKINP AVSS AVSS AVSS AVSS AINP

AVDD AVDD VCM AVSS AVSS AVSS AVSS AVSS AVSS VCM AVDD AVDD

AVDD33 AVDD33 SNRB DRVSS AVDD33 AVDD33

DCD13M DCD13P DRVDD DRVSS DAB13P DAB13M

DCD12M DCD12P TRIG_EN TRIG_RDY DAB12P

DCD11M DCD11P DCD6P DCD6M DAB11P DAB11M

DCD8M DCD8P DCD3P DCD3M DCD1P DCD1M DAB1M DAB1P DAB3M DAB3P DAB8P DAB8M

DCD7M DCD7P CLKOUT CDP

CLKOUT CDM

DCD0P/

OVRCDP

DCD0M/

OVRCDM

DAB0M/

OVRABM

DAB0P/

OVRABP

CLKOUT ABM

CLKOUT

ABP DAB7P DAB7M

DRVSS DRVSS

SDATA

DRVDD

DAB2M

DAB2P DAB4M DAB4P DAB5P DAB6P SDOUT DRVDD PDN DRVSS

DRVSS

DRVDD DRVDD DRVDD SCLK DRVSS DRVSS

DRVDD DRVDD DRVDD RESET DRVSS DRVSS

DCD2M DCD2P DRVDD HIRES DRVSS DRVSS AVSS

DAB12M

DAB5M DAB6M SEN

BINP BGA-144

(TOP VIEW)

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AINM B12 I Negative differential analog input for channel A AINP C12 I Positive differential analog input for channel A AVDD33 B6, B7, E1, E2, E11, E12 I Analog 3.3-V power supply

A1, A2, A5, A8, A11, A12,

AVDD B3, B4, B9, B10, D1, D2, I Analog 1.9-V power supply D11, D12

B2, B5, B8, B11, C2-C5,

AVSS I Analog ground

C8-C11, D4-D9

BINM A9 I Negative differential analog input for channel B

BINP A10 I Positive differential analog input for channel B

CINM A3 I Negative differential analog input for channel C

CINP A4 I Positive differential analog input for channel C

CLKINM C6 I Negative differential clock input

CLKINP C7 I Positive differential clock input

CLKOUTABM M9 O Negative differential LVDS clock output for channel A and B CLKOUTABP M10 O Positive differential LVDS clock output for channel A and B CLKOUTCDM M4 O Negative differential LVDS clock output for channels C and D CLKOUTCDP M3 O Positive differential LVDS clock output for channels C and D

DAB[13:1]P, DDR LVDS outputs for channels A and B.

F11, F12, G11, G12,

DAB0P/OVRABP, In 11-bit mode, DAB13 is the MSB, DAB3 is the LSB, and DAB0 is the over-range (OVR) bit.

H9-H12, J8-J12, K8-K12, O

DAB[13:1]M, In 14-bit burst mode, DAB13 is the MSB and DAB0 is the LSB. There is no OVR bit in this L7-L12, M7, M8, M11, M12

DAB0M/OVRABM mode.

DCD[13:1]P, DDR LVDS outputs for channels C and D.

F1, F2, G1, G2, H1-H4,

DCD0P/OVRCDP, In 11-bit mode, DCD13 is the MSB, DCD3 is the LSB, and DCD0 is the OVR bit.

J1-J5, K1-K5, L1-L6, M1, O

DCD[13:1]M, In 14-bit burst mode, DCD13 is the MSB and DCD0 is the LSB. There is no OVR bit in this M2, M5, M6

DCD0M/OVRCDM mode.

DINM C1 I Negative differential analog input for channel D

DINP B1 I Positive differential analog input for channel D F3, F10, H5-H8, J6, J7, K6,

DRVDD I Digital 1.8-V power supply

K7

DRVSS E4-E9, F4-F9 I Digital ground

HIRES G5 O Indication in burst mode if output data is high or low resolution PDN E10 I Power-down control; active high. Logic high is power down.

RESET G6 I Hardware reset; active high

SCLK G7 I Serial interface clock input

SDATA G8 I Serial interface data input

SDOUT G10 O Serial interface data output

SEN G9 I Serial interface enable

SNRB E3 I SNRB enable; active high

TRIG_EN G3 I Trigger burst mode; active high

TRIG_RDY G4 O Indication if ADC is ready for another high-resolution burst mode

VCM A6, A7, D3, D10 O Common-mode voltage for analog inputs. All VCM pins are internally connected together.

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DAB0P, DAB0M or OVRABP, OVRABM

CLKINP, CLKINM

AINP, AINM

SCLK

SEN SDATA SDOUT

RESET

Common VCM Mode

CLKOUTABP, CLKOUTABM DAB[13:1]P, DAB[13:1]M 13

BINP, BINM

CINP, CINM

DINP, DINM

SNR Boost

Burst Mode 11-Bit 11-Bit

14-Bit Digital Processing Block

PDN

HRES

TRIG_EN

SNRB

Configuration Registers

TRIG_RDY

CLKOUTCDP, CLKOUTCDM DCD[13:1]P, DCD[13:1]M 13

SNR Boost

Burst Mode 11-Bit 11-Bit

14-Bit Digital Processing Block

Digital

Block DCD0P, DCD0M or

OVRCDP, OVRCDM Output

Formatter DDR LVDS Digital

Block 14-Bit

ADC

14-Bit ADC

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−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

SFDR = 87.6 dBc SNR = 69.5 dBFS SINAD = 69.4 dBFS THD = 85.5 dBc

G003

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

SFDR = 85.8 dBc SNR = 69.1 dBFS SINAD = 69 dBFS THD = 83.9 dBc

G005

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

SFDR = 88.1 dBc SNR = 70.1 dBFS SINAD = 70 dBFS THD = 85 dBc

G001

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

G002

output interface, and 32k-point FFT, unless otherwise noted.

FFT IN 14-BIT MODE INPUT FREQUENCY FFT IN 14-BIT MODE INPUT FREQUENCY

(140 MHz) (170 MHz)

Figure 4. Figure 5.

FFT IN 14-BIT MODE INPUT FREQUENCY FFT IN 14-BIT MODE INPUT FREQUENCY

(185 MHz) (190 MHz)

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−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

BW = 90 MHz

(17.5 MHz to 107.5 MHz) AIN = −1 dBFS SFDR = 86.5 dBc SNR = 70.3 dBFS SINAD = 70.2 dBFS

G007

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

BW = 90 MHz

(17.5 MHz to 107.5 MHz) AIN = −1 dBFS SFDR = 84.7 dBc SNR = 70.1 dBFS SINAD = 70 dBFS

G008

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

G005

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

BW = 90 MHz

(17.5 MHz to 107.5 MHz) AIN = −1 dBFS SFDR = 86.7 dBc SNR = 70.4 dBFS SINAD = 70.3 dBFS

G006

FFT IN 14-BIT MODE INPUT FREQUENCY FFT IN 11-BIT MODE WITH SNRBoost^3G+

(230 MHz) INPUT FREQUENCY (150 MHz, 90-MHz Bandwidth)

FFT IN 11-BIT MODE WITH SNRBoost^3G+ FFT IN 11-BIT MODE WITH SNRBoost^3G+

INPUT FREQUENCY (185 MHz, 90-MHz Bandwidth) INPUT FREQUENCY (230 MHz, 90-MHz Bandwidth)

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75 80 85 90 95 100

140 155 170 185 200 215 230

Input Frequency (MHz)

SFDR (dBc)

G011

68 68.5 69 69.5 70 70.5 71

140 155 170 185 200 215 230

SNR (dBFS)

G012

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

Each Tone at

−7 dBFS Amplitude fIN1 = 185.1 MHz fIN2 = 190.1 MHz 2−Tone IMD = 97 dBFS SFDR = 102.2 dBFS

G009

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

Each Tone at

−36 dBFS Amplitude fIN1 = 185.1 MHz fIN2 = 190.1 MHz 2−Tone IMD = 101 dBFS SFDR = 100.9 dBFS

G010

FFT FOR –7-dBFS, TWO-TONE INPUT SIGNAL FFT FOR –36-dBFS, TWO-TONE INPUT SIGNAL

IN 14-BIT MODE IN 14-BIT MODE

SPURIOUS-FREE DYNAMIC RANGE vs SIGNAL-TO-NOISE RATIO vs

INPUT FREQUENCY INPUT FREQUENCY

(16)

82 84 86 88 90 92 94 96

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB)

SFDR (dBc)

140 MHz 170 MHz 185 MHz 190 MHz 230 MHz

G015

63 64 65 66 67 68 69 70 71 72

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB)

SINAD (dBFS)

G016

70 72 74 76 78 80 82 84 86

270 290 310 330 350

SFDR (dBc)

G013

68 68.5 69 69.5 70 70.5 71

270 290 310 330 350

SNR (dBFS)

G014

SPURIOUS-FREE DYNAMIC RANGE vs SIGNAL-TO-NOISE RATIO vs

HIGH INPUT FREQUENCY (–3 dBFS) HIGH INPUT FREQUENCY (–3 dBFS)

SPURIOUS-FREE DYNAMIC RANGE vs SIGNAL-TO-NOISE RATIO AND DISTORTION vs

GAIN ACROSS INPUT FREQUENCY GAIN ACROSS INPUT FREQUENCY

(17)

82 83 84 85 86 87 88 89 90

−40 −15 10 35 60 85

Temperature (°C)

SFDR (dBc)

AVDD = 1.8 V AVDD = 1.9 V AVDD = 2 V

Input Frequency = 185 MHz

G020

0.7 0.8 0.9 1 1.1 1.2 1.3

78 80 82 84 86 88 90 92 94

68 68.5 69 69.5 70 70.5 71 71.5 72

Input Common−Mode Voltage (V)

SFDR (dBc) SNR (dBFS)

SFDR SNR Input Frequency = 185 MHz

G019

62 63 64 65 66 67 68 69 70 71 72

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB)

SNR (dBFS)

G017

−50 −40 −30 −20 −10 0

20 30 40 50 60 70 80 90 100 110 120

69 69.5 70 70.5 71 71.5 72 72.5 73 73.5 74

Amplitude (dBFS)

SFDR (dBc,dBFS) SNR (dBFS)

SFDR (dBc) SFDR (dBFS) SNR Input Frequency = 185 MHz

G018

SIGNAL-TO-NOISE RATIO vs

GAIN ACROSS INPUT FREQUENCY PERFORMANCE vs INPUT AMPLITUDE

PERFORMANCE vs SPURIOUS-FREE DYNAMIC RANGE vs

INPUT COMMON-MODE VOLTAGE TEMPERATURE (AVDD Supply)

(18)

68 68.5 69 69.5 70 70.5 71

−40 −15 10 35 60 85

Temperature (°C)

SNR (dBFS)

DRVDD = 1.7 V DRVDD = 1.8 V DRVDD = 1.9 V DRVDD = 2 V

G023

82 83 84 85 86 87 88 89 90

−40 −15 10 35 60 85

Temperature (°C)

SFDR (dBc)

AVDD3V = 3.15 V AVDD3V = 3.3 V AVDD3V = 3.45 V

G024

68 68.5 69 69.5 70 70.5 71

−40 −15 10 35 60 85

Temperature (°C)

SNR (dBFS)

AVDD = 1.8 V AVDD = 1.9 V AVDD = 2 V

G021

83 84 85 86 87 88 89 90

−40 −15 10 35 60 85

Temperature (°C)

SFDR (dBc)

DRVDD = 1.7 V DRVDD = 1.8 V DRVDD = 1.9 V DRVDD = 2 V

G022

SIGNAL-TO-NOISE RATIO vs SPURIOUS-FREE DYNAMIC RANGE vs

TEMPERATURE (AVDD Supply) TEMPERATURE (DRVDD Supply)

SIGNAL-TO-NOISE RATIO vs SPURIOUS-FREE DYNAMIC RANGE vs

TEMPERATURE (DRVDD Supply) TEMPERATURE (AVDD3V Supply)

(19)

0 256 512 768 1024 1280 1536 1792 2048

0 4096 8192 12288 16384 20480 24576 28672 32768 Sample Number

Output Code (LSB)

FS = 250 MSPS FIN = 185 MHz

G028

25 30 35 40 45 50 55 60 65 70 75

82 83 84 85 86 87 88 89 90 91 92

67 67.5 68 68.5 69 69.5 70 70.5 71 71.5 72

Input Clock Duty Cycle (%)

THD (dBc) SNR (dBFS)

SNR THD Input Frequency = 185 MHz

G027

68 68.5 69 69.5 70 70.5 71

−40 −15 10 35 60 85

Temperature (°C)

SNR (dBFS)

AVDD3V = 3.15 V AVDD3V = 3.3 V AVDD3V = 3.45 V

G025

0.2 0.5 0.8 1.1 1.4 1.7 2 2.3 2.6 2.9 76

78 80 82 84 86 88 90 92 94 96 98 100

65 65.5 66 66.5 67 67.5 68 68.5 69 69.5 70 70.5 71

Differential Clock Amplitudes (Vpp)

SFDR (dBc) SNR (dBFS)

SFDR SNR Input Frequency = 185 MHz

G026

SIGNAL-TO-NOISE RATIO vs PERFORMANCE vs

TEMPERATURE (AVDD3V Supply) DIFFERENTIAL CLOCK AMPLITUDE

PERFORMANCE vs TIME DOMAIN DATA WITH

INPUT CLOCK DUTY CYCLE SNRBoost^3G+ENABLED

(20)

−70

−65

−60

−55

−50

−45

−40

−35

−30

−25

−20

0 50 100 150 200 250 300

Frequency of Signal on Supply (MHz)

PSRR (dB)

PSRR on AVDD Supply PSRR on AVDD3V Supply

50−mVPP Signal Superimposed on Supply

G032

−120

−100

−80

−60

−40

−20 0

0 25 50 75 100 125

Frequency (MHz)

Amplitude (dB)

G031

f = 185 MHz f = 10 MHz, 50 mV SFDR = 76.2 dBc Amplitude:

f = 1 dBFS f = 95.1 dBFS f + f = 77.2 dBFS f f = 80.9 dBFS

IN

PP

CM CM

IN CM IN CM IN

- -

f_IN= 185 MHz

f_IN-f_CM= 175 MHz f_IN+ f_CM= 195 MHz

f_CM= 10 MHz 0

256 512 768 1024 1280 1536 1792 2048

0 4096 8192 12288 16384 20480 24576 28672 32768 Sample Number

Output Code (LSB)

FS = 250 MSPS FIN = 185 MHz

G029

−60

−55

−50

−45

−40

−35

−30

−25

−20

−15

−10

−5 0

0 50 100 150 200 250 300

Frequency of Input Common−Mode Signal (MHz)

CMRR (dB)

50−mVPP Signal Superimposed on VCM

G030

TIME DOMAIN DATA WITH

SNRBoost^3G+DISABLED (Default is 11-Bit Mode) COMMON-MODE REJECTION RATIO vs FREQUENCY

COMMON-MODE REJECTION RATIO SPECTRUM POWER-SUPPLY REJECTION RATIO vs FREQUENCY

(21)

0 100 200 300 400 500 600 700

0 25 50 75 100 125 150 175 200 225 250 Sampling Speed (MSPS)

Analog Power (mW)

AVDD Power AVDD3V Power

G035

100 200 300 400 500 600 700 800

DRVDD Power (mW)

Default 11−bit 14−bit Burst Mode 11−bit with SNRBoost

G036

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Total Power (W)

Default 11−bit 14−bit Burst Mode 11−bit with SNRBoost

G034

−120

−100

−80

−60

−40

−20 0

Frequency (MHz)

Amplitude (dB)

G033

0 5 10 15 20 25 30 35 40 45 50

f_IN-f_PSRR

f_IN+ f_PSRR f_PSRR

f_IN f = 10 MHz

f = 2 MHz, 50 mV Amplitude (f ) = 1 dBFS Amplitude (f ) = 87.4 dBFS Amplitude (f + f ) = 60.6 dBFS Amplitude (f f ) = 60 dBFS

IN PP PSRR

IN PSRR IN PSRR IN PSRR

- - -

- -

ZOOMED VIEW OF POWER-SUPPLY REJECTION RATIO

SPECTRUM TOTAL POWER vs SAMPLING RATE

DRVDD POWER vs SAMPLING RATE IN

ANALOG POWER vs SAMPLING RATE VARIOUS DIGITAL MODES