Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

ROBUST WAFER-LEVEL

THIN-FILM

ENCAPSULATION OF

MICROSTRUCTURES USING LOW STRESS PECVD SILICON

CARBIDE

V

Rajaraman

I,

L.S.

Pakula',

H.TM

Pham2,

P.M

Sarro2and

P.J.

French'

IElectronic

Instrumentation

Laboratory,

2ECTM

Laboratory, DIMES,

Dept.

of

Microelectronics,

Faculty of EEMCS, Delft University of Technology, The Netherlands

ABSTRACT

This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface- and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are itsversatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries aslargeas955x827.m2has been achieved.

INTRODUCTION

Using a meticulously developed IC-compatible microfabrication technology, MEMS can in principle be monolithically integrated with CMOS control/detection circuitry. However, akey distinguisher between theMEMS and IC is that the former contains free-standing and/or movingcomponentswithgapsand feature sizesintherange of a few microns that requires protection against dust, contamination andhandling during backend processing such as dicing and assembly. Besides, someMEMS devices like pressure sensors, resonators, gyroscopes, infrared sensors, etc. also require a stable and controlled environment, like vacuum for instance, for reliable operation. These challenging demands are usually fulfilled by means of packaging MEMS devices on the wafer-level using either wafer bonding [1,2] or thin-film chip-scale encapsulation [1-6], also knownaszero-levelpackaging.

Typical requirements for wafer-level MEMS packaging are low cost processing, CMOS compatibility (in terms of materials employed, process development and device compatibility), hermeticity, robustness, stability, good sealing characteristics and an ability to withstand harsh environments. Although widespread, zero-level packaging

usingwaferbonding technologies suffers from limitations in terms of size, cost and complexity. Hence, thin-film encapsulation technique offers an interesting alternative for zero-levelpackaging ofMEMS.

A generic representation of thin-film packaged MEMS is illustrated inFig. 1. Thistechnique involves the deposition and patterning of a sacrificial material, over the microstructure, above which the encapsulation material is applied. Later, the sacrificial material is etchedthrough the

encapsulation via etch-windowsto form a microcavity that is then sealed with a second material, the sealing layer, which caneither be adifferent material orthe same as the one used forencapsulation. Somekey advantages of wafer level chip-scale packaging of MEMS by thin-film encapsulation are a smaller footprint, reduced chip thickness, reduced process complexity and lower costs. Thin-film packaging technique specifically is more appropriate for surface micromachined and thin-SOI micromachined devices due to thepossibility of producing ultra compact MEMS devices, both integrated and standalone.

Cavity

Si MEMS Encapsulation Sealing

Figure 1: Schematic representation of a thin-film encapsulatedMEMSdevice

Several thin-film encapsulation techniques, using different materials andprocesses, arereported inthe literature [1-6], each having their distinctive pros and cons. However, a majority of the reported techniques have shortcomings like being costly and exclusive, requiring high temperature processing, employing less reliable materials, involving process complexity, etc. Inthis work, we have developed twothin-filmencapsulation processes, for small- and large-areaMEMS,respectively, using astress-optimisedPECVD SiC for encapsulation and sealing that is compatible with post-CMOS processing. Moreover, the use ofPECVD SiC for packaging brings in benefits such as mechanical robustness, chemical inertness and an ability to operate at hightemperatures,making it suitable for harsh environment applications [7-9].

GENERAL CONSIDERATIONS

There are several issues to consider in the design and development of a wafer-level thin-film encapsulation process, someof whicharediscussed below.

Choice of theEncapsulationMaterial

The material being used for encapsulation should be mechanically robust with a minimal residual stress, crack-resistant and pin-hole-free for achieving hermitic sealing. Also the material shouldpreferably exhibit low tensilestress such that the encapsulation does not deform and is held intact whensuspended. Thisaspecthas been takencare ofin our encapsulation process by choosing a pin-hole-free

PECVDSiC, which isamechanically robust material witha high Young's modulus (460GPa), and by optimising its

residual tensile stress level to 65MPa [9]. Deflection oftheEncapsulationLayer

The maximum deflection caused due to the pressure difference between the sealed cavity and the ambience acting acrossthe encapsulation layer hastobeoptimised as it also introduces stress along the edges. This can be done by choosing an appropriate thickness for the encapsulation layer as well as the sacrificial layer that will later define the height of the microcavity on removal. This value was determined both numerically and verified by FEM simulation using COMSOL for rectangular and circular PECVD SiC encapsulation geometries, to ensure that the encapsulation does not collapse onto the microstructures. An example simulation result shown in Fig. 2 suggests that a 4pm thick, 200x200im2, self-supported PECVD SiC encapsulation undergoes a maximum deflection that is around 100nm. Based onthe FEMresults, the thickness of the PECVD SiC was fixed between 4pm-8pm in the encapsulationprocesses, discussedinthenextsection.

Figure 2. Simulation

of

the maximum

deformation of

a

4jum thick,

200x200jiM2

PECVD SiC

encapsulation

under

atmospheric

pressure

loading

Inclusion of Etch-Windows and Anchors

The third

design

issue concerns the geometry of the etch-windows that need to be etched in the

encapsulation

layer

for

removing

the sacrificial material so that the

encapsulation

and the MEMS can be released

simultaneously

and made

free-standing.

These etch-windows could be located either around the

periphery

of smaller microstructures or on top of the

larger

microstructures,

enabling quicker

release,

depending

onthe

device

design. According

to

[6]

theuse of slit

shaped

etch-windows instead of circular ones results in a smaller

principal

stress onthe

encapsulation layer.

So in this work,

horizontal and vertical 1x5

gm2

Slit

shaped

etch-windows that were

placed

apart

by

10Oim, representing

a unit cell, were

designed. Multiple

cellswere

placed

all over ontop of the

encapsulation layer

with

10Oim

spacing,

in order to

facilitate

quicker

release of the

encapsulation layer.

Yet another and

important design

issue is the inclusion of

support-pillars

or anchors in the MEMS device

design

that

can assist the

suspended encapsulation layer

to

spread

over

large-areas

without deformation. Anchors are

especially

required

for

accommodating large-area

MEMS structures, like accelerometers for instance, into the thin-film

package.

Thus,40x40

gm2 anchor

points

wereincluded inthe

design

of

large-area

thin SOI-MEMSstructures likeinertial sensors thatwere

placed

apart

by

150t m-225 im.

Encapsulated Geometries

A variety of circular and rectangular encapsulations with varying dimensions were designedto accommodate a wide range of microstructures that included cantilevers, resonators, micro-bridges, switches, accelerometers and gyroscopes. The diameter of the circular encapsulations intended for small-area microstructures ranged between 50pm-150gm. The minimum and maximum dimensions of the rectangular encapsulations ranged from a meagre 13x63gm2 for small area-microstructures through to

955x827gm2

for large-area thin-SOI microstructures. In the design of encapsulation for large area microstructures, the effective area of the rectangular encapsulations was minimised at fixed intervals to facilitate the mechanical stability of the long encapsulation layer.

ENCAPSULATION PROCESSES

Two wafer-level thin-film encapsulation processes, with integrated MEMS fabrication, were developed for surface micromachined and thin-SOI microstructures on 100mm wafers.A65MPalow tensilestress PECVD SiC layer, used for encapsulation and sealing, was obtained in a Novellus Concept One plasma deposition system that allows post-CMOS processing. The RIE of SiC was performed in an Alcatel GIR 300 plasma etch system. The key process parameters are summarised in Table 1. Also, proper etch selectivity was achieved against inorganic and organic sacrificial materials (likePECVDoxides andpolyimide),Al and Siusing different etch chemistries.

Table1: Key process parametersfor low-stressPECVD SiC Parameter Deposition Etching

SiH4 250sccm Gas GEl4 3000sccm FlwCF4 -70seem SF6 Io1seem 02 - 10sccm Temperature 400 °C

Pressure 2 Torr 37.5 Torr

HFPower 450 W 60 W

LFPower 150 W

SurfaceMicromachiningwithIntegratedPackaging The post-CMOS surface micromachining fabrication process with integrated PECVD SiC encapsulation is illustratedinFig. 3. Inthis process, Al was micromachined and used as the mechanical material as well as the electrodes, PECVD SiC was used as the encapsulation and sealing material and PECVD oxide was used as the sacrificial layer. The fabricationstartswith thesputtering of Al(1% Si) on a Si substrate pre-isolated with nitride or oxide followed by the deposition ofa 100nm PECVD SiC thin-filmlayer and then both layersarepatterned (Fig.3a-a). The PECVD SiC thin-film layer is usedtoprevent stiction and to provide isolation between the electrodes and the microstructure. Next,

1.5gm

of PECVD oxide sacrificial layer is deposited and patterned (Fig. 3a-b). This step is followed by sputtering of a

2.5gm

thick Al(1% Si) mechanicallayer that is micromachinedto form theMEMS structure (Fig. 3a-c). Later, a second PECVD oxide sacrificial layer is deposited and patterned (Fig. 3a-d). On

thetop of the sacrificial layer, againa 100nm PECVD SiC isolation layer is deposited that is followed by sputtering of a

0.6gm

second Al(1% Si) layer. Both layers are then patterned forming a second set of electrodes. A 4

gm

PECVD SiC is then used for encapsulation. At first, a 2pm PECVD SiC is deposited and patterned to create the first layer of encapsulation. Simultaneously, etch-windows are opened for sacrificial layer etching (Fig. 3a-e).The structure is then released by removing the PECVD oxide sacrificial layer in 73% HF, followed by a freeze-drying procedure to prevent stiction. Finally, another 2pm of PECVD SiC layer is deposited to seal the microcavity and to strengthen the encapsulation (Fig. 3a-f).

over the suspended PECVD SiC encapsulation layer and patterned, thus sealing themicrocavity (Fig. 3b-f). The layer also adds to the first encapsulation layer making it mechanically more robust. Now for devices requiring electrical contacts, the 8pm thick PECVD SiC layer is patterned and etched followed by the sputtering and patterning of

0.6gm

Al(1% Si) for the bond pads (Fig. 3b-g) completing the encapsulation process.

RESULTS

Several circular PECVD SiC encapsulations, suitable for small-area microstructures, ranging in diameters from

50gm-150gm

were realised using the presented process in Fig. 3a. Fig. 4a presents an array offree-standing circular microcavities after removal of thesacrificial layer. The etch-windows that were situated around the periphery of the encapsulations canalso be seen. A close-up cross-sectional view ofone suchencapsulation is visualisedinFig. 4b. The cross-sectional schematic and thetopview of the fabricated surface micromachined RF MEMS switch are shown in Fig. 5 and the electrical characterisation results of the RF switcharetabularisedinTable2. Inthisdevice, the function ofPECVD SiC is two-fold. Firstly, it has to hold the top electrode that is embedded beneath the PECVD SiC encapsulation layer and secondly, it has to encapsulate and seal the microcavity defining the zero-level packaged environment for deviceoperation.

Si -A PECVD Oxide | SiC - Si -Oxide -SiC Al

(a)

(b)

Figure 3: Processflow for: surface micromachined devices (a) and thin-SOI micromachined devices (b)

Thin-SOIMicromachining with Integrated Packaging The fabrication process for thin-SOI microstructures and their PECVD SiC encapsulation is presented in Fig. 3b. Here, an SOIsubstrate withathin active Si(thin-SOI) layer and areasonably thick buried oxide (BOX) layerwasused. PECVD oxidewasusedasthe sacrificial layer andPECVD SiC is used forencapsulation and sealing as with the other process. Processing starts withRIEof the active Si layerto define the microstructures (Fig. 3b-a) over which a

5gm-7gm

thick sacrificial PECVD oxide layer is deposited and

patterned (Fig. 3b-b). Then a 4pm PECVD SiC

encapsulation layer is deposited and patterned (Fig. 3b-c). Now etch-windows are patterned on the PECVD SiC encapsulation layer for accessing and etching the sacrificial layer together with the buried oxide (Fig. 3b-d). The sacrificial layer is then etched in40% HF that is succeeded by a freeze-drying procedure to prevent stiction, thereby simultaneously releasing the PECVD SiC encapsulation layer together with the thin-SOI microstructure (Fig. 3b-e). Another4pmofPECVD SiCsealing layer is then deposited

Figure 4: An array of free-standing circular SiC encapsulations (a); cross-sectionalviewofamicrocavity(b)

Figure 5: Schematic cross-section (a) and top view (b) of thesurface micromachinedRFswitch

Table2:Characterisation resultsoftheRFSwitch Device Parameter Values Resonantfrequency 204 kHz Qualityfactor 687.5 Pull-involtage 38 V Pull-offvoltage 1.18V/0.8 V Capacitance(down/up) 2.66pF/ 14.7fF Operatingvoltage 5V

In the thin-SOI micromachining process, illustrated in Fig. 3b,PECVD SiC thin-filmencapsulation ofavariety of small- and large-area microstructures were achieved. The

encapsulated small-area microstructures included cantilevers, resonators, micro-bridges, etc. Amongst large area microstructures, see Fig. 6, a range of accelerometers micromachined on thin-SOI before the deposition of the sacrificial oxide layer. The largest area encompassing the proof-mass and the comb electrodes requiring a successful encapsulation was, 955x827pm2, that of the left-most accelerometer seen inFig. 6a. The cross-sections inFig. 7a reveals the trenches thatwere first etched into Si and later filled with PECVD sacrificial oxide, over which the PECVD SiC encapsulation was applied. In order to reveal the interface of the contrasting

layers,

these samples were diced and then etched using HF. Fig. 7b shows an accelerometer structure encapsulated withPECVD SiC and patterned with etch-windows before removal of the sacrificial PECVD oxide and the buried oxide.

Figure 6: Thin-SOI accelerometers structures before encapsulation

Figure 7: Gross-sectionalviewrevealing contrasting layers after deposition ofPECVDSiO2 andPECVD SiClayers (a); top view ofan encapsulated accelerometer with patterned etch-windowsandbeforethesacrificialoxideetching (b)

Figure 8: Detailed view ofan encapsulated and released accelerometer showing variousparts after removal of the

sacrificialand buried oxide.

Fig. 8a presents a detailed view of a released device that was later cleaved showing the free-standing PECVD SiC encapsulation layer with etch-windows, the comb electrodes and the perforated proof-mass. Fig. 8b shows the PECVD SiC encapsulation layer anchored to one of the support-pillars that ismeant toimprove the reliability of thePECVD SiC encapsulation layer. A series of encapsulated, sealed and fullyreleased accelerometers are showninFig. 9a. The

Figure 9: Encapsulated and released accelerometers (a) andadetailed cross-sectionalview(b)

close-up SEM image in Fig. 9b shows the final free-standing 8pm thick PECVD SiC encapsulation obtained after sealing the etch-windows. Thus, the above results demonstrate the versatility of this encapsulation techniquetoaccommodateawiderangeofMEMSdevices.

CONCLUSIONS

We presented two encapsulation processes, related design issues and the results of a low-cost, robust and reliable wafer-level thin-film encapsulation for surface micromachined and thin-SOIMEMS devicesusing a 4gm-8gmthickstress-optimisedPECVDSiClayer.Awiderange of microstructures can be encapsulated in this process and results were demonstrated for microcavities, RF-switches, and accelerometers. The largest encapsulatedgeometry was about

955x827gm2.

The presented approach is CMOS-compatible and moreover, it enables a smaller footprintand reducedchip thickness comparedtowaferbonding.PECVD SiC based thin-film encapsulation technique for wafer-level MEMS packaging is very interesting for automotive, industrial and medical applications where devices are often subjected to harsh environments requiring astable, durable and reliableencapsulation layer.

ACKNOWLEDGEMENT

The authors, V. Rajaraman and P.J. French, would like to

gratefully acknowledge the financial support provided by NXP Semiconductors, The Netherlands. The authors wish to thank: Dr. H. Boezen and Dr. J.-J. Koning of NXP Semiconductors, Nijmegen, for their support, the staff of DIMES ICP Group, TU Delft, for their assistance during microfabrication, Dr. K.A.A. Makinwa ofEl,TUDelft, for his support, Q. Li, Dr. J.F.L. Goosenof 3ME, TUDelft, for the interesting discussions, and Dr. H.W. vanZeijlofDIMES, TUDelft,for his assistance in investigating the CMOS compatibility of PECVD SiC layers.

REFERENCES

[1] M.Esashi, J.Micromech. Microeng.,18, 2008, pp.1-13. [2] K. Najafi, Proc. SPIEMicromachining andMicrofabrication

ProcessTech.,Vol.4979, 2003, pp. 1-19.

[3] A.Hochstetal.,Sensorsand ActuatorsA, 114, 2004, pp. 355-361.

[4] D. Reuter et al., Sensors and Actuators A, 145-146, 2008, pp.316-322.

[5] P.Monajemietal.,J. Micromech. Microeng. 16, 2006, pp.742-750.

[6] Y.Shimookaetal.,Proc. ECTC2008,Florida, 2008,pp. 824-828.

[7] P.M. Sarro, Sensors andActuators A, 82, 2000, pp. 210-218. [8] H.T.M.Pham,PhDThesis, DelftUniv. ofTech.,NL, 2004. [9] L.S. Pakula et al., J. Micromech. Microeng., 14, 2004,

pp. 1478-1483.