ADS4222

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www.ti.com SBAS533C–MARCH 2011–REVISED JUNE 2011

Dual-Channel, 14-/12-Bit, 160/125/65MSPS Ultralow-Power ADC

Check for Samples:ADS4222,ADS4225,ADS4226,ADS4242,ADS4245,ADS4246

1

FEATURES APPLICATIONS

23• Ultralow Power with Single 1.8V Supply, • Wireless Communications Infrastructure

CMOS Output: • Software Defined Radio

– 183mW total power at 65MSPS • Power Amplifier Linearization – 277mW total power at 125MSPS

– 332mW total power at 160MSPS

DESCRIPTION

• High Dynamic Performance: The ADS424x/422x are low-speed variants of the ADS42xx ultralow-power family of dual-channel, – 88dBc SFDR at 170MHz

14-bit/12-bit analog-to-digital converters (ADCs).

– 71.4dBFS SNR at 170MHz

Innovative design techniques are used to achieve

• Crosstalk:>90dB at 185MHz high-dynamic performance, while consuming

• Programmable Gain up to 6dB for extremely low power with 1.8V supply. This topology SNR/SFDR Trade-off makes the ADS424x/422x well-suited for multi-carrier,

• DC Offset Correction wide-bandwidth communications applications.

• Output Interface Options: The ADS424x/422x have gain options that can be – 1.8V parallel CMOS interface used to improve SFDR performance at lower full-scale input ranges. These devices include a dc – Double data rate (DDR) LVDS with

offset correction loop that can be used to cancel the programmable swing:

ADC offset. Both DDR (double data rate) LVDS and – Standard swing: 350mV

parallel CMOS digital output interfaces are available – Low swing: 200mV in a compact QFN-64 PowerPAD™package.

• Supports Low Input Clock Amplitude

The devices include internal references while the Down to 200mV_PP

traditional reference pins and associated decoupling

• Package: QFN-64 (9mm×9mm)

capacitors have been eliminated. All devices are specified over the industrial temperature range (–40°C to +85°C).

ADS424x/422x FAMILY COMPARISON⁽¹⁾

250MSPS 160MSPS 125MSPS 65MSPS

ADS424x

ADS4249 ADS4246 ADS4245 ADS4242

14-bit family ADS422x

ADS4229 ADS4226 ADS4225 ADS4222

12-bit family

(1) See for details on migrating from the ADS62P49 family.

PERFORMANCE SUMMARY

ADS4246 ADS4245 ADS4242 ADS4226 ADS4225 ADS4222

SFDR (dBc), fIN= 20MHz 86 88 91 86 88 91

SFDR (dBc), fIN= 170MHz 82 88 85 82 88 85

SNR (dBFS), f_IN= 20MHz 72.8 73.4 73.6 70.5 70.8 70.9

SNR (dBFS), f_IN= 170MHz 70.4 71.4 71.2 69.5 69.9 69.9

Total power (mW/channel) 166 138 91 166 138 91

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments Incorporated.

3All other trademarks are the property of their respective owners.

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SBAS533C–MARCH 2011–REVISED JUNE 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

SPECIFIED

PACKAGE- PACKAGE TEMPERATURE LEAD/BALL PACKAGE ORDERING

PRODUCT LEAD DESIGNATOR RANGE ECO PLAN⁽²⁾ FINISH MARKING NUMBER TRANSPORT MEDIA

ADS4246IRGCT Tape and reel GREEN (RoHS, no

ADS4246 QFN-64 RGC –40°C to +85°C Cu/NiPdAu AZ4246

Sb/Br) ADS4246IRGCR Tape and reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder atwww.ti.com.

(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to theQuality and Lead-Free (Pb-Free) Dataweb site for more information.

The ADS424x/422x are pin-compatible with the previous generation ADS62P49 family of data converters; this architecture enables easy migration. However, there are some important differences between the two device generations, summarized inTable 1.

Table 1. Migrating from the ADS62P49

ADS62P49 FAMILY ADS424x/422x FAMILY

PINS

Pin 22 is NC (not connected) Pin 22 is AVDD

Pins 38 and 58 are DRVDD Pins 38 and 58 are NC (do not connect, must be floated) Pins 39 and 59 are DRGND Pins 39 and 59 are NC (do not connect, must be floated) SUPPLY

AVDD is 3.3V AVDD is 1.8V

DRVDD is 1.8V No change

INPUT COMMON-MODE VOLTAGE

VCM is 1.5V VCM is 0.95V

SERIAL INTERFACE

No change in protocol Protocol: 8-bit register address and 8-bit register data

New serial register map EXTERNAL REFERENCE

Supported Not supported

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ADS424x/422x

MIN MAX UNIT

Supply voltage range, AVDD –0.3 2.1 V

Supply voltage range, DRVDD –0.3 2.1 V

Voltage between AGND and DRGND –0.3 0.3 V

Voltage between AVDD to DRVDD (when AVDD leads DRVDD) –2.4 2.4 V

Voltage between DRVDD to AVDD (when DRVDD leads AVDD) –2.4 2.4 V

Minimum

INP_A, INM_A, INP_B, INM_B –0.3 V

(1.9, AVDD + 0.3)

Voltage applied to input pins CLKP, CLKM⁽²⁾ –0.3 AVDD + 0.3 V

RESET, SCLK, SDATA, SEN,

–0.3 3.9 V

CTRL1, CTRL2, CTRL3

Operating free-air temperature range, TA –40 +85 °C

Operating junction temperature range, T_J +125 °C

Storage temperature range, T_stg –65 +150 °C

ESD rating Human body model (HBM) 2 kV

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|).

This configuration prevents the ESD protection diodes at the clock input pins from turning on.

THERMAL INFORMATION

ADS42xx

THERMAL METRIC⁽¹⁾ RGC UNITS

64 PINS

θJA Junction-to-ambient thermal resistance 23.9

θ_JCtop Junction-to-case (top) thermal resistance 10.9

θ_JB Junction-to-board thermal resistance 4.3

ψ_JT Junction-to-top characterization parameter 0.1 °C/W

ψJB Junction-to-board characterization parameter 4.4

θJCbot Junction-to-case (bottom) thermal resistance 0.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,SPRA953.

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RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range, unless otherwise noted.

ADS424x/422x

PARAMETER MIN NOM MAX UNIT

SUPPLIES

Analog supply voltage, AVDD 1.7 1.8 1.9 V

Digital supply voltage, DRVDD 1.7 1.8 1.9 V

ANALOG INPUTS

Differential input voltage range 2 V_PP

Input common-mode voltage VCM±0.05 V

Maximum analog input frequency with 2V_PPinput amplitude⁽¹⁾ 400 MHz

Maximum analog input frequency with 1VPPinput amplitude⁽¹⁾ 600 MHz

CLOCK INPUT

Input clock sample rate (ADS4242/ADS4222)

Low-speed mode enabled (by default after reset) 1 65 MSPS

Low-speed mode enabled⁽²⁾ 1 80 MSPS

Low-speed mode disabled⁽²⁾(by default after reset) 80 125 MSPS

Low-speed mode enabled⁽²⁾ 1 80 MSPS

Low-speed mode disabled⁽²⁾(by default after reset) 80 160 MSPS

Sine wave, ac-coupled 0.2 1.5 VPP

LVPECL, ac-coupled 1.6 VPP

Input clock amplitude differential

(V_CLKP–V_CLKM) LVDS, ac-coupled 0.7 V_PP

LVCMOS, single-ended, ac-coupled 1.5 V

Input clock duty cycle

Low-speed mode disabled 35 50 65 %

Low-speed mode enabled 40 50 60 %

DIGITAL OUTPUTS

Maximum external load capacitance from each output pin to DRGND, C_LOAD 5 pF

Differential load resistance between the LVDS output pairs (LVDS mode), R_LOAD 100 Ω

Operating free-air temperature, TA –40 +85 °C

(1) See theTheory of Operationsection in the Application Information.

(2) See theSerial Interface Configurationsection for details on programming the low-speed mode.

HIGH-PERFORMANCE MODES^{(1) (2)}

PARAMETER DESCRIPTION

Set the HIGH PERF MODE register bit to obtain best performance across sample clock and High-performance mode input signal frequencies.

Register address = 03h, data = 03h

Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input signal frequencies greater than 200MHz.

High-frequency mode

Register address = 4Ah, data = 01h Register address = 58h, data = 01h (1) It is recommended to use these modes to obtain best performance.

(2) See theSerial Interface Configurationsection for details on register programming.

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ELECTRICAL CHARACTERISTICS: ADS4246/ADS4245/ADS4242

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle,–1dBFS differential analog input, LVDS interface, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:

T_MIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.8V.

ADS4246 (160MSPS) ADS4245 (125MSPS) ADS4242 (65MSPS)

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Resolution 14 14 14 Bits

f_IN= 20MHz 72.8 73.4 73.6 dBFS

f_IN= 70MHz 72.5 70 72.9 69.5 72.5 dBFS

Signal-to-noise ratio SNR f_IN= 100MHz 72.2 72.6 72.3 dBFS

fIN= 170MHz 69 71.2 71.4 70.4 dBFS

f_IN= 300MHz 69.4 69.3 69.4 dBFS

f_IN= 20MHz 72.6 73.2 73.5 dBFS

f_IN= 70MHz 72.1 69 72.6 68.5 72.3 dBFS

Signal-to-noise and

SINAD f_IN= 100MHz 71.7 72.3 72.1 dBFS

distortion ratio

fIN= 170MHz 67.5 70.8 71.2 70.2 dBFS

f_IN= 300MHz 68 68.5 68.2 dBFS

f_IN= 20MHz 86 88 91 dBc

f_IN= 70MHz 84 73.5 86 73.5 88 dBc

Spurious-free dynamic range SFDR f_IN= 100MHz 82 85 87 dBc

fIN= 170MHz 72 82 88 85 dBc

f_IN= 300MHz 78 78 74 dBc

f_IN= 20MHz 84 86 88 dBc

f_IN= 70MHz 81 72 84 72 85 dBc

Total harmonic distortion THD f_IN= 100MHz 81 83 85 dBc

fIN= 170MHz 70 80 84 82 dBc

f_IN= 300MHz 76 75 73 dBc

f_IN= 20MHz 86 88 91 dBc

f_IN= 70MHz 84 73.5 86 73.5 88 dBc

Second-harmonic distortion HD2 f_IN= 100MHz 82 85 87 dBc

fIN= 170MHz 72 82 88 85 dBc

f_IN= 300MHz 78 78 74 dBc

f_IN= 20MHz 92 93 95 dBc

f_IN= 70MHz 86 73.5 89 73.5 90 dBc

Third-harmonic distortion HD3 f_IN= 100MHz 93 89 96 dBc

fIN= 170MHz 72 94 90 87 dBc

f_IN= 300MHz 80 81 81 dBc

f_IN= 20MHz 90 95 98 dBc

f_IN= 70MHz 92 78 94 79 97 dBc

Worst spur

f_IN= 100MHz 89 93 95 dBc

(other than second and third harmonics)

fIN= 170MHz 77 89 91 93 dBc

f_IN= 300MHz 91 89 92 dBc

f₁= 46MHz, f₂= 50MHz,

96 96 98 dBFS

each tone at–7dBFS Two-tone intermodulation

distortion IMD f₁= 185MHz, f₂= 190MHz,

83 92 92 dBFS

each tone at–7dBFS

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ELECTRICAL CHARACTERISTICS: ADS4246/ADS4245/ADS4242 (continued)

20-MHz full-scale signal on channel under observation;

Crosstalk 95 95 95 dB

170-MHz full-scale signal on other channel Recovery to within 1%

Clock

Input overload recovery (of full-scale) for 6dB overload 1 1 1

cycle with sine-wave input

AC power-supply rejection For 100mV_PPsignal on AVDD

PSRR >30 >30 >30 dB

ratio supply, up to 10MHz

f_IN= 70MHz

Effective number of bits ENOB (ADS4245, ADS4242) 11.5 11.5 11.4 LSBs

f_IN= 170MHz (ADS4246) fIN= 70MHz

Differential nonlinearity DNL (ADS4245, ADS4242) –0.97 ±0.5 1.7 –0.97 ±0.5 1.7 –0.97 ±0.5 1.7 LSBs

fIN= 170MHz (ADS4246) f_IN= 70MHz

Integrated nonlinearity INL (ADS4245, ADS4242) ±2 ±5 ±2 ±5 ±2 ±5 LSBs

f_IN= 170MHz (ADS4246)

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ELECTRICAL CHARACTERISTICS: ADS4226/ADS4225/ADS4222

Resolution 12 12 12 Bits

f_IN= 20MHz 70.5 70.8 70.9 dBFS

f_IN= 70MHz 70.3 68.0 70.5 68.0 70.3 dBFS

Signal-to-noise ratio SNR f_IN= 100MHz 70.1 70.3 70.2 dBFS

fIN= 170MHz 67.5 69.5 69.9 69.9 dBFS

f_IN= 300MHz 68.2 68.1 68.2 dBFS

f_IN= 20MHz 70.4 70.7 70.8 dBFS

f_IN= 70MHz 70.1 67.0 70.3 67.0 70.2 dBFS

Signal-to-noise and

SINAD f_IN= 100MHz 69.8 70.1 70.1 dBFS

distortion ratio

fIN= 170MHz 66.5 69.3 69.5 68.7 dBFS

f_IN= 300MHz 67.6 67.5 67.2 dBFS

f_IN= 20MHz 86 88 91 dBc

f_IN= 70MHz 84 72.5 86 72.5 88 dBc

Spurious-free dynamic range SFDR f_IN= 100MHz 82 85 87 dBc

fIN= 170MHz 70 82 88 85 dBc

f_IN= 300MHz 78 78 74 dBc

f_IN= 20MHz 84 86 88 dBc

f_IN= 70MHz 81 70.0 84 71.0 85 dBc

Total harmonic distortion THD f_IN= 100MHz 81 83 85 dBc

fIN= 170MHz 68 80 84 82 dBc

f_IN= 300MHz 76 75 73 dBc

f_IN= 20MHz 86 88 91 dBc

f_IN= 70MHz 84 72.5 86 72.5 88 dBc

Second-harmonic distortion HD2 f_IN= 100MHz 82 85 87 dBc

fIN= 170MHz 70 82 88 85 dBc

f_IN= 300MHz 78 78 74 dBc

f_IN= 20MHz 92 93 95 dBc

f_IN= 70MHz 86 72.5 89 72.5 90 dBc

Third-harmonic distortion HD3 f_IN= 100MHz 93 89 96 dBc

fIN= 170MHz 70 94 90 87 dBc

f_IN= 300MHz 80 81 81 dBc

f_IN= 20MHz 90 95 98 dBc

f_IN= 70MHz 92 76.0 94 77.0 97 dBc

Worst spur

f_IN= 100MHz 89 93 95 dBc

(other than second and third harmonics)

fIN= 170MHz 75 89 91 93 dBc

f_IN= 300MHz 91 89 92 dBc

f₁= 46MHz, f₂= 50MHz,

96 96 98 dBFS

each tone at–7dBFS Two-tone intermodulation

distortion IMD f₁= 185MHz, f₂= 190MHz,

83 92 92 dBFS

each tone at–7dBFS

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ELECTRICAL CHARACTERISTICS: ADS4226/ADS4225/ADS4222 (continued)

20MHz full-scale signal on channel under observation;

Crosstalk 95 95 95 dB

170MHz full-scale signal on other channel Recovery to within 1%

Clock

Input overload recovery (of full-scale) for 6dB overload 1 1 1

cycle with sine-wave input

AC power-supply rejection For 100mV_PPsignal on AVDD

PSRR 30 30 30 dB

ratio supply, up to 10MHz

f_IN= 70MHz

Effective number of bits ENOB (ADS4225, ADS4222) 11.2 11.3 11.1 LSBs

f_IN= 170MHz (ADS4226) fIN= 70MHz

Differential nonlinearity DNL (ADS4225, ADS4222) –0.8 ±0.13 1.5 –0.8 ±0.13 1.5 –0.8 ±0.13 1.2 LSBs

fIN= 170MHz (ADS4226) f_IN= 70MHz

Integrated nonlinearity INL (ADS4225, ADS4222) ±0.5 ±3.5 ±0.5 ±3.5 ±0.5 ±2.5 LSBs

f_IN= 170MHz (ADS4226)

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ELECTRICAL CHARACTERISTICS: GENERAL

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and–1dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN=–40°C to TMAX= +85°C, AVDD = 1.8V, and DRVDD = 1.8V.

ADS4246/ADS4226 (160MSPS) ADS4245/ADS4225 (125MSPS) ADS4242/ADS4222 (65MSPS)

PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

ANALOG INPUTS

Differential input voltage range (0dB gain) 2 2 2 V_PP

Differential input resistance (at 200MHz) 0.75 0.75 0.75 kΩ

Differential input capacitance (at 200MHz) 3.7 3.7 3.7 pF

Analog input bandwidth

550 550 550 MHz

(with 50Ωsource impedance, and 50Ωtermination) Analog input common-mode current

1.5 1.5 1.5 µA/MSPS

(per input pin of each channel)

Common-mode output voltage VCM 0.95 0.95 0.95 V

VCM output current capability 4 4 4 mA

DC ACCURACY

Offset error –15 2.5 15 –15 2.5 15 –15 2.5 15 mV

Temperature coefficient of offset error 0.003 0.003 0.003 mV/°C

Gain error as a result of internal

E_GREF –2 2 –2 2 –2 2 %FS

reference inaccuracy alone

Gain error of channel alone E_GCHAN ±0.1 –1 ±0.1 ±0.1 –1 %FS

Temperature coefficient of E_GCHAN 0.002 0.002 0.002 Δ%/°C

POWER SUPPLY IAVDD

123 150 105 130 73 85 mA

Analog supply current IDRVDD

Output buffer supply current

111 135 99 120 78 95 mA

LVDS interface, 350mV swing with 100Ωexternal termination, f_IN= 2.5MHz

IDRVDD

Output buffer supply current

61 49 28 mA

CMOS interface, no load capacitance⁽¹⁾ f_IN= 2.5MHz

Analog power 222 189 133 mW

Digital power

LVDS interface, 350mV swing with 100Ωexternal 199 179 131 mW

termination, fIN= 2.5MHz Digital power

CMOS interface, no load capacitance⁽¹⁾ 109 88 50 mW

f_IN= 2.5MHz

Global power-down 25 25 25 mW

(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see theCMOS Interface Power Dissipationsection in theApplication Information).

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DAn_P DBn_P

DAn_M DBn_M

GND

Logic 0 V_ODL= 350mV- ⁽¹⁾

Logic 1 V_ODH= +350mV⁽¹⁾

V_OCM

DIGITAL CHARACTERISTICS

At AVDD = 1.8V and DRVDD = 1.8V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level'0'or'1'.

ADS424x/422x

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)⁽¹⁾

High-level input voltage All digital inputs support 1.8V 1.3 V

and 3.3V CMOS logic levels

Low-level input voltage 0.4 V

SDATA, SCLK⁽²⁾ VHIGH= 1.8V 10 µA

High-level input current

SEN⁽³⁾ V_HIGH= 1.8V 0 µA

SDATA, SCLK VLOW= 0V 0 µA

Low-level input current

SEN VLOW= 0V 10 µA

DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)

High-level output voltage DRVDD–0.1 DRVDD V

Low-level output voltage 0 0.1 V

Output capacitance (internal to device) pF

DIGITAL OUTPUTS, LVDS INTERFACE

High-level output With an external

VODH 270 350 430 mV

differential voltage 100Ωtermination

Low-level output With an external

VODL –430 –350 –270 mV

differential voltage 100Ωtermination

Output common-mode voltage V_OCM 0.9 1.05 1.25 V

(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.

(2) SDATA, SCLK have internal 150kΩpull-down resistor.

(3) SEN has an internal 150kΩpull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers.

(1) With external 100Ωtermination.

Figure 1. LVDS Output Voltage Levels

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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DRVDD DA6P DA6M DA4P DA4M DA2P DA2M DA0P DA0M NC NC CTRL3 CTRL2 CTRL1 AVDD AVDD 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRVDD

DB4M DB4P DB6M DB6P DB8M DB8P DB10M DB10P DB12M DB12P RESET SCLK SDATA SEN AVDD

SDOUT DB2P DB2M DB0P DB0M NC NC CLKOUTP CLKOUTM DA12P DA12M DA10P DA10M DA8P DA8M DRGND

AGND AGND INP_B INM_B AGND AVDD VCM AGND CLKP CLKM AGND AGND INP_A INM_A AGND AGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

Thermal Pad (Connected to DRGND)

PIN CONFIGURATION: LVDS MODE

RGC PACKAGE⁽²⁾ QFN-64 (TOP VIEW)

(2) The PowerPAD is connected to DRGND.

NOTE: NC = do not connect; must float.

Figure 2. ADS4246/ADS4245/ADS4242 LVDS Mode

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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DRVDD DA4P DA4M DA2P DA2M DA0P DA0M NC NC NC NC CTRL3 CTRL2 CTRL1 AVDD AVDD 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRVDD

DB2M DB2P DB4M DB4P DB6M DB6P DB8M DB8P DB10M DB10P RESET SCLK SDATA SEN AVDD

SDOUT DB0P DB0M NC NC NC NC CLKOUTP CLKOUTM DA10P DA10M DA8P DA8M DA6P DA6M DRGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RGC PACKAGE⁽³⁾ QFN-64 (TOP VIEW)

Figure 3. ADS4226/ADS4225/ADS4222 LVDS Mode

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Pin Descriptions: LVDS Mode

PIN NUMBER PIN NAME # OF PINS FUNCTION DESCRIPTION

1, 48 DRVDD 2 Input Output buffer supply

Serial interface RESET input.

When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the 12 RESET 1 Input software reset option; refer to theSerial Interface Configurationsection.

In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150kΩpull-down resistor.

This pin functions as a serial interface clock input when RESET is low. It controls 13 SCLK 1 Input the low-speed mode selection when RESET is tied high; seeTable 5for detailed

information. This pin has an internal 150kΩpull-down resistor.

14 SDATA 1 Input Serial interface data input; this pin has an internal 150kΩpull-down resistor.

This pin functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high;

15 SEN 1 Input

seeTable 6for detailed information. This pin has an internal 150kΩpull-up resistor to AVDD.

16, 22, 33, 34 AVDD 4 Input Analog power supply

17, 18, 21, 24,

AGND 8 Input Analog ground

27, 28, 31, 32

19 INP_B 1 Input Differential analog positive input, channel B

20 INM_B 1 Input Differential analog negative input, channel B

This pin outputs the common-mode voltage (0.95V) that can be used externally to

23 VCM 1 Output

bias the analog input pins

25 CLKP 1 Input Differential clock positive input

26 CLKM 1 Input Differential clock negative input

29 INP_A 1 Input Differential analog positive input, channel A

30 INM_A 1 Input Differential analog negative input, channel A

35 CTRL1 1 Input Digital control input pins. Together, they control the various power-down modes.

49, PAD DRGND 2 Input Output buffer ground

56 CLKOUTM 1 Output Differential output clock, complement

57 CLKOUTP 1 Output Differential output clock, true

This pin functions as a serial interface register readout when the READOUT bit is

64 SDOUT 1 Output

enabled. When READOUT = 0, this pin is in high-impedance state.

Refer to

Figure 2and DA0P, DA0M 2 Output Channel A differential output data pair, D0 and D1 multiplexed Figure 3

Refer to

Figure 2and DA2P, DA2M 2 Output Channel A differential output data D2 and D3 multiplexed Figure 3

Refer to

Figure 2and DA12P, DA12M 2 Output Channel A differential output data D12 and D13 multiplexed (ADS424x only) Figure 3

Refer to

Figure 2and DB0P, DB0M 2 Output Channel B differential output data pair, D0 and D1 multiplexed Figure 3

Refer to

Figure 2and DB2P, DB2M 2 Output Channel B differential output data D2 and D3 multiplexed Figure 3

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Pin Descriptions: LVDS Mode (continued)

PIN NUMBER PIN NAME # OF PINS FUNCTION DESCRIPTION

Refer to

Figure 2and DB12P, DB12M 2 Output Channel B differential output data D12 and D13 multiplexed (ADS424x only) Figure 3

Refer to Figure 38,

8 (ADS422x)

Figure 39, NC — Do not connect, must be floated

4 (ADS424x) Figure 56, and

Figure 57

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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DRVDD DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 NC NC CTRL3 CTRL2 CTRL1 AVDD AVDD 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRVDD

DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 RESET SCLK SDATA SEN AVDD

SDOUT DB3 DB2 DB1 DB0 NC NC CLKOUT UNUSED DA13 DA12 DA11 DA10 DA9 DA8 DRGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PIN CONFIGURATION: CMOS MODE

RGC PACKAGE⁽⁴⁾ QFN-64 (TOP VIEW)

Figure 4. ADS4246/ADS4245/ADS4242 CMOS Mode

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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DRVDD DA5 DA4 DA3 DA2 DA1 DA0 NC NC NC NC CTRL3 CTRL2 CTRL1 AVDD AVDD 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRVDD

DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 RESET SCLK SDATA SEN AVDD

SDOUT DB1 DB0 NC NC NC NC CLKOUT UNUSED DA11 DA10 DA9 DA8 DA7 DA6 DRGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RGC PACKAGE⁽⁵⁾ QFN-64 (TOP VIEW)

Figure 5. ADS4226/ADS4225/ADS4222 CMOS Mode

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Pin Descriptions: CMOS Mode

# OF

PIN NUMBER PIN NAME PINS FUNCTION DESCRIPTION

1, 48 DRVDD 2 Input Output buffer supply

Serial interface RESET input.

When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset 12 RESET 1 Input option; refer to theSerial Interface Configurationsection.

In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN are used as parallel control pins in this mode. This pin has an internal 150kΩ pull-down resistor.

This pin functions as a serial interface clock input when RESET is low. It controls the 13 SCLK 1 Input low-speed mode when RESET is tied high; seeTable 5for detailed information. This pin

has an internal 150kΩpull-down resistor.

14 SDATA 1 Input Serial interface data input; this pin has an internal 150kΩpull-down resistor.

This pin functions as a serial interface enable input when RESET is low. It controls the 15 SEN 1 Input output interface and data format selection when RESET is tied high; seeTable 6for

detailed information. This pin has an internal 150kΩpull-up resistor to AVDD.

16, 22, 33, 34 AVDD 4 Input Analog power supply

17, 18, 21, 24, 27, 28,

AGND 8 Input Analog ground

31, 32

19 INP_B 1 Input Differential analog positive input, channel B 20 INM_B 1 Input Differential analog negative input, channel B

This pin outputs the common-mode voltage (0.95V) that can be used externally to bias

23 VCM 1 Output

the analog input pins

25 CLKP 1 Input Differential clock positive input

26 CLKM 1 Input Differential clock negative input

29 INP_A 1 Input Differential analog positive input, channel A 30 INM_A 1 Input Differential analog negative input, channel A

35 CTRL1 1 Input Digital control input pins. Together, they control various power-down modes.

49, PAD DRGND 2 Input Output buffer ground

56 UNUSED 1 — This pin is not used in the CMOS interface

57 CLKOUT 1 Output CMOS output clock

This pin functions as a serial interface register readout when the READOUT bit is

64 SDOUT 1 Output

enabled. When READOUT = 0, this pin is in high-impedance state.

Refer toFigure 4and

DA0 to DA11 12 Output Channel A ADC output data bits, CMOS levels Figure 5

Refer toFigure 4 DA12 to DA13 2 Output Channel A ADC output data bits, CMOS levels (ADS424x only) Refer toFigure 4and

DB0 to DB11 12 Output Channel B ADC output data bits, CMOS levels Figure 5

Refer toFigure 4 DB12 to DB13 2 Output Channel B ADC output data bits, CMOS levels (ADS424x only)

— NC 1 — Do not connect, must be floated