Electrothermal Behavior of High-Frequency Silicon-On-Glass Transistors

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Electrothermal Behavior of

High-Frequency

Silicon-On-Glass Transistors

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Electrothermal Behavior of

High-Frequency Silicon-On-Glass

Transistors

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus Prof. dr. ir. J. T. Fokkema, voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op maandag 1 november 2004 om 15:30 uur

door

Nebojˇsa NENADOVI ´

C

Electrical Engineer van Universiteit van Belgrado, Servi¨e en Montenegro, geboren te Belgrado, Servi¨e en Montenegro

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Dit proefschrift is goedgekeurd door de promotoren: Prof. dr. L. K. Nanver

Prof. dr. ir. J. W. Slotboom

Samenstelling promotiecommissie: Rector Magnificus, voorzitter

Prof. dr. L. K. Nanver, Technische Universiteit Delft, promotor Prof. dr. ir. J. W. Slotboom, Technische Universiteit Delft, promotor Prof. dr. Ing. J. N. Burghartz, Technische Universiteit Delft

Prof. dr. N. Rinaldi, University of Naples ”Federico II” (Italy) Prof. dr. H. F. F. Jos, Chalmers University of Technology (Sweden) Dr. ir. L. K. J. Vandamme, Technische Universiteit Eindhoven Dr. R. Dekker, Philips Research Eindhoven

Nebojˇsa Nenadovi´c,

Electrothermal Behavior of High-Frequency Silicon-On-Glass Transistors, Ph.D. Thesis Delft University of Technology,

with summary in Dutch.

Keywords: electrothermal effects in semiconductor devices, bipolar transistors, metal-oxide-semiconductor field effect transistors, substrate transfer, silicon-on-insulator.

ISBN: 90-6464-114-5

Copyright c° 2004 by Nebojˇsa Nenadovi´c

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the prior written permission of the copyright owner.

Printed by Grafisch bedrijf Ponsen & Looijen BV, Wageningen, The Nether-lands.

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Chapter 1 Introduction

In this thesis electrothermal characteristics of the silicon-on-glass transistors are studied by employing experimental measurements and numerical simu-lations. The experimental devices are fabricated in a substrate transfer te-chnology invented at Philips Research [1–3] with additional post-processing techniques developed by both Philips and DIMES. This technology has been used in the last few years for enhancing functionality of radio-frequency (RF) devices and circuits [4–9]. Both integrated bipolar and discrete power MOS transistors on glass are investigated in the present work. While the electrother-mal characterization no doubt has become the most important result of the present work, it was research born out of bitter necessity. For the success of the future IC generations, electrothermal issues must be dealt with and brought under control. Nevertheless, exploring the potentials of silicon-on-glass for in-troducing of new types of device has been the true driver for this research. In this respect, new silicon-on-glass VDMOS transistors for 2 GHz base station applications were also fully developed and fabricated during the research.

This introductory chapter discusses the evolution of substrate transfer technology and explains the need for electrothermal characterization of the transferred devices and high-frequency transistors in general. The motivation and objectives of the research are highlighted, and finally the outline of the thesis is drawn.

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2 Introduction

1980 1990 2000 2010 2020

µP+Memory (CMOS, DRAM)

DSP+RF

(CMOS, DRAM, SiGe, GaAs, passives...)

Computer

Moore's Law Scaling 70 % every 2-3 years

Moore's Law

Communication

SOC & SIP integration

Figure 1.1: In the Communication Age, Moore’s Law will continue to be a technology imperative. However, System-On-a-Chip and System-In-a-Package integration will also drive down the cost of Personal Communication Systems.

1.1 RF circuit integration

In the past 25 years, much of the worldwide output of the semiconductor industry was destined for the consumer market, in particular for personal computers. Today, however, the worldwide demand for personal wireless com-munication, everywhere, anytime, is growing much faster than demand for personal computation. As is shown in Fig. 1.1, for the past 20 years the in-dustry has followed Moore’s Law. During this so called Computer Age, the digital CMOS and DRAM technologies have been dominant on the market. The feature size has been reduced by 70 % every two-three years while the cost of the same chip area containing a much larger number of transistors decreased. In the Communication Age Moore’s Law will continue to be a te-chnology imperative and will enable novel radio-frequency (RF) products that have a lot of new capabilities at little or no additional cost.

However, the level of integration of RF systems is still far below that of the digital systems. Monolithic RF transceivers made on conventional silicon substrates have serious performance limitations: a parasitic signal transfer

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1.2 Substrate transfer silicon-on-glass technology 3

through the silicon causes undesirable feedback or crosstalk between circuits, while the capacitive and eddy current losses severely effect the quality of in-tegrated inductors [10, 11]. Therefore, RF functions are typically realized by very few RF integrated circuits (ICs) and a large number of lumped and dis-tributed passive components for filtering and biasing purposes. This approach is flexible but results in large area and large cost. However, for new, com-mercially driven applications of the Communication Age, RF systems must be small in size, low in cost, fabricated in large volumes and have low power consumption.

A number of bulk-silicon substrate modifications have been proposed re-cently with the objective to reduce substrate losses, and thus increase the speed of active devices and improve the quality of integrated passives. This allows a higher level of integration and better functionality of RF ICs. Some of the solutions are based on the introduction of silicon-on-insulator (SOI) substrates [12–15], high- and low-resistivity silicon substrates [11, 16], shallow and deep trench isolation [17], bulk-silicon micromachining [18] and substrate transfer techniques [1].

However, the path to further cost reduction and performance improvement of RF products is to find a balance between the System-On-a-Chip (SOC) [19] and System-In-a-Package (SIP) integration [20, 21]. While the SOC solution dictates monolithic integration of high quality passives and RF, CMOS and DRAM devices, the SIP approach relaxes the compatibility by keeping dif-ferent technologies on difdif-ferent dies and then connecting them directly by for example vertical interconnects. This allows manufacturers to optimize each die’s performance while keeping cost down. In the SIP solution functional blocks are integrated on a small module, by combining a few ICs of different technologies (e.g. CMOS, DRAM, SiGe or GaAs) in a single package with pas-sive components. This provides more cost-effective solutions in a shorter time to market than the SOC solutions. With substrate transfer techniques, such a semi-monolithic combination of different technologies can be realized on a wafer-scale level all the way to the packaging [22, 23].

1.2 Substrate transfer silicon-on-glass

te-chnology

Silicon substrate modifications, in particular substrate transfer techniques, show great promise for future RF systems. Substrate transfer is already

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com-4 Introduction

monly used in the world of GaAs and InP [24–26]. In silicon processing, the first substrate transfer techniques were demonstrated as early as forty years ago [27], but particularly over the last years many groups have performed research on utilization of adhesive and direct wafer bonding (also called the fusion bonding) [28–34]. However, until recently none of these attempts were brought to a production level with the required high yield and low cost. In 1997, Ronald Dekker from Philips Research Eindhoven introduced a novel sub-strate transfer technique (STT) [2,3], which was soon after put into production in the SPIRIT process at the Philips IC Foundry Hamburg. A schematic of the process flow is shown in Fig. 1.2. A fully processed bulk-silicon or silicon-on-insulator (SOI) wafer (a) is glued to an alternative substrate (e.g. the glass wafer) by means of a monomer activated by the UV light or at an elevated temperature of 200◦_{C to form a hard acrylic (b). This technique has three} major advantages with respect to many other bonding techniques:

1. it is a low temperature bonding technique,

2. it does not require application of high-voltages during bonding, and 3. it does not require a flat wafer surface for bonding.

Thus, it is possible to bond the fully processed wafers to any substrate despite the silicon wafer surface topology and discrepancies in thermal expansion co-efficients.

After gluing, the silicon substrate is removed by grinding and chemical etching (c). In the basic substrate transfer technology from Fig. 1.2, the back-wafer processing was limited to first a simple mechanical alignment, with an accuracy of ±100 µm, and, second, contacting only to the metallic bondpads (d). Originally, the technology was called the silicon-on-anything (SOA), high-lighting the arbitrary choice of the alternative substrate (see Fig. 1.3): it has become possible to fabricate a monocrystalline layer of silicon on the top of any substrate.

The choice of glass in the silicon-on-anything technology is made for at least three important reasons: first glass is a very good electrical insulator, second it is cheap material and third it is transparent for the UV light that is used to cure the glue. The first transistors fabricated in silicon-on-glass technology were ultra-low power lateral BJTs, demonstrated by Dekker et al. in 1997 [3]. These devices were made on expensive SOI starting material. A year later a more low-cost substrate transfer technology, applying much cheaper bulk-silicon wafers, was also demonstrated by Dekker [4]. In this

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bondpad

silicon

circuit

adhesive

glass substrate

BOX

(a)

BOX

(b)

UV curing

(c)

glass substrate

(d)

glass substrate

bond area

silicon

oxide

glass

metal

Figure 1.2: Schematic cross section of the transfer of an SOI wafer to a glass substrate. (a) Fully processed SOI wafer showing a silicon circuit and bondpad on a buried oxide (BOX). (b) Curing of adhesive by UV exposure through the glass substrate. (c) Removal of the silicon substrate selective toward the buried oxide. (d) Optional deposition of a scratch protection layer and opening of bondpads. (After Dekker [1]).

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6 Introduction

Figure 1.3: Silicon circuits transferred to different types of substrates: glass (8 and 6 inch), aluminum nitride, alumina, ferrite, and flexible glass-fiber epoxy. (After Dekker [1]).

process, schematically presented in Fig. 1.4, the vertical bipolar devices are contacted on the back-wafer via large n+ _regions.

Soon after this, the Philips silicon-on-glass technology was transferred to DIMES to be used for independent research. Several novel techniques for en-hancing the post-processing (i.e. the back-wafer processing) of the transferred wafers were developed by DIMES:

1) van Zeijl et al. [6] developed front- to back-wafer alignment with a sin-gle wafer-stepper and mirror-symmetric alignment markers yielding the back-wafer patterning to the front-wafer with a precision of 3σ=350 nm; 2) Nanver et al. [5] demonstrated ultra-low temperature low-ohmic contact-ing to both p- and n-type silicon uscontact-ing laser annealcontact-ing. Post-processcontact-ing of the glued wafers is restricted to low-temperatures since the integrity of the metallization on the front-wafer and glue are limited to 400◦_C and 300◦_{C, respectively. However, by local heating with the laser it} is possible to activate implanted dopants on the back-wafer and form low-ohmic contacts.

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bondpad

spiral inductor

silicon substrate

circuit

(a)

(b)

(c)

(d)

(e)

glass substrate

silicon substrate

glass substrate

active devices

bondpad high Q inductor

Figure 1.4: Schematic processing sequence to transfer non-SOI wafers to glass. (a) A fully processed wafer with active devices grouped into functional units. (b) Gluing of wafer to a glass substrate. (c) Silicon thinned to 50 µm. (d) Deposition and patterning of PECVD nitride etch-mask. (e) Etching of the silicon using the field oxide as an etch-stop. (After Dekker [1]).

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8 Introduction

A back-wafer contacted silicon-on-glass integrated bipolar pro-cess

Laser annealing and high-precision front- to back-wafer alignment have been used in DIMES to develop a back-wafer contacted silicon-on-glass integrated bipolar process [8]. The basic process flow for the fabrication of a NPN transis-tor in such technology is shown in Fig. 1.5, where the silicon-on-glass structure is also compared to the corresponding bulk transistor, a 25-GHz DIMES-04 fully-implanted NPN BJT [35]. The conventional silicon wafers with buried n+ layers and epi are replaced by SOI wafers with a 0.84-µm n-doped silicon top layer. The pedestal collector region is implanted with phosphorous and extrin-sic base regions are doped by a low-dose deep B+ implant (to compensate the n-epi) and a high-dose shallow B+ _{contact implant. The active device areas}

are isolated by means of trenches etched to the buried oxide. The emitter and base are processed and contacted following standard front-wafer processing procedures (a). After gluing the front-wafer onto glass, the silicon substrate is removed. The front- to back-wafer high precision alignment [6] is used to align minimum-dimension contact windows on the back-wafer to front-wafer structures. The back-wafer processing starts with the deposition of a 0.3-µm Al/Si reflective masking layer at room temperature onto the buried oxide. All contact windows are plasma etched to the silicon and implantations are per-formed with an oversized resist mask. They are laser annealed [8] using the XMR5121 XeCl excimer laser system. After laser annealing (b), a HF dip etch step is performed to remove the native oxide. In this step most of the Al/Si mask is also removed and the windows are contacted by sputtering a new layer of Al/Si(1%). The device processing is completed by opening contacts to the front-wafer metal, sputtering and patterning a final layer of 0.8-µm Al/Si on the back-wafer (c).

Pure electrically the resulting integrated silicon-on-glass bipolar process has many potential advantages for the integration of high-performance low-power RF circuits. First, the lossy silicon substrate is replaced by a low-loss glass substrate. Second, the devices are fabricated in very small silicon islands where the emitter and base are contacted via the front-wafer, while the collec-tor is contacted directly under the emitter via the back-wafer. Thus, the need for a buried layer and collector plug is eliminated and the collector resistance becomes very low. Moreover, the substrate capacitance is eliminated and the collector-base capacitance is independent of the lateral extrinsic base dimen-sions. All in all this gives a very high flexibility in the design of the devices and integrating other device types, such as high-frequency PNPs, becomes almost

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(a) 1µm Silicon-on-glass process flow:

p_ DIMES 04: B C E B C silicon substrate n+ p+ p+ C _(c) glass substrate B E B adhesive BOX Al/Si (b) glass substrate B E B adhesive Al/Si laser As+implant B E B Al/Si oxide collector implant silicon substrate 400 µm ~10 µm

Figure 1.5: Schematic cross-section of a bulk DIMES-04 NPN and the pro-cess flow of the corresponding silicon-on-glass device. Device dimensions are determined by a 1 µm lithography and a 3 µm metal pitch. (After Nanver et al. [5]).

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10 Introduction

straightforward.

However, from the beginning it became clear that the silicon-on-glass de-vices were prone to a strong electrothermal feedback [36, 37]. The special conditions created in the DIMES-04 NPN silicon-on-glass transistors, i.e. a very small device silicon island with very high thermal resistance and very low collector contact resistance, gave a unique opportunity of studying elec-trothermal behavior of bipolar transistors. The enormous impact that such effects can have on device performance also became obvious. This is treated for the case of high-frequency bipolar transistors in relationship to the available methods of device isolation and cooling.

1.3 Electrothermal limitations on the

cur-rent density of high-frequency bipolar

transistors

To put the electrothermal effects into perspective simple analytical calculations are presented in this section. These demonstrate that electrothermal feedback is becoming a crucial issue for high-frequency silicon bipolar technologies in general.

Thermal resistance in high-frequency BJTs

The thermal resistance of a device is defined as a temperature increase over ambient ∆T for a given dissipated power P :

RT H = ∆T_P . (1.1)

In a first approximation, the thermal resistance RT H of a bulk bipolar transis-tor can be related to the emitter area A_E and the thermal conductivity k_bulk of the bulk material by the simple equation [38]:

RT H = 1

4k_bulk√AE

. (1.2)

The power P dissipated in the device is related to the power density p as P =AEp= AEJCVCE, where JC is the collector current density and VCE the collector-emitter voltage. Thus the temperature increase above ambient ∆T

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1.3 Electrothermal limitations on the current density... 11 f T,max [GHz] ∆ T fTmax [K] A E [ µ m 2 ] Si SiGe JC,fTmax [mA/µm2] 0.1 1 10 100 0 50 100 150 200 250 300 350 400 0 4 8 12 16 20 24 28 32 36 40 0 5 10 15 20 25

Figure 1.6: The emitter area AE, peak cut-off frequency fT,max and ap-proximated temperature increase at fT,max ∆Tf T max versus current density J_{C,f T max} at f_T,max for recently published Si and SiGe transistors.

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12 Introduction is related to JC as: ∆T = R_{T H}P = R_{T H}A_Ep = p √ A_E 4kbulk = JCVCE √ A_E 4kbulk . (1.3)

The present trends for emitter area downscaling and current densities at max-imum cut-off frequency fT,max are displayed in Fig. 1.6, where it is clear that there is an almost linear relationship between the current density JC at fT,max and the f_T,maxitself (the data are collected for transistors published at IEDM, BCTM and in EDL [39–46]). Equation (1.3) is used to calculate ∆T at fT,max from Fig. 1.6. For a constant power density, a reduction in device size would reduce the self-heating. However, due to the trend to increase power density to achieve higher fT, the self-heating increases despite reduction in the device size. In addition, for most modern devices the RT His higher than predicted by such simple formulations, since for example effects of shallow and deep trench isolation, and buried oxide have not been taken into account here [38].

In order to illustrate the effect of substrate modifications on the self-heating, 2D numerical thermal simulations are performed in Femlab [47] and the results are shown in Fig. 1.7. The bulk-silicon technology in A is compared to the bulk-silicon technology with deep trenches in B, silicon-on-insulator te-chnology without and with trenches in C and D respectively, silicon-on-glass technology in E and silicon-on-copper technology in F. It can be seen that as the electrical isolation gets better, the thermal resistance gets undesirably high. The heat transfer is significantly enhanced if the bulk-silicon is replaced by a better thermal conductor like copper, as is done in [48] by Dekker et al. The silicon-on-copper technology is schematically represented in F, where the thermal resistance becomes lower than the bulk-silicon value.

Enhancing the heat transfer to a heat sink is often implemented during the post-processing or packaging, for example by the surface mounting [49,50]. This approach is used in practice to relieve the self-heating in the silicon-on-glass power RF transistors. A technology solution, schematically shown in Fig. 1.8, has been proposed for bipolar devices by Dekker et al. [7]. Compared to the integrated devices from Fig. 1.5, these transistors are large enough to allow the placement of heat spreaders and heat sinks below the active device region. Thus power RF silicon BJTs and high-quality passive components can be integrated with excellent heat sinking through the back-wafer copper interconnects to a thermally conducting printed circuit board (PCB).

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1.3 Electrothermal limitations on the current density... 13 ∆ T/ ∆ T A glass substrate A B C D E F ~ ~ ~ ~ copper substrate ~ ~ ~ ~ 1.0 1.4 1.7 4.1 60.4 0.5 0.1 1 10 100 silicon heat source buried oxide silicon ~ ~ ~ ~ ~ _~ ~ _~ ~ _~ ~ ~ ~ ~ ~ ~

A. bulk-silicon B. bulk-silicon with deep trenches

C. silicon-on-insulator D. silicon-on-insulator with trenches

E. silicon-on-glass F. silicon-on-copper silicon 150 oxide 1.4 copper 400 glass 1 thermal conductivity [W/mK]

Figure 1.7: An illustrative example of numerically simulated temperature in-crease with respect to ambient for different technologies. The temperatures are calculated for the same input power and normalized to ∆T of A. The table in the inset gives bulk values for the thermal conductivity of materials used in the simulations.

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14 Introduction

substrate via

npn

n++ n++ substrate

n-(a)

glass substrate

n++ n++ substrate n-

(b)

10 µm plated Cu

glass substrate

n++

n-(c)

glass substrate

n++ n++

n-(d)

(e)

glass substrate

n++ n++ reflow soldering emitter/base connection collector connection and heat sink

n-printed circuit board

Figure 1.8: Schematic processing sequence for the fabrication of surface mounted RF transistors on glass. (a) Fully processed wafer with via diffu-sions for frontside to backside wafer connection. (b) Wafer glued to a glass substrate. (c) Silicon thinned to 5 µm. (d) Formation of 10-µm-thick cop-per plated contacts. (e) Anisotropic KOH etching of the remaining silicon down toward the field oxide using the copper contacts as etching masks. (f) Soldering of the separated devices to the PCB. (After Dekker [1]).

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1.3 Electrothermal limitations on the current density... 15

Thermal breakdown

However, in integrated bipolar circuits, where heat spreading and heat sinking is very limited, the self-heating becomes critical for the device performance. The electrothermal interaction can lead to thermal instability [51, 52] and temperature-current positive feedback can even result in destructive thermal breakdown [53]. In Fig. 1.9(a) the Gummel plots of the bulk-silicon and silicon-on-glass NPN BJT’s [8] from Fig. 1.5 with AE=20×1 µm2 are shown. In the silicon-on-glass transistor the thermal breakdown (or the thermal runaway) is seen as a sudden increase in the collector and base current even for V_CB=0 V. In a first approximation, the collector current density at the onset of thermal breakdown, JC,crit, can be calculated by [51]:

JC,crit = IC,crit_A E

= VT/AE

|ϕ|V_CER_{T H}− R_Σ, (1.4)

where VT=kT /q (≈26 mV) is the thermal voltage, ϕ the base-emitter voltage temperature coefficient (≈-1 mV/K) and RΣ=RE+re the equivalent electri-cal emitter resistance, including the internal r_e and externally applied R_E resistance terms. The internal resistance re is usually expressed in terms of the specific emitter resistivity res=reAE in Ωµm2, which is a technology pa-rameter. From device measurements, the thermal resistance is determined to be about 10000 K/W and 300 K/W for the silicon-on-glass and bulk-silicon device, respectively. For VCB=2 V and RΣ=3 Ω this gives IC,crit ≈ 1 mA for the silicon-on-glass device and unconditional stability for the bulk-silicon transistor since |ϕ|VCERT H,bulk− RΣ < 0.

JC,crit and gm as function of RΣ

Thermal stability can be improved by increasing resistance RΣ [54]. This is

illustrated in Fig. 1.9(b), in which the Gummel plots of the silicon-on-glass device are shown for different RE’s. Nevertheless, the voltage drop across the emitter series resistance also reduces the transconductance gm:

gm IC =

1

VT + ICRΣ. (1.5)

For most applications a (gm/IC) value of about half the maximum value (for RΣ=0) is still useful. Therefore the quantity:

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16 Introduction 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 0.6 0.7 0.8 0.9 1 1.1

V =2V

CB

I

_C,crit R E=0, re=3 Ω

V =1V

CB

V =0V

CB silicon-on-glass

V

_BE

[V]

I,

I

[A]

CB bulk-silicon (a) 0.70 0.75 0.80 0.85 10-5 10-4 10-3 10-2 VBE[V] I[ A] C _a) b) R E=4 Ω R E=8 R E=16 Ω R E=24 Ω R E=32 Ω R E=100 Ω R E=0 Ω c) d) e) f) g) Ω a,b,c,d,e,f,g I_C,crit V_CB=2 V r_e=3 Ω (b)

Figure 1.9: Measured (a) Gummel plots of a bulk-silicon (dashed lines) and glass devices (solid lines) and (b) Gummel plots of the silicon-on-glass device for several externally added emitter series resistors R_E. Emitter area is 20×1 µm2.

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1.3 Electrothermal limitations on the current density... 17 1 10 20 30 40 0.1 10 100 J_C,max[mA/µm2] (g m /I C ) [1/V] G=(g m/IC)min r sp=2 Ωµm 2 r sp=4 Ωµm 2 r_sp=20 Ωµm2 r_sp=200 Ωµm2 too low high enough

Figure 1.10: Transconductance versus collector current density for different values of specific emitter resistance. External emitter series resistance RE is neglected. JC,max is highlighted by the filled circles.

can be introduced as a lower limit on the transconductance [55]. The maximum current density at which (gm/IC) is above or equal to 20 V−1 for a given RΣ,

is evaluated from (1.5) as:

JC,max= 1 − V_A TG

ERΣG. (1.7)

From Fig. 1.10 it is clear that as the series resistance gets higher, the JC,max gets lower. Therefore, for operation at very high current densities, which is typical for modern high-frequency devices, the series resistance must be minimized [56]. For example, to reach the most-advanced value for fT,max of 350 GHz, the J_{C,f T max} needs to be as high as 20 mA/µm2_{. Even in the}

absence of any external emitter resistance, i.e. for RE=0, such a high current density will limit (gm/IC) to below 20 V−1 if the technology advances [57] do not allow res to be reduced to 1.2 Ωµm2. For such a low value of res, the negative feedback in the emitter is almost completely suppressed, which directly means that the electrothermal feedback is significantly increased.

In the following it is assumed that the external emitter resistance RE is negligible, thus RΣ=re=res/AE.

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18 Introduction

Analytical formulation of the critical emitter area

According to (1.4), the thermal instability occurs only if |ϕ|V_CER_{T H}−R_Σ > 0. Therefore, with the expression for RT H given by (1.2), the maximum emitter area AE,crit for which the device is unconditionally thermally stable for given r_es, k_bulk and V_CE is expressed by:

AE,crit= _ϕ₂16_V₂ CE

k_bulk2 r2_es. (1.8)

This means that a device with A_E ≤ A_E,crit cannot be driven into thermal breakdown. Otherwise, for AE > AE,crit the thermal breakdown occurs for JC,crit defined by (1.4).

The critical area expressed by (1.8) is plotted in Fig. 1.11(a) versus the thermal conductivity of the substrate kbulk, where res is set to 10 Ωµm2, VCE to 2 V and ϕ to -1 mV/K. A device with the emitter area smaller than 9 µm2

is unconditionally stable for bulk-silicon technology. On the other hand, if a device is completely surrounded by glass, the critical area is almost four to five orders of magnitude smaller. The figure shows that a small device, which is theoretically not prone to thermal breakdown if made in bulk-silicon technology, can experience instability problems if made in the trench-isolated, SOI or especially silicon-on-glass technology. Also, replacing the silicon wafer with a more thermally conducting substrate like copper, lowers the thermal resistance and can be beneficial for thermal stability of large transistors.

In Fig. 1.11(b) AE,crit is plotted as a function of res for devices sur-rounded by either glass or silicon. For the measured silicon-on-glass and bulk-silicon devices from Fig. 1.9(a) the res is 60 Ωµm2, which corresponds to AE,crit(silicon)=324 µm2 and AE,crit(glass)=0.016 µm2. Therefore, the device with A_E=20 µm2 _{is unconditionally stable in bulk-silicon technology,}

while it suffers from thermal breakdown at very low current levels if made in silicon-on-glass technology. For the most advanced device from Fig. 1.6 with A_E=0.3 µm2_{, f}

T,max=350 GHz, JC,f T max=20 mA/µm2 and res of 1.2 Ωµm2, (1.4) and (1.8) yield JC,crit(silicon)=41.5 mA/µm2 and AE,crit(silicon)=0.13 µm2_.

Optimum specific emitter resistivity and optimum current den-sity

From (1.4) and (1.7) it has been shown that while lowering the emitter resis-tance increases JC,max, it will decrease JC,crit. Therefore, there is an res for

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1.3 Electrothermal limitations on the current density... 19 102 101 100 10-1 Si 10-2 10-3 10-4 10-6 10-5 10-4 A E [ µ m 2 ] k sub [W/µmK] V CE=2 V Cu A E,crit glass

SOG, SOI, deep & shallow trench

stability region conditiona ly instable region r es=10 Ω µm 2 ϕ=-1mV/K (a) r_es [Ω µm2] 10-1 10-2 10-3 10-4 10-1 100 silicon trench SOI SOG glass 101 102 103 102 101 100 A E [ µ m 2 ] AE,crit AE,crit _{stability re} gion stability re gion conditiona ly instable region conditiona ly instable region V CE=2 V ϕ=-1mV/K (b)

Figure 1.11: Maximum emitter area for which a bipolar transistor is thermally stable versus (a) thermal conductivity of the substrate for a fixed specific emit-ter resistivity and (b) specific emitemit-ter resistivity for silicon and glass substrate materials.

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20 Introduction

which JC,max=JC,crit. This defines an optimum value for the specific emit-ter resistivity res,opt, which optimizes the allowable current density JC,opt of a bipolar transistor for given AE, VCE and RT H:

res,opt= AEVCERT Hϕ(1 − GVT), (1.9) and

J_C,opt= 1

A_EGϕV_CER_{T H}. (1.10)

The JC,opt is the optimum current density of a single-finger high-frequency bipolar transistor made in a given technology node. Keeping emitter area constant while reducing the specific emitter resistivity below res,optis not ben-eficial for the speed of BJTs: for res ≤ res,opt the current is limited by the thermal instability to JC,crit ≤ JC,opt, while for res ≥ res,opt the current is limited by (gm/IC)min to JC,max≤ JC,opt.

In Fig. 1.12 JC-res characteristics defined by (1.4) and (1.7) are plotted versus r_es. For the bulk-silicon device with A_E=0.3 µm2_{, (1.9) and (1.10)}

yield res,opt=1 Ωµm2 and JC,opt=27.5 mA/µm2. The 350 GHz transistor has parameters approaching these values.

Multifinger devices

In multifinger transistors, the mutual thermal coupling resistance RM be-tween the neighboring device fingers is very important for the thermal stabil-ity. Moreover, in such devices, the JC,crit depends on the type of biasing [58]. If the thermal interaction between more distant fingers is negligible, (1.10) can be rewritten to include the effect of R_M:

JC,opt= _A 1

EGϕVCE(RT H± RM), (1.11) where + and − corresponds to voltage-controlled and current-controlled bias-ing, respectively.

The mutual thermal coupling RM from (1.11) can be approximated by a point-to-point thermal resistance [38] R_M = 1/(2πk_subd), where d is the pitch between the neighboring fingers. As an example, single-finger transistors with AE of 20×1 µm2and 0.3×1 µm2are compared to two-finger devices with AE’s equal to 2×(1×10) µm2 _{and 2×(1×0.15) µm}2_{, respectively. The optimum}

current densities are calculated versus the finger pitch for both the voltage-and current-controlled biasing, voltage-and are compared to JC,optof the corresponding

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1.3 Electrothermal limitations on the current density... 21

J

[mA/

µ

m

2 ]

J

C,crit

r

_es

[Ω µm

2

]

r

_es,opt 103 102 101 100 10-1 10-2 10-3 10-2 10-1 100 101 102 103 silicon glass

J

C,max 0.01 µm2 0.01 µm2 0.3 µm2 0.3 µm2 20 µm2 20 µm2

J

_C,opt

Figure 1.12: The current densities J_C,max(dashed line) and J_C,crit (solid lines) versus specific emitter resistivity for three different emitter areas, and for silicon or glass substrates.

single-finger transistor in Fig. 1.13. If a current-controlled biasing is used, splitting a single-finger transistor into a two-finger device results in an increase in the JC,opt regardless of the value of the pitch. For this type of biasing, bringing fingers closer to each other results in a significant increase of J_C,opt, and is also beneficial for reducing the device area. On the other hand, if a voltage-controlled biasing is used, the JC,opt increases for a large finger pitch. Thus, reducing the distance between the fingers in order to decrease the total area of the device, can result in a decrease of JC,opt, which can eventually become lower than that of the single-finger device.

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22 Introduction J C,opt [ mA/ µ m 2 ] 104 103 102 101 100 10-1 10-2 10-2 10-1 100 101 102 d [µm] voltage control current control A_E=10 µm2 A_E=20 µm2 A_E=0.15 µm2 A_E=0.3 µm2 singlefinger twofinger

Figure 1.13: Calculated optimum current density of two-finger (solid-lines) and single-finger (dotted-lines) devices. The effect of the finger pitch d on J_C,opt is plotted for two-finger devices in both voltage- and current-controlled biasing conditions.

1.4 This thesis

Motivation and objectives

From the above analysis, it becomes clear that the speed requirements of ad-vanced bipolar transistors is driving the emitter dimensions and resistance into a region where the very high power densities and the significant thermal resistances will lead to significant device self-heating and detrimental elec-trothermal feedback. These thermal effects set a maximum current for the safe operating region of the device, which can be extremely low for devices isolated on all sides by dielectrics. For more conventional bulk-silicon devices the maximum current is orders of magnitude higher but the presented analysis predicts that the limit on the current density of high-frequency bipolar devices will, before too long, be set by electrothermal effects.

For the silicon-on-glass devices studied in this thesis, the electro-thermal effects are imminent. Particularly for the bipolar transistors, the threat of

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1.4 This thesis 23

thermal breakdown is an obstacle for designing circuits even for low-power RF applications. Therefore, although the main goal of the silicon-on-glass process research is to use the unique features of such a process to create new device concepts and enhance the performance of existing active and passive devices, it is of paramount importance that the thermal behavior is understood and brought under control. In this thesis, work was focused on the development of a novel silicon-on-glass structure, a back-wafer contacted VDMOS transistor, as well as on thorough investigations of the electrothermal behavior of both this device and silicon-on-glass NPN transistors.

The silicon-on-glass VDMOST was designed to profit from the fact that the device can be fabricated in a small silicon island with contacts to both the front- and back-wafer side. In this manner it was possible to combine attrac-tive features of both bulk-silicon LDMOSFETs and bulk-silicon VDMOSFETs in a device with performance particularly well-suited for highly-linear RF ap-plications. The resulting structure is shown in Fig. 1.14. The fabrication of this device was undertaken in a collaboration between DIMES, Philips Semi-conductors Nijmegen and Philips Research Eindhoven, where the substrate transfer and back-wafer processing was performed at DIMES, the active sili-con device regions were processed in the LDMOS production line in Nijmegen and surface mounting was performed in Eindhoven.

The electrothermal investigations of this VDMOS device and the bipolar NPNs were mainly driven by the desire to understand how the devices could be electrothermally stabilized. Methods were sought by which the electrical design and biasing promoted electrothermal stability, as well as methods by which the thermal resistance of the devices was physically reduced by adding heat spreaders and heat sinks. The results are reported in the following chap-ters, the organization of which is given below.

Outline

The core of the thesis is formed by several journal papers and conference contributions, some of which are reprinted in their original form.

In Chapter 2, the silicon-on-glass integrated NPN BJTs from Fig. 1.5 are electrothermally characterized. The devices are studied with respect to differ-ent heat spreader designs by means of electrical measuremdiffer-ents and nematic liquid crystal imaging. In Chapter 3 a very detailed theoretical and experi-mental investigation of thermal breakdown in single-finger bipolar transistors is presented. This effect is analyzed particularly with respect to thermal resis-tance and the individual contribution of each electrical series resisresis-tance term.

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24 Introduction oxide source Cu Cu Cu dummy gate Cu p++ p++ p++ p++ n++ p++ p++ glass source gate gate drain gate plug adhesive BCB source n-epi p- p-n++ source gate PCB solder ~ ~ ~ ~ n++ trench 400 µm ~10 µm ~5 µm ~10 µm ~10 µm <1 µm

Figure 1.14: Schematic cross section of the surface mounted silicon-on-glass VDMOSFET.

In Chapter 4 thermal instability in multifinger BJTs is discussed, and for the first time this effect is theoretically investigated by simultaneously taking into account the self-heating and mutual thermal coupling resistance as well as the temperature dependence of the current gain. The thermal instability is ana-lyzed for different technologies: silicon and silicon-germanium base technolo-gies are compared for several substrate modifications. Chapter 5 introduces a novel measurement method for extraction and modelling of the self-heating and mutual thermal coupling impedance of bipolar transistors. Measurements of the silicon-on-glass test structures are used as a case study, and the results are modelled for the purpose of large-signal RF characterization.

The research on the silicon-on-glass VDMOSFETs is thoroughly treated in Chapters 6 and 7. Chapter 6 discusses the device concept in relationship to the evolution from standard MOSFETs. The processing of the device is described with focus on the novel post-processing steps, such as the back-wafer trench etching and two level of copper plating. Chapter 7 presents electrical and electrothermal characteristics of the devices, based both on experimental and

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1.4 This thesis 25

numerical results. In particular, effects of the dummy-gate electrode and the thermal resistance on the device overall performance are investigated. Finally, Chapter 8 gives the main conclusions and recommendations for the future work.

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Chapter 2 Electrothermal

characterization of

silicon-on-glass bipolar

transistors

In this chapter the electrothermal consequences of implementing a bulk-silicon bipolar NPN process in the silicon-on-glass [3,5] substrate transfer technology are examined. The good electrical isolation of the silicon-on-glass NPN’s with low collector-base capacitance, collector resistance and substrate capacitance, also provides an extremely good thermal isolation and the electrothermal cou-pling in these devices is forbiddingly strong. They have thermal resistance values up to 100 times higher than that of corresponding bulk-silicon devices, so self-heating effects and thermal breakdown appear at power densities much lower than any ever witnessed before in silicon. Here the devices are elec-trothermally characterized in relationship to different heat-spreader designs by electrical measurement and nematic liquid crystal imaging. Accurate values of the temperature at thermal breakdown and thermal resistance are extracted from current-controlled Gummel plot measurements.

2.1 Introduction

The processing flowchart of a back-wafer contacted silicon-on-glass integrated bipolar process is schematically presented in Fig. 1.5. The main fabrication

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28 Electrothermal characterization of silicon-on-glass BJTs

Table 2.1: Device parameters.

NPN processed in bulk Si silicon-on-glass Device area [µm2_] _21×35 _8×21 Emitter area [µm2_] _20×1 _20×1 hF E(VBE = 0.8 V) 100 100 VA [V] 12 12 re [Ω] 3 3 rb [Ω] 60 60 rc [Ω] 20 3 BVCEO [V] 5 5 Cbc(VCB = 0 V) [fF] 75 30 Ceb(VCB = 0 V) [fF] 88 88 RT H [K/W] ∼ 300 ∼ 10500

issues are detailed in Chapter 1, while in this chapter the fabricated transistors are experimentally characterized.

A schematic cross section and microscope images of a silicon-on-glass NPN bipolar transistor with an emitter area of 20×1 µm2_{, placed in a small}

(0.84×10×23 µm3) silicon island, are shown in Figs. 2.1 and 2.2, respectively. This transistor has a base contact on each side of the emitter. Fig. 2.2(a) is focused on the front-wafer metal, i.e. the metal on the emitter side of the device, while Fig. 2.2(b) is focused on the back-wafer metal, i.e. the metal on the collector side of the device. In Fig. 2.1 the silicon-on-glass structure is also compared to the corresponding DIMES-04 bulk-silicon transistor.

The NPNs are fabricated in 1 µm lithography and the lateral dimensions are determined by a 3 µm metal pitch. The bulk-silicon transistor has a lightly doped n-epi around the collector implant. Thus, for a 20×1 µm2_{emitter area,}

the total collector-base area in the bulk-silicon device is 21×7 µm2_{. On the}

other hand, in the silicon-on-glass device the region underneath the base is p-doped. Therefore, the collector implant area determines the size of the collector-base region, which is in the present devices 21×2 µm2_{. In addition,}

in the silicon-on-glass device the buried n+ _{layer is eliminated because the}

collector is directly contacted via the back-wafer.

In Table 2.1 the main device parameters of the bulk and silicon-on-glass device are compared. Electrically, the main advantages of glass processing

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2.1 Introduction 29

C

glass substrate

B

E

B

adhesive 10 µm 0.84 µm p+ p+ p+ n n- n-n+ n n+ p p p n+ 400 µm ~10 µm 500 µm

Silicon-on-glass:

Bulk-silicon:

B

C

E

B

C

silicon substrate p+ p+ p-n+

Figure 2.1: Schematic cross sections of DIMES-04 silicon-on-glass and bulk-silicon NPN BJTs.

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(a)

(b)

Figure 2.2: Microscope images of the silicon-on-glass NPN (A_E = 20×1 µm2₎

bipolar transistor in a small (10×23 µm2) silicon island. (a) The focus is on the emitter-base front-wafer metallization. (b) The focus is on the collector and bondpads back-wafer metallization.

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2.2 Electrical measurement of self-heating 31

for NPNs lie in a large reduction of the collector resistance and the collector-base capacitance. This has clear advantages for the fmax of the devices. The bulk NPN has an fT and fmax of 25 GHz (VCB =3 V). The exact design of the collector-base region in the silicon-on-glass devices will also influence the fT. However, characterization and optimization of the devices with respect to the high-frequency parameters has been impeded by the strong electrothermal coupling at high currents. In fact, aside from the first and second metalliza-tion and the thin layer of silicon, in which the active device is fabricated, the silicon-on-glass transistors are surrounded by dielectric layers with very low thermal conductivity. This gives rise to the thermal resistance. Therefore, understanding and controlling self-heating effects will be decisive for the via-bility of integrated silicon-on-glass circuits. In this chapter, the device design in relationship to the electrothermal behavior is thoroughly investigated.

2.2 Electrical measurement of self-heating

Self-heating during electrical measurement of silicon-on-glass NPNs is readily observed. Two factors are essentially responsible for the high thermal resis-tance:

1) the silicon islands in which devices are formed are small and almost completely surrounded by oxide and glass, which are poor thermal con-ductors. Silicon itself has a good thermal conductivity. Therefore, nor-mally low-power transistors in bulk silicon are not seriously affected by the heat they dissipate themselves;

2) devices are composed of thin layers of various materials such as silicon, silicon dioxide and nitride. The thermal conductivity of a thin film is lower than that of the corresponding bulk material due to phonon scattering on imperfections and phonon-boundary scattering [59]. All electrical measurements were performed with a HP4156B parameter analyzer and a Cascade probe station equipped with a thermal chuck. Typical transistor characteristics are shown in Figs. 2.3 and 2.4, where the charac-teristics of a bulk-silicon device are compared to the corresponding minimum dimension silicon-on-glass transistor. During these measurements the thermal chuck temperature was kept constant at 27◦_{C. In general, in silicon devices} both the base and collector current increase with temperature and the current gain also increases due to bandgap narrowing in the highly-doped emitter. In

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32 Electrothermal characterization of silicon-on-glass BJTs 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 0.6 0.7 0.8 0.9 1 1.1

V =2V

CB

V =1V

CB

V =0V

CB bulk-Si silicon-on-glass

V

_BE

[V]

I,

I

[A]

CB (a) 1 2 3 4 5 0 0.5 1 1.5 2 2.5 3 3.5 4 ∆I B=5 µA

V

_CE

[V]

I

[mA]

C 0 (b)

Figure 2.3: (a) Gummel plots and (b) output characteristics and of a bulk-Si (dashed lines) and silicon-on-glass device (solid lines). Emitter area is AE = 20 × 1 µm2_.

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2.2 Electrical measurement of self-heating 33 -0.5 0 0.5 1.0 1.5 0 1 2 3 4 5

I

B

[A

]

V

_CB

[V]

BV_CEO-V_BE 1: V =0.68VBE 1 2 3 4 5 6 7 2: V =0.70VBE 3: V =0.72VBE 4: V =0.73VBE 5: V =0.733VBE 6: V =0.735VBE 7: V =0.74VBE

Figure 2.4: IB-VCBcharacteristics of silicon-on-glass device (solid lines). Emit-ter area is AE = 20 × 1 µm2.

both the Gummel plots and output characteristics shown in Fig. 2.3(a) and (b) an excessive increase in collector current is observed in the silicon-on-glass device as compared to the bulk device. In the Gummel plot for VCB =0 V, thermal breakdown with catastrophic increase of both the collector and base current is observed at the low VBE ≈ 0.8 V corresponding to a power of only ≈ 2 mW. In the output characteristics both self-heating and avalanching increase the collector current. By looking at the I_B-V_CB characteristics of the silicon-on-glass device shown in Fig. 2.4, the breakdown voltage BVCEO associated with avalanching can be determined from the IB =0 intersection point for low V_BE values. For V_BE values around 0.72 V, self-heating is already producing a noticeable increase in IB and for VBE ≈ 0.733 V the IB no longer decreases to zero.

Although the self-heating effects and thermal breakdown are clearly de-tected in the above measurements, these do not provide a good technique for quantifying the conditions at thermal breakdown. On the other hand, in current-controlled I_C-V_BE characteristics the thermal breakdown is detected as the snap-back, or turn-over, or fly-back point [51, 54, 60]. This point is seen in Fig. 2.5 where the biasing circuits for both the base-emitter

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voltage-34 Electrothermal characterization of silicon-on-glass BJTs 10-7 10-6 10-5 10-4 10-3 10-2 0.74 0.75 0.76 0.77 0.78 I I I B B C ,IC [A ] V_BE[V] (a) (b) C B E + -VCB IE C B E + -VCB VBE +

-(a)

(b)

V =1 V_CB

Figure 2.5: Measurement circuits and Gummel plot measurements for (a) emitter current-controlled method (solid line) and (b) base-emitter voltage-controlled method (dashed line). Emitter area is AE = 20 × 1 µm2.

and emitter current-controlled measurements in common-base configuration are given together with the corresponding I_C-V_BE measured characteristics. In the current-controlled measurement the self-heating lowers the VBE cor-responding to a given collector current and above the critical temperature a negative differential resistance is observed. In Chapter 3 the fly-back point is examined theoretically and it is shown that the critical power Pcrit deter-mined from the biasing conditions at this point can be used to calculate both the critical temperature rise ∆Tcrit necessary for thermal breakdown and the thermal resistance RT H of the device. Applying the derived expressions to the device measured in Fig. 2.5 yields ∆Tcrit = 19.0 K and RT H = 10440 K/W. In Fig. 2.6(a) the current at the fly-back point is seen to decrease as the collector-base voltage increases.

The emitter and collector series resistances are both very low in the silicon-on-glass transistor characterized in Figs. 2.3, 2.4 and 2.5. This fact, and not only the high thermal resistance, is important for the clarity with which the fly-back point is detected in the current-controlled Gummel plots. Ballasting resistors have a stabilizing effect on the electrothermal behavior as seen in the example in Fig. 2.6(b) where the effect of a 20-Ω series resistance added to either the emitter or collector terminal is shown. The collector resistance

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2.2 Electrical measurement of self-heating 35 10-8 10-7 10-6 10-5 10-4 10-3 10-2 0.66 0.68 0.7 0.72 0.74 0.76 0.78 0.8 0.82 0.84

I

I I B B C

,I

C

[A]

V

_BE

[V]

V =2VCB V =1VCB V =0VCB (a) 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 0.65 0.7 0.75 0.8 0.85 0.9

I

B

,I

C

[A]

V

_BE

[V]

V =0.2 VCB R =20 ΩE R =20 ΩC V sweepBE R ,CRE=0Ω I I B C I sweepE (b)

Figure 2.6: (a) Current-controlled Gummel plots measured without ballasting resistors for several VCB values. (b) Voltage- and current-controlled Gummel plots measured with and without a 20-Ω emitter-ballasting or collector resistor. Emitter area is AE = 20 × 1 µm2.

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only causes a very small increase of the position of the fly-back point but does, for high enough currents, deter the negative differential behavior in the current-controlled Gummel plot and correspondingly the uncontrolled current rise in the voltage-controlled measurement is tempered. Emitter ballasting eliminates the fly-back point and is thus very effective in preventing ther-mal breakdown. However, for RF applications such resistors reduce device transconductance, fT, fmax, and increase input and output resistances [61]. The choice of ballasting resistors is therefore not trivial and implies device performance trade-offs. The analytical formulation of the thermal breakdown condition given in Chapter 3 provides a handsome tool for evaluating the way in which series resistances influence the electrothermal characteristics.

2.3 The effect of device surroundings on

heat spreading

To electrothermally stabilize the silicon-on-glass NPNs the thermal resistance of the devices must be significantly reduced. In large discrete silicon-on-glass NPNs [7, 62] and power MOSFETs (see Chapters 6 and 7) this has been achieved on the packaging level by placing a large metallic heat sink directly on the collector or source contact. For the present low-power devices, such an approach would be in conflict with the aim for low collector-base capaci-tance and negligible substrate capacicapaci-tance in a circuit situation. Methods of spreading the heat away from the active device region to a convenient place for heat sinking are therefore preferable. Electrical interconnect metal such as that shown in Fig. 2.2, is not effective in doing this because the 2-µm-narrow metal tracks have a thermal resistance of approximately 2000 K/W per mi-cron length. Other options for achieving more effective on-chip heat spreading within the present two metal processing scheme are examined in the following. A series of devices were designed with different surroundings as shown schematically in Fig. 2.7. While the basic device (a) is surrounded completely by trenches filled with thermally isolating materials, the devices (b), (c) and (g) have neighboring silicon regions, and devices (d), (e) and (f) have neighbor-ing metal (Al) regions. From the correspondneighbor-ing current-controlled Gummel plots, the junction temperature rise at the thermal breakdown point and ther-mal resistance are calculated for each device, and the results are presented in Table 2.2. Device (g) without trench isolation is the most effectively cooled by the direct contact to surrounding silicon. Insertion of trench isolation increases

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2.3 The effect of device surroundings on heat spreading 37 C (a) (b) (d) (c) (e) (f) (g) C x x=8.5 µm x=3.5 µm x C C B B B B E E E E B B B B adhesive adhesive adhesive adhesive glass substrate glass substrate glass substrate glass substrate C B E B adhesive glass substrate x=8.5 µm x=3.5 µm

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Table 2.2: Extracted parameters for the devices surrounded by different heat spreaders.

Device Pcrit ∆Tcrit RT H

[mW] [K] [K/W] (a) 1.82 19.00 10440 (b) 1.93 19.15 9920 (c) 2.09 19.37 9270 (d) 1.93 19.15 9920 (e) 2.12 19.41 9150 (f) 3.97 21.72 5470 (g) 6.73 24.85 3690

the thermal resistance even if the trench sidewalls are covered with metal as in device (f). Nevertheless, partial substitution of poor thermally conducting material in the close proximity of the active device with silicon or aluminium has a beneficial effect on RT H. For devices (b) to (e) the distance x to either a neighboring silicon or metal heat spreader (30×80 µm2_{) is varied from 3.5 µm}

to 8.5 µm. The efficiency of a heat spreader decreases with increasing distance x. It is noteworthy that although aluminium has twice the thermal conduc-tivity of bulk silicon, replacing silicon with aluminium (compare (b) and (d), (c) and (e)) is advantageous only when the heat spreader is close enough to the active device region. Although the reduction of RT H is not significant (a mere 12% difference between devices (a) and (e)), it has been achieved solely with the very limited quantity of material available in the standard two metal process. The more effective methods of (f) and (g) where large areas of ther-mally conducting material are added directly to the base contact are seen to give an RT H lowering of about 50 and 65%, respectively. These methods do not increase the collector-base capacitance, but introducing large electrically conducting regions to the device terminals may affect RF device and circuit performance.

The heat spreading in such silicon-on-glass NPNs has been visualized by using nematic liquid crystal (NLC) temperature mapping [63,64] whereby the self-heating process during device operation can be monitored. Nematic liq-uid crystal thermal imaging is performed at Philips Research Eindhoven with Dick de Mooij and Victor Zieren. With this method a map of the

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tempera-2.3 The effect of device surroundings on heat spreading 39 both front-and back-wafer metal back-wafer metal glass silicon island front-wafer metal (a1) (a2) (a3) (b1) (b2) (b3)

Figure 2.8: Nematic liquid crystal images of a 2×(20×1-µm2_{) emitter device}

in a 0.84×18×25-µm3 _{silicon island, with and without large aluminium heat}

spreaders connected to the base as shown schematically in (b1) and (a1), respectively. The hot-chuck temperature is 46◦_{C and clearing point is 56.5}◦_C. (a2) and (b2) show dark area for P = 2.2 mW. (a3) and (b3) show isothermal lines for power levels P = [1.75, 2.2, 2.65, 3.5] mW.

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ture rise all over the device and its surroundings can be generated. A NLC material with a clearing point TC = 56.5◦C is used. To facilitate the mea-surements the wafer is placed on a thermal chuck, the device under test is covered with a thin layer of NLC and subsequently biased. Areas with a tem-perature above the clearing point appear as dark regions when viewed under a microscope using crossed polarizer and analyzer. The method has an ex-cellent 0.1◦_{C absolute temperature accuracy and a spatial resolution of about} 1 µm. Devices with three base and two emitter contacts, with an emitter area of 2×(20×1 µm2_{) in a 0.84×18×25-µm}3 _{silicon island, were examined.}

An example of the results is given in Fig. 2.8. The device in Fig. 2.8(a1) corresponds to one represented in Fig. 2.7(a), while device from Fig. 2.8(b1) corresponds to the one in Fig. 2.7(f). To obtain the images of Figs. 2.8(a2), (a3), (b2) and (b3) the hot chuck temperature is set at 46◦_{C. This implies that} ∆T = 10.5◦_{C isothermal curves are detected as the boarders of dark “hot”} ar-eas as shown in Figs. 2.8(a2) and (b2). The device is biased in a common-base configuration where only emitter E2 is contacted. The input power is varied

in steps and each corresponding isothermal curve is mapped in Figs. 2.8(a3) and (b3). The curves are slightly asymmetric because only the lower emitter finger is biased. Moreover, the probe needles contacting the bondpads E2, B and C act as heat sinks and contribute to this asymmetry. This experiment clearly shows the effectiveness of on-wafer heat spreaders and demonstrates the utilization of NLC temperature mapping for studying heat spreading in micron-scale semiconductor devices.

In an integrated-circuit environment the individual device will be sur-rounded by other devices and metal tracks in varying patterns. The influence of such changes in the surroundings has been studied by considering chains of seven devices. The design of the middle device with the two neighboring devices is shown schematically in Fig. 2.9 for three different isolation schemes. Each set of seven devices is placed in a trenched island while the region between the individual devices is: 2.9(a) trench isolated, 2.9(b) filled with silicon and 2.9(c) filled with aluminum. In the corresponding current-controlled Gummel plots the fly-back point is sensitive to the position of the device as well as to the isolation scheme. In Fig. 2.10, the fly-back point of each middle device is compared to that of the device 2.7(g). Although the silicon island of 2.9(b) is quite large, the thermal resistance is higher than that of 2.7(g), which has no trenching at all. In 2.9(c) the silicon between the devices is replaced by a smaller amount of aluminium. This configuration does, however, have a slightly lower thermal resistance, showing again the large benefits of materials

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2.3 The effect of device surroundings on heat spreading 41 C C C B B B E E E B B B adhesive adhesive adhesive glass substrate glass substrate glass substrate

(a)

(c)

(b)

Figure 2.9: Schematic of the middle device and the two neighboring devices in a chain of seven devices, for three different isolation schemes.

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42 Electrothermal characterization of silicon-on-glass BJTs 10-4 10-3 10-2 0.76 0.78 0.8 0.82 0.84

I

C

[A]

V

_BE

[V]

Fig. 2.7 (g) Fig. 2.9 (a) Fig. 2.9 (b) Fig. 2.9 (c)

Figure 2.10: Emitter-current controlled IC-VBE measurement of the device from Fig. 2.7(g) and the middle device in device chains 2.9(a)-2.9(c). Emitter area is AE = 20 × 1 µm2.

with high thermal conductivity.

The effects of the size of the silicon island, emitter area and trench width have also been studied and compared by means of electrical measurements, numerical simulations and analytical modelling. The results are summarized in [65]where it is shown that the developed numerical simulation procedure and analytical model can be very helpful in predicting and optimizing thermal performance of silicon-on-glass devices.

2.4 Conclusions

In this chapter, low-power, back-wafer contacted silicon-on-glass NPNs have been electrothermally characterized. Electrically, these devices exhibit the same quality as the corresponding bulk devices and their performance is en-hanced by a reduction of the resistive and capacitive parasitics. However, very high thermal resistance values impose serious limitations on the current density and, thus, high-frequency performance is restrained by

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electrother-2.4 Conclusions 43

mal feedback. In the silicon-on-glass devices the self-heating is so strong that the thermal breakdown point moves to very low power levels. It is read-ily detected even for VCB=0 V as a fly-back point in the current-controlled Gummel plot. By inserting this critical power in the analytical formulation developed in Chapter 3, very accurate values for the thermal resistance have been determined for a number of device designs. Different device isolation and metallization schemes have been designed and investigated. Even the slight-est modifications, such as varying the distance to the adjacent device, have been accurately discerned and translated into the thermal resistance values. The benefits of replacing silicon with a material that has higher thermal con-ductivity, in this case aluminium, were apparent. However, the results show that sufficient heat spreading can only be achieved by directly contacting the active device silicon to large areas of material with high thermal conductiv-ity. The thermal resistance of the conventional narrow metal tracks is too high and is unlikely that connecting these tracks to a heat sink outside the main circuit area will be enough to thermally stabilize even a low-current cir-cuit. If the electrical isolation is not to be deteriorated, dielectric layers with high thermal conductivity are imperative for heat spreading. Therefore highly thermally conducting dielectrics (e.g. AlN, SiC and diamond) are needed and investigating possibilities of integration of such materials in the silicon pro-cessing is now in progress at DIMES. The first experiments with AlN give very promising results.

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Chapter 3 Analysis of thermal

breakdown in single-finger

bipolar transistors

In this chapter, analytical expressions for the electrothermal parameters gov-erning thermal instability in single-finger bipolar transistors, i.e. thermal re-sistance RT H, critical temperature Tcrit and critical current JC,crit, are es-tablished and verified by measurements on silicon-on-glass bipolar NPNs. A minimum junction temperature increase above ambient due to self-heating that can cause thermal breakdown is identified and verified to be as low as 10-20◦_{C. The role of internal and external series resistances and the thermal} resistance for self-heating becomes clear because they are explicitly included in the expressions for T_crit and J_C,crit. The use of the derived expressions for determining the safe-operating-area of a device and for extracting the thermal resistance is demonstrated.

3.1 Introduction

Observations of thermal instability in bipolar transistors date back even to the late ’50s [66–68]. Several efforts have been devoted towards determin-ing the conditions that lead to thermal instability. Some detailed theories at carrier level have been proposed [69–71], in which the authors focus on evaluation of the local hot-spot temperature that triggers thermal breakdown in single-emitter devices. Such mechanisms are usually related to operation

Electrothermal Behavior of High-Frequency Silicon-On-Glass Transistors

Electrothermal Behavior of

High-Frequency

Silicon-On-Glass Transistors

Electrothermal Behavior of

High-Frequency Silicon-On-Glass

Transistors

PROEFSCHRIFT

Nebojˇsa NENADOVI ´

C

Contents

Chapter 1

Introduction

1.1

RF circuit integration

1.2

Substrate transfer silicon-on-glass

te-chnology

bondpad

silicon

circuit

adhesive

glass substrate

BOX

(a)

BOX

(b)

UV curing

(c)

glass substrate

(d)

glass substrate

bond area

silicon

oxide

glass

metal

bondpad

spiral inductor

silicon substrate

circuit

(a)

(b)

(c)

(d)

(e)

glass substrate

silicon substrate

glass substrate

glass substrate

glass substrate

active devices

bondpad high Q inductor

1.3

Electrothermal limitations on the

cur-rent density of high-frequency bipolar

transistors

substrate via

npn

n-(a)

glass substrate

(b)

glass substrate

n-(c)

glass substrate

n-(d)

(e)

glass substrate

n-printed circuit board

V =2V

I

V =1V

V =0V

V

[V]

I,

I

[A]

J

[mA/