Pinout and Signal Descriptions
Section 12. Clock Functions
12.12 Clock Function Registers
All register addresses shown reflect the reset state. Registers may be mapped to any 2K byte space.
RTIE — Real Time Interrupt Enable Read and write anytime.
0 = Interrupt requests from RTI are disabled.
1 = Interrupt will be requested whenever RTIF is set.
RSWAI — RTI and COP Stop While in Wait
Write once in normal modes, anytime in special modes. Read anytime.
0 = Allows the RTI and COP to continue running in wait.
1 = Disables both the RTI and COP whenever the part goes into Wait.
RSBCK — RTI and COP Stop While in Background Debug Mode Write once in normal modes, anytime in special modes. Read anytime.
0 = Allows the RTI and COP to continue running while in background mode.
1 = Disables both the RTI and COP when the part is in background mode. This is useful for emulation.
RTBYP — Real Time Interrupt Divider Chain Bypass
Write not allowed in normal modes, anytime in special modes. Read anytime.
0 = Divider chain functions normally.
1 = Divider chain is bypassed, allows faster testing (the divider chain is normally XCLK divided by 213, when bypassed becomes XCLK divided by 4).
Bit 7 6 5 4 3 2 1 Bit 0
RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0
RESET: 0 0 0 0 0 0 0 0
RTICTL — Real-Time Interrupt Control Register $0014
RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select Read and write anytime.
Rate select for real-time interrupt. The clock used for this module is the XCLK.
RTIF — Real Time Interrupt Flag
This bit is cleared automatically by a write to this register with this bit set.
0 = Time-out has not yet occurred.
1 = Set when the time-out period is met.
Table 12-4. Real Time Interrupt Rates
RTR2 RTR1 RTR0 Divide X By: Time-Out Period X = 125 KHz
Time-Out Period X = 500 KHz
Time-Out Period X = 2.0 MHz
Time-Out Period X = 8.0 MHz
0 0 0 OFF OFF OFF OFF OFF
0 0 1 213 65.536 ms 16.384 ms 4.096 ms 1.024 ms
0 1 0 214 131.72 ms 32.768 ms 8.196 ms 2.048 ms
0 1 1 215 263.44 ms 65.536 ms 16.384 ms 4.096 ms
1 0 0 216 526.88 ms 131.72 ms 32.768 ms 8.196 ms
1 0 1 217 1.05 s 263.44 ms 65.536 ms 16.384 ms
1 1 0 218 2.11 s 526.88 ms 131.72 ms 32.768 ms
1 1 1 219 4.22 s 1.05 s 263.44 ms 65.536 ms
Bit 7 6 5 4 3 2 1 Bit 0
RTIF 0 0 0 0 0 0 0
RESET: 0 0 0 0 0 0 0 0
RTIFLG — Real Time Interrupt Flag Register $0015
Clock Function Registers
CME — Clock Monitor Enable Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
0 = Clock monitor is disabled. Slow clocks and stop instruction may be used.
1 = Slow or stopped clocks (including the stop instruction) will cause a clock reset sequence or limp-home mode. See Limp-Home and Fast STOP Recovery modes.
On reset
CME is 1 if VDDPLL is high CME is 0 if VDDPLL is low.
NOTE: The VDDPLL-dependent reset operation is not implemented on first pass products.
In this case the state of CME on reset is 0.
FCME — Force Clock Monitor Enable
Write once in normal modes, anytime in special modes. Read anytime.
In normal modes, when this bit is set, the clock monitor function cannot be disabled until a reset occurs.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence or limp-home mode.
See Limp-Home and Fast STOP Recovery modes.
Bit 7 6 5 4 3 2 1 Bit 0
CME FCME FCMCOP WCOP DISR CR2 CR1 CR0
RESET: 0/1 0 0 0 0 1 1 1 Normal
RESET: 0/1 0 0 0 1 1 1 1 Special
COPCTL — COP Control Register $0016
FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = A clock monitor failure reset or a COP failure reset is forced depending on the state of CME and if COP is enabled.
WCOP — Window COP mode
Write once in normal modes, anytime in special modes. Read anytime.
0 = Normal COP operation 1 = Window COP operation
When set, a write to the COPRST register must occur in the last 25%
of the selected period. A premature write will also reset the part. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written the time-out logic restarts and the user must wait until the next window before writing to COPRST.
Please note, there is a fixed time uncertainty about the exact COP counter state when reset, as the initial prescale clock divider in the RTI section is not cleared when the COP counter is cleared. This means the effective window is reduced by this uncertainty. Table 12-5 below shows the exact duration of this window for the seven available COP rates.
CME COP enabled Forced reset
0 0 none
0 1 COP failure
1 0 Clock monitor failure
1 1 Both(1)
1. Highest priority interrupt vector is serviced.
Clock Function Registers
DISR — Disable Resets from COP Watchdog and Clock Monitor Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor will not generate a system reset.
CR2, CR1, CR0 — COP Watchdog Timer Rate select bits
These bits select the COP time-out rate. The clock used for this module is the XCLK.
Write once in normal modes, anytime in special modes. Read anytime.
Table 12-5. COP Watchdog Rates
CR2 CR1 CR0
Divide XCLK
by
8.0 MHz XCLK Time-out
Window COP enabled:
Window start
(1) Window end Effective Window (2)
0 0 0 OFF OFF OFF OFF OFF
0 0 1 2 13 1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms 0 % (3) 0 1 0 2 15 4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 % 0 1 1 2 17 16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.4 % 1 0 0 2 19 65.536 ms -0/+1.024 ms 49.152 ms 64.512 ms 23.4 % 1 0 1 2 21 262.144 ms -0/+1.024 ms 196.608 ms 261.120 ms 24.6 % 1 1 0 2 22 524.288 ms -0/+1.024 ms 393.216 ms 523.264 ms 24.8 % 1 1 1 2 23 1.048576 ms -0/+1.024 ms 786.432 ms 1.047552 s 24.9 % 1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.
2. Please refer to WCOP bit description above.
3. Window COP cannot be used at this rate.
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog sequence.
Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may be executed between these writes but both must be completed in the correct order prior to time-out to avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur.
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
RESET: 0 0 0 0 0 0 0 0
COPRST — Arm/Reset COP Timer Register $0017
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