Pinout and Signal Descriptions
Section 13. Oscillator
Contents
mask set. This implementation, described in section 13.5
MC68HC912Dx128P Pierce Oscillator Specification, utilises the
Automatic Level Control circuit to provide a lower power oscillator than traditional Pierce oscillators based on simple inverter circuits. In this section of the document, the term MC68HC912Dx128P refers only to the MC68HC912DT128P and MC68HC912DG128P devices.
In the following sections, each particular oscillator implementation is described in detail. Refer to the appropriate sections for the mask set being used and optimum external component selection.
13.3 MC68HC912DT128A Oscillator Specification
This section applies to the 0L05H mask set and all previous MC68HC912DT128A versions.
13.3.1 MC68HC912DT128A Oscillator Design Architecture
The Colpitts oscillator architecture is shown in Figure 13-1. The component configuration for this oscillator is the same as all previous MC68HC912DT128A configurations.
MC68HC912DT128A Oscillator Specification
Figure 13-1. MC68HC912DT128A Colpitts Oscillator Architecture
ALC + -
OTA + -
CFLT RFLT
EN BIAS
Resonator CX-EX
CX-VSS
BUF
RFLT CFLT
2
GM
EXTAL XTAL
RESD
13.3.2 MC68HC912DT128A Oscillator Design Guidelines
Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting
oscillators, and reaction to noise on the clock input buffer. In addition to published errata for the MC68HC912DT128A, the following guidelines must be followed or failure in operation may occur.
• Minimize Capacitance to VSS on EXTAL pin — The Colpitts oscillator architecture is sensitive to capacitance in parallel with the resonator (from EXTAL to VSS). Follow these techniques:
i. Remove ground plane from all layers around resonator and EXTAL route
ii. Observe a minimum spacing from the EXTAL trace to all other traces of at least three times the design rule minimum (until the microcontroller’s pin pitch prohibits this guideline)
iii. Where possible, use XTAL as a shield between EXTAL and VSS
iv. Keep EXTAL capacitance to less than 1pF (2pF absolute maximum)
• Shield all oscillator components from all noisy traces (while observing above guideline).
• Keep the VSSPLL pin and the VSS reference to the oscillator as identical as possible. Impedance between these signals must be minimum.
• Observe best practice supply bypassing on all MCU power pins. The oscillator’s supply reference is VDD, not VDPLL.
• Account for XTAL–VSS and EXTAL–XTAL parasitics in component values.
NOTE: An increase in the EXTAL–XTAL parasitic as a result of reducing EXTAL–VSS parasitic is acceptable provided component value is reduced by the appropriate value.
• Minimize XTAL and EXTAL routing lengths to reduce EMC issues.
MC68HC912Dx128C Colpitts Oscillator Specification
NOTE: EXTAL and XTAL routing resistances are less important than
capacitances. Using minimum width traces is an acceptable trade-off to reduce capacitance.
13.4 MC68HC912Dx128C Colpitts Oscillator Specification
This section applies to the 1L05H mask set, which refers to the newest set of CGM improvements (to the MC68HC912DT128A) with the Colpitts oscillator configuration enabled. The name for these devices is
MC68HC912Dx128C.
13.4.1 MC68HC912Dx128C Oscillator Design Architecture
The Colpitts oscillator architecture is shown in Figure 13-2. The component configuration for this oscillator is the same as all previous MC68HC912DT128A configurations, although the recommended component values may be different.
Figure 13-2. MC68HC912Dx128C Colpitts Oscillator Architecture
There are the following primary differences between the previous (’A’) and new (’C’) Colpitts oscillator configurations:
• Hysteresis was added to the clock input buffer to reduce sensitivity to noise
• Internal parasitics were reduced from EXTAL to VSS to increase oscillator gain margin.
ALC + -
OTA + -
CFLT RFLT
EN BIAS
Resonator CX-EX
CX-VSS
BUF
RFLT CFLT
2
GM
EXTAL XTAL
RESD
MC68HC912Dx128C Colpitts Oscillator Specification
• The bias current to the amplifier was optimized for less variation over process.
• The input ESD resistor from EXTAL to the gate of the oscillator amplifier was changed to provide a parallel path, reducing parasitic phase shift in the oscillator.
13.4.1.1 Clock Buffer Hysteresis
The input clock buffer uses an Operational Transconductance Amplifier (labeled ‘OTA’ in the figure above) followed by a digital buffer to amplify the input signal on the EXTAL pin into a full-swing clock for use by the clock generation section of the microcontroller. There is an internal R-C filter (composed of components RFLT2 and CFLT2 in the figure above), which creates the DC value to which the EXTAL signal is compared. In this manner, the clock input buffer can track changes in the EXTAL bias voltage due to process variation as well as external factors such as leakage.
Because the purpose of the clock input buffer is to amplify relatively low-swing signals into a full-rail output, the gain of the OTA is very high. In the configuration shown, this means that very small levels of noise can be coupled onto the input of the clock buffer resulting in noise
amplification.
To remedy this issue, hysteresis was added to the OTA so that the circuit could still provide the tolerance to leakage and the high gain required without the noise sensitivity. Approximately 150mV of hysteresis was added with a maximum hysteresis over process variation of 350mV. As such, the clock input buffer will not respond to input signals until they exceed the hysteresis level. At this point, the input signal due to oscillation will dominate the total input waveform and narrow clock pulses due to noise will be eliminated.
This circuit will limit the overall performance of the oscillator block only in cases where the amplitude of oscillation is less than the level of hysteresis. The minimum amplitude of oscillation is expected to be in excess of 750mV and the maximum hysteresis is expected to be less than 350mV, providing a factor of safety in excess of two.
13.4.1.2 Internal Parasitic Reduction
Any oscillator circuit’s gain margin is reduced when a low AC-impedance (low resistance or high capacitance) is placed in parallel with the resonator. In the Colpitts oscillator configuration, this impedance is dominated by the parasitic capacitance from the EXTAL pin to VSS.
Since this capacitance is large compared to the shunt capacitance of the resonator, the gain margin in a Colpitts configuration is less than in other configurations.
To remedy this issue, the internal circuits were optimized for lower capacitance. This should increase the gain margin and allow more robust operation over process, temperature and voltage variation. To maximize the benefit of this change, different external component values are required. However, the oscillator will function at least as well as the MC68HC912DT128A version with the same components.
13.4.1.3 Bias Current Process Optimization
For proper oscillation, the gain margin of the oscillator must exceed one or the circuit will not oscillate. Due to the sensitive gain margin of the Colpitts configuration, process variance in the bias current (which controls the gain of the amplifier) can cause the gain margin to be much lower than typical. This can be as a result of either too much or too little current.
To reduce the process sensitivity of the gain, the material of the device that sets the bias current was changed to a material with tighter process and temperature control. As a result, the transconductance and Ibias variances are more limited than in the previous design.
MC68HC912Dx128C Colpitts Oscillator Specification
13.4.1.4 Input ESD Resistor Path Modification
To satisfy the condition of oscillation, the oscillator circuit must not only provide the correct amount of gain but also the correct amount of phase shift. In the Colpitts configuration, the phase shift due to parasitics in the input path to the gate of the transconductance amplifier must be as low as possible. In the original configuration, the parasitic capacitance of the clock input buffer (OTA), automatic Loop Control circuit (ALC), and input resistors (RFLT and RFLT2) reacted with the input resistance to cause a large phase shift.
To reduce the phase shift, the input ESD resistor (marked RESD in the figure above) was changed from a single path to the input circuitry (the ALC and the OTA) and oscillator transconductance amplifier (marked GM in the figure above) to a parallel path. In this configuration, the only capacitance causing a phase shift on the input to the transconductance device is due to the transconductance device itself.
13.4.2 MC68HC912Dx128C Oscillator Circuit Specifications
13.4.2.1 Negative Resistance Margin
Negative Resistance Margin (NRM) is a figure of merit commonly used to qualify an oscillator circuit with a given resonator. NRM is an indicator of how much additional resistance in series with the resonator is
tolerable while still maintaining oscillation. This figure is usually expected to be a multiple of the nominal "maximum" rated ESR of the resonator to allow for variation and degradation of the resonator.
Currently, many systems are optimized for NRM by adjusting the load capacitors until NRM is maximized. This method may not achieve the best overall NRM because the optimization method is empirical and not analytical. That is, the method only achieves the best NRM for the particular sample set of microcontrollers, resonators, and board values tested. The figure below shows the anticipated NRM for a nominal 4MHz resonator given the expected process variance of the microcontroller (D60A), board, and crystal (excluding ESR). In this case, the value of load capacitors providing the optimum NRM for a best-case situation