PLL Register Descriptions

Read anytime, write anytime, except when BCSP = 1 (PLL selected as bus clock).

If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the bus frequency from the PLL reference frequency by SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution should be used not to exceed the maximum rated operating frequency for the CPU.

Read anytime, write anytime, except when BCSP = 1.

The reference divider bits provides a finer granularity for the PLL multiplier steps. The reference frequency is divided by REFDV + 1.

Always reads zero, except in test modes.

Bit 7 6 5 4 3 2 1 Bit 0

0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

RESET: 0 0 0 0 0 0 0 0

SYNR — Synthesizer Register $0038

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 REFDV2 REFDV1 REFDV0

RESET: 0 0 0 0 0 0 0 0

REFDV — Reference Divider Register $0039

Bit 7 6 5 4 3 2 1 Bit 0

TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0

RESET: 0 0 0 0 0 0 0 0

CGTFLG — Clock Generator Test Register $003A

Read anytime, refer to each bit for write conditions.

LOCKIF — PLL Lock Interrupt Flag 0 = No change in LOCK bit.

1 = LOCK condition has changed, either from a locked state to an unlocked state or vice versa.

To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home mode.

LOCK — Locked Phase Lock Loop Circuit

Regardless of the bandwidth control mode (automatic or manual):

0 = PLL VCO is not within the desired tolerance of the target frequency.

1 = After the phase lock loop circuit is turned on, indicates the PLL VCO is within the desired tolerance of the target frequency.

Write has no effect on LOCK bit. This bit is cleared in limp-home mode as the lock detector cannot operate without the reference frequency.

LHIF — Limp-Home Interrupt Flag 0 = No change in LHOME bit.

1 = LHOME condition has changed, either entered or exited limp-home mode.

To clear the flag, write one to this bit in PLLFLG.

LHOME — Limp-Home Mode Status

0 = MCU is operating normally, with EXTALi clock available for generating clocks or as PLL reference.

1 = Loss of reference clock. CGM delivers PLL VCO limp-home frequency to the MCU.

For Limp-Home mode, see Limp-Home and Fast STOP Recovery modes.

Bit 7 6 5 4 3 2 1 Bit 0

LOCKIF LOCK 0 0 0 0 LHIF LHOME

RESET: 0 0 0 0 0 0 0 0

PLLFLG — PLL Flags $003B

Limp-Home and Fast STOP Recovery modes

Read and write anytime. Exceptions are listed below for each bit.

LOCKIE — PLL LOCK Interrupt Enable 0 = PLL LOCK interrupt is disabled 1 = PLL LOCK interrupt is enabled Forced to 0 when VDDPLL=0.

PLLON — Phase Lock Loop On 0 = Turns the PLL off.

1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will lock automatically.

Cannot be cleared when BCSP = 1 (PLL selected as bus clock). Forced to 0 when VDDPLL is at VSS level. In limp-home mode, the output of PLLON is forced to 1, but the PLLON bit reads the latched value.

AUTO — Automatic Bandwidth Control

0 = Automatic Mode Control is disabled and the PLL is under software control, using ACQ bit.

1 = Automatic Mode Control is enabled. ACQ bit is read only.

Automatic bandwidth control selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. See Electrical Specifications.

Bit 7 6 5 4 3 2 1 Bit 0

LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM

RESET: 0 —⁽¹⁾ 1 0 0 0 0 —⁽²⁾

PLLCR — PLL Control Register $003C

1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.

2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.

ACQ — Not in Acquisition

If AUTO = 1 (ACQ is Read Only)

0 = PLL VCO is not within the desired tolerance of the target frequency. The loop filter is in high bandwidth, acquisition mode.

1 = After the phase lock loop circuit is turned on, indicates the PLL VCO is within the desired tolerance of the target frequency.

The loop filter is in low bandwidth, tracking mode.

If AUTO = 0

0 = High bandwidth PLL loop selected 1 = Low bandwidth PLL loop selected PSTP — Pseudo-STOP Enable

0 = Pseudo-STOP oscillator mode is disabled 1 = Pseudo-STOP oscillator mode is enabled

In Pseudo-STOP mode, the oscillator is still running while the MCU is maintained in STOP mode. This allows for a faster STOP recovery and reduces the mechanical stress and aging of the resonator in case frequent STOP conditions at the expense of a slightly increased power consumption.

LHIE — Limp-Home Interrupt Enable 0 = Limp-Home interrupt is disabled 1 = Limp-Home interrupt is enabled Forced to 0 when VDDPLL is at VSS level.

NOLHM —No Limp-Home Mode

0 = Loss of reference clock forces the MCU in limp-home mode.

1 = Loss of reference clock causes standard Clock Monitor reset.

Read anytime; Normal modes: write once; Special modes: write anytime. Forced to 1 when VDDPLL is at VSS level.

Limp-Home and Fast STOP Recovery modes

Read and write anytime. Exceptions are listed below for each bit.

BCSP and BCSS bits determine the clock used by the main system including the CPU and buses.

BCSP — Bus Clock Select PLL

0 = SYSCLK is derived from the crystal clock or from SLWCLK.

1 = SYSCLK source is the PLL.

Cannot be set when PLLON = 0. In limp-home mode, the output of BCSP is forced to 1, but the BCSP bit reads the latched value.

BCSS — Bus Clock Select Slow

0 = SYSCLK is derived from the crystal clock EXTALi.

1 = SYSCLK source is the Slow clock SLWCLK.

This bit has no effect when BCSP is set.

MCS — Module Clock Select

0 = M clock is the same as PCLK.

1 = M clock is derived from Slow clock SLWCLK.

This bit determines the clock used by the ECT module and the baud rate generators of the SCIs. In limp-home mode, the output of MCS is forced to 0, but the MCS bit reads the latched value.

Bit 7 6 5 4 3 2 1 Bit 0

0 BCSP BCSS 0 0 MCS 0 0

RESET: 0 0 0 0 0 0 0 0

CLKSEL — Clock Generator Clock select Register $003D

Read and write anytime.

A write to this register changes the SLWCLK frequency with minimum delay (less than one SLWCLK cycle), thus allowing immediate tune-up of the performance versus power consumption for the modules using this clock. The frequency divide ratio is 2 times (SLOW), hence the divide range is 2 to 126 (not on first pass products). When SLOW = 0, the divider is bypassed. The generation of E, P and M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252, by steps of 4. SLWCLK is a 50% duty cycle signal.

Bit 7 6 5 4 3 2 1 Bit 0

0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0

RESET: 0 0 0 0 0 0 0 0

SLOW — Slow mode Divider Register $003E

System Clock Frequency Formulae